From patchwork Thu Sep 23 05:46:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: liuhongt X-Patchwork-Id: 1531551 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=K1UuEInA; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4HFPTk3bwjz9sW4 for ; Thu, 23 Sep 2021 15:53:13 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 805FB3858425 for ; Thu, 23 Sep 2021 05:53:10 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 805FB3858425 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1632376390; bh=WIy7GQVEiEf9KxFdEk6IWlvQy+17S679nNH4HTQXpBM=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=K1UuEInAGl0RIXxTvmG7QH6empWrZ/ANj5PG7Ne3DvF0QCGA0WsMkB/TpBjzrlljG gnzEnWjnkdTkuEbWnp/osnB1bkqe+ADrgnYKzsHdyZNd1mVzz8Ln1y0dEjS/C3O3sx CDanaIZAXpvynWw6ObREz5WGZFw6s6VSC9ZKRRlA= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by sourceware.org (Postfix) with ESMTPS id DF45A3858025 for ; Thu, 23 Sep 2021 05:46:50 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org DF45A3858025 X-IronPort-AV: E=McAfee;i="6200,9189,10115"; a="210846888" X-IronPort-AV: E=Sophos;i="5.85,316,1624345200"; d="scan'208";a="210846888" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Sep 2021 22:46:50 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,316,1624345200"; d="scan'208";a="704434569" Received: from scymds01.sc.intel.com ([10.148.94.138]) by fmsmga005.fm.intel.com with ESMTP; 22 Sep 2021 22:46:50 -0700 Received: from shliclel219.sh.intel.com (shliclel219.sh.intel.com [10.239.236.219]) by scymds01.sc.intel.com with ESMTP id 18N5keO9025461; Wed, 22 Sep 2021 22:46:49 -0700 To: gcc-patches@gcc.gnu.org Subject: [PATCH 6/7] AVX512FP16: add truncmn2/extendmn2 expanders Date: Thu, 23 Sep 2021 13:46:39 +0800 Message-Id: <20210923054640.1406227-7-hongtao.liu@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210923054640.1406227-1-hongtao.liu@intel.com> References: <20210923054640.1406227-1-hongtao.liu@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: liuhongt via Gcc-patches From: liuhongt Reply-To: liuhongt Cc: Hongyu Wang Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" From: Hongyu Wang gcc/ChangeLog: * config/i386/sse.md (extend2): New expander. (extendv4hf2): Likewise. (extendv2hfv2df2): Likewise. (trunc2): Likewise. (avx512fp16_vcvt2ph_): Rename to ... (truncv4hf2): ... this, and drop constraints. (avx512fp16_vcvtpd2ph_v2df): Rename to ... (truncv2dfv2hf2): ... this, and likewise. gcc/testsuite/ChangeLog: * gcc.target/i386/avx512fp16-trunc-extendvnhf.c: New test. --- gcc/config/i386/sse.md | 75 +++++++++++++++++-- .../i386/avx512fp16-trunc-extendvnhf.c | 55 ++++++++++++++ 2 files changed, 123 insertions(+), 7 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16-trunc-extendvnhf.c diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 66062dc3bcf..a48c8e8bede 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -6328,6 +6328,12 @@ (define_mode_attr ph2pssuffix [(V16SF "x") (V8SF "x") (V4SF "x") (V8DF "") (V4DF "") (V2DF "")]) +(define_expand "extend2" + [(set (match_operand:VF48H_AVX512VL 0 "register_operand") + (float_extend:VF48H_AVX512VL + (match_operand: 1 "nonimmediate_operand")))] + "TARGET_AVX512FP16") + (define_insn "avx512fp16_float_extend_ph2" [(set (match_operand:VF48H_AVX512VL 0 "register_operand" "=v") (float_extend:VF48H_AVX512VL @@ -6338,6 +6344,21 @@ (define_insn "avx512fp16_float_extend_ph2" (set_attr "prefix" "evex") (set_attr "mode" "")]) +(define_expand "extendv4hf2" + [(set (match_operand:VF4_128_8_256 0 "register_operand") + (float_extend:VF4_128_8_256 + (match_operand:V4HF 1 "nonimmediate_operand")))] + "TARGET_AVX512FP16 && TARGET_AVX512VL" +{ + if (!MEM_P (operands[1])) + { + operands[1] = lowpart_subreg (V8HFmode, operands[1], V4HFmode); + emit_insn (gen_avx512fp16_float_extend_ph2 + (operands[0], operands[1])); + DONE; + } +}) + (define_insn "avx512fp16_float_extend_ph2" [(set (match_operand:VF4_128_8_256 0 "register_operand" "=v") (float_extend:VF4_128_8_256 @@ -6360,6 +6381,21 @@ (define_insn "*avx512fp16_float_extend_ph2_load" (set_attr "prefix" "evex") (set_attr "mode" "")]) +(define_expand "extendv2hfv2df2" + [(set (match_operand:V2DF 0 "register_operand") + (float_extend:V2DF + (match_operand:V2HF 1 "nonimmediate_operand")))] + "TARGET_AVX512FP16 && TARGET_AVX512VL" +{ + if (!MEM_P (operands[1])) + { + operands[1] = lowpart_subreg (V8HFmode, operands[1], V2HFmode); + emit_insn (gen_avx512fp16_float_extend_phv2df2 + (operands[0], operands[1])); + DONE; + } +}) + (define_insn "avx512fp16_float_extend_phv2df2" [(set (match_operand:V2DF 0 "register_operand" "=v") (float_extend:V2DF @@ -6382,6 +6418,12 @@ (define_insn "*avx512fp16_float_extend_phv2df2_load" (set_attr "prefix" "evex") (set_attr "mode" "TI")]) +(define_expand "trunc2" + [(set (match_operand: 0 "register_operand") + (float_truncate: + (match_operand:VF48H_AVX512VL 1 "nonimmediate_operand")))] + "TARGET_AVX512FP16") + (define_insn "avx512fp16_vcvt2ph_" [(set (match_operand: 0 "register_operand" "=v") (float_truncate: @@ -6392,11 +6434,21 @@ (define_insn "avx512fp16_vcvt2ph_" (set_attr "prefix" "evex") (set_attr "mode" "")]) -(define_expand "avx512fp16_vcvt2ph_" - [(set (match_operand:V8HF 0 "register_operand" "=v") +(define_expand "truncv4hf2" + [(set (match_operand:V4HF 0 "register_operand") + (float_truncate:V4HF (match_operand:VF4_128_8_256 1 "vector_operand")))] + "TARGET_AVX512FP16 && TARGET_AVX512VL" +{ + operands[0] = lowpart_subreg (V8HFmode, operands[0], V4HFmode); + emit_insn (gen_avx512fp16_truncv4hf2 (operands[0], operands[1])); + DONE; +}) + +(define_expand "avx512fp16_truncv4hf2" + [(set (match_operand:V8HF 0 "register_operand") (vec_concat:V8HF (float_truncate:V4HF - (match_operand:VF4_128_8_256 1 "vector_operand" "vm")) + (match_operand:VF4_128_8_256 1 "vector_operand")) (match_dup 2)))] "TARGET_AVX512FP16 && TARGET_AVX512VL" "operands[2] = CONST0_RTX (V4HFmode);") @@ -6461,11 +6513,20 @@ (define_insn "*avx512fp16_vcvt2ph__mask_1" (set_attr "prefix" "evex") (set_attr "mode" "")]) -(define_expand "avx512fp16_vcvtpd2ph_v2df" - [(set (match_operand:V8HF 0 "register_operand" "=v") +(define_expand "truncv2dfv2hf2" + [(set (match_operand:V2HF 0 "register_operand") + (float_truncate:V2HF (match_operand:V2DF 1 "vector_operand")))] + "TARGET_AVX512FP16 && TARGET_AVX512VL" +{ + operands[0] = lowpart_subreg (V8HFmode, operands[0], V2HFmode); + emit_insn (gen_avx512fp16_truncv2dfv2hf2 (operands[0], operands[1])); + DONE; +}) + +(define_expand "avx512fp16_truncv2dfv2hf2" + [(set (match_operand:V8HF 0 "register_operand") (vec_concat:V8HF - (float_truncate:V2HF - (match_operand:V2DF 1 "vector_operand" "vm")) + (float_truncate:V2HF (match_operand:V2DF 1 "vector_operand")) (match_dup 2)))] "TARGET_AVX512FP16 && TARGET_AVX512VL" "operands[2] = CONST0_RTX (V6HFmode);") diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-trunc-extendvnhf.c b/gcc/testsuite/gcc.target/i386/avx512fp16-trunc-extendvnhf.c new file mode 100644 index 00000000000..286ea9f2624 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-trunc-extendvnhf.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512vl -ftree-slp-vectorize -mprefer-vector-width=512" } */ + +extern double df[8]; +extern float sf[16]; +extern _Float16 hf[32]; + +#define DO_PRAGMA(X) _Pragma(#X) + +#define TRUNCHFVV(size, mode) \ + void __attribute__ ((noinline, noclone)) \ +truncv##size##mode##v##size##hf () \ +{\ + int i; \ + DO_PRAGMA (GCC unroll size) \ + for (i = 0; i < size; i++) \ + hf[i] = mode[i]; \ +} + +#define EXTENDHFVV(size, mode) \ + void __attribute__ ((noinline, noclone)) \ +extendv##size##hf##v##size##mode () \ +{\ + int i; \ + DO_PRAGMA (GCC unroll size) \ + for (i = 0; i < size; i++) \ + mode[i] = hf[i]; \ +} + +TRUNCHFVV(8, df) +TRUNCHFVV(4, df) +TRUNCHFVV(2, df) +TRUNCHFVV(16, sf) +TRUNCHFVV(8, sf) +TRUNCHFVV(4, sf) +EXTENDHFVV(8, df) +EXTENDHFVV(4, df) +EXTENDHFVV(2, df) +EXTENDHFVV(16, sf) +EXTENDHFVV(8, sf) +EXTENDHFVV(4, sf) + +/* { dg-final { scan-assembler-times "vcvtpd2phz\[ \\t\]+\[^\{\n\]*\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtpd2phy\[ \\t\]+\[^\{\n\]*\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-times "vcvtpd2phx\[ \\t\]+\[^\{\n\]*\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-times "vcvtps2phx\[ \\t\]+\[^\{\n\]*\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtps2phxy\[ \\t\]+\[^\{\n\]*\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtps2phxx\[ \\t\]+\[^\{\n\]*\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-times "vcvtph2pd\[ \\t\]+\[^\{\n\]*\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2pd\[ \\t\]+\[^\{\n\]*\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-times "vcvtph2pd\[ \\t\]+\[^\{\n\]*\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-times "vcvtph2psx\[ \\t\]+\[^\{\n\]*\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2psx\[ \\t\]+\[^\{\n\]*\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2psx\[ \\t\]+\[^\{\n\]*\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 { xfail *-*-* } } } */ +