From patchwork Thu Sep 23 05:46:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: liuhongt X-Patchwork-Id: 1531550 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=k+n/ukhO; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (ip-8-43-85-97.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4HFPS412vWz9sRN for ; Thu, 23 Sep 2021 15:51:48 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D41DE3858025 for ; Thu, 23 Sep 2021 05:51:45 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org D41DE3858025 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1632376305; bh=SfVS/NbnYsAhOVBhiQv76wlVuDD9BOew6PN4YpdxFtQ=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=k+n/ukhOzZzhHJOL1nSDLXNVtx+MK9XKpvqTG6Iy7J06cGqpoBa2t+wXX8gt9xm5b DJBenDvGbn68Nm7pmLSUWpCgRX5WA1oYJMe577KNwvv64MICyiDuDXhFiiljFgVZc4 OfA3Y9cXV5MCeaxelQVq8F9l8sNHWxSIR57ixU+o= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by sourceware.org (Postfix) with ESMTPS id 3A329385802E for ; Thu, 23 Sep 2021 05:46:49 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 3A329385802E X-IronPort-AV: E=McAfee;i="6200,9189,10115"; a="203267416" X-IronPort-AV: E=Sophos;i="5.85,316,1624345200"; d="scan'208";a="203267416" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Sep 2021 22:46:48 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,316,1624345200"; d="scan'208";a="558108848" Received: from scymds01.sc.intel.com ([10.148.94.138]) by fmsmga002.fm.intel.com with ESMTP; 22 Sep 2021 22:46:48 -0700 Received: from shliclel219.sh.intel.com (shliclel219.sh.intel.com [10.239.236.219]) by scymds01.sc.intel.com with ESMTP id 18N5keO8025461; Wed, 22 Sep 2021 22:46:47 -0700 To: gcc-patches@gcc.gnu.org Subject: [PATCH 5/7] AVX512FP16: Add float(uns)?mn2 expander Date: Thu, 23 Sep 2021 13:46:38 +0800 Message-Id: <20210923054640.1406227-6-hongtao.liu@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210923054640.1406227-1-hongtao.liu@intel.com> References: <20210923054640.1406227-1-hongtao.liu@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_SHORT, SPF_HELO_PASS, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: liuhongt via Gcc-patches From: liuhongt Reply-To: liuhongt Cc: Hongyu Wang Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" From: Hongyu Wang gcc/ChangeLog: * config/i386/sse.md (float2): New expander. (avx512fp16_vcvt2ph_): Rename to ... (floatv4hf2): ... this, and drop constraints. (avx512fp16_vcvtqq2ph_v2di): Rename to ... (floatv2div2hf2): ... this, and likewise. gcc/testsuite/ChangeLog: * gcc.target/i386/avx512fp16-floatvnhf.c: New test. --- gcc/config/i386/sse.md | 46 +++++++++++--- .../gcc.target/i386/avx512fp16-floatvnhf.c | 61 +++++++++++++++++++ 2 files changed, 99 insertions(+), 8 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16-floatvnhf.c diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index f8a5f197f3c..66062dc3bcf 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -6006,6 +6006,12 @@ (define_insn "avx512fp16_vcvtph2_< (set_attr "prefix" "evex") (set_attr "mode" "")]) +(define_expand "float2" + [(set (match_operand: 0 "register_operand") + (any_float: + (match_operand:VI2H_AVX512VL 1 "nonimmediate_operand")))] + "TARGET_AVX512FP16") + (define_insn "avx512fp16_vcvt2ph_" [(set (match_operand: 0 "register_operand" "=v") (any_float: @@ -6016,11 +6022,23 @@ (define_insn "avx512fp16_vcvt2ph_")]) -(define_expand "avx512fp16_vcvt2ph_" - [(set (match_operand:V8HF 0 "register_operand" "=v") +(define_expand "floatv4hf2" + [(set (match_operand:V4HF 0 "register_operand") + (any_float:V4HF + (match_operand:VI4_128_8_256 1 "vector_operand")))] + "TARGET_AVX512FP16 && TARGET_AVX512VL" +{ + operands[0] = lowpart_subreg (V8HFmode, operands[0], V4HFmode); + emit_insn (gen_avx512fp16_floatv4hf2 (operands[0], + operands[1])); + DONE; +}) + +(define_expand "avx512fp16_floatv4hf2" + [(set (match_operand:V8HF 0 "register_operand") (vec_concat:V8HF - (any_float:V4HF (match_operand:VI4_128_8_256 1 "vector_operand" "vm")) - (match_dup 2)))] + (any_float:V4HF (match_operand:VI4_128_8_256 1 "vector_operand")) + (match_dup 2)))] "TARGET_AVX512FP16 && TARGET_AVX512VL" "operands[2] = CONST0_RTX (V4HFmode);") @@ -6079,11 +6097,23 @@ (define_insn "*avx512fp16_vcvt2ph__mask_1" (set_attr "prefix" "evex") (set_attr "mode" "")]) -(define_expand "avx512fp16_vcvtqq2ph_v2di" - [(set (match_operand:V8HF 0 "register_operand" "=v") +(define_expand "floatv2div2hf2" + [(set (match_operand:V2HF 0 "register_operand") + (any_float:V2HF + (match_operand:V2DI 1 "vector_operand")))] + "TARGET_AVX512FP16 && TARGET_AVX512VL" +{ + operands[0] = lowpart_subreg (V8HFmode, operands[0], V2HFmode); + emit_insn (gen_avx512fp16_floatv2div2hf2 (operands[0], + operands[1])); + DONE; +}) + +(define_expand "avx512fp16_floatv2div2hf2" + [(set (match_operand:V8HF 0 "register_operand") (vec_concat:V8HF - (any_float:V2HF (match_operand:V2DI 1 "vector_operand" "vm")) - (match_dup 2)))] + (any_float:V2HF (match_operand:V2DI 1 "vector_operand")) + (match_dup 2)))] "TARGET_AVX512FP16 && TARGET_AVX512VL" "operands[2] = CONST0_RTX (V6HFmode);") diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-floatvnhf.c b/gcc/testsuite/gcc.target/i386/avx512fp16-floatvnhf.c new file mode 100644 index 00000000000..112ac3e74d5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-floatvnhf.c @@ -0,0 +1,61 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512vl -ftree-slp-vectorize -mprefer-vector-width=512" } */ + +extern long long di[8]; +extern unsigned long long udi[8]; +extern int si[16]; +extern unsigned int usi[16]; +extern short hi[32]; +extern unsigned short uhi[32]; +extern _Float16 hf[32]; + +#define DO_PRAGMA(X) _Pragma(#X) + +#define FLOATHFVV(size, mode) \ + void __attribute__ ((noinline, noclone)) \ +float##v##size##mode##v##size##hf () \ +{\ + int i; \ + DO_PRAGMA (GCC unroll size) \ + for (i = 0; i < size; i++) \ + hf[i] = (_Float16) mode[i]; \ +} + +FLOATHFVV(32, hi) +FLOATHFVV(16, hi) +FLOATHFVV(8, hi) +FLOATHFVV(16, si) +FLOATHFVV(8, si) +FLOATHFVV(4, si) +FLOATHFVV(8, di) +FLOATHFVV(4, di) +FLOATHFVV(2, di) + +FLOATHFVV(32, uhi) +FLOATHFVV(16, uhi) +FLOATHFVV(8, uhi) +FLOATHFVV(16, usi) +FLOATHFVV(8, usi) +FLOATHFVV(4, usi) +FLOATHFVV(8, udi) +FLOATHFVV(4, udi) +FLOATHFVV(2, udi) + +/* { dg-final { scan-assembler-times "vcvtqq2phz\[ \\t\]+\[^\{\n\]*\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtuqq2phz\[ \\t\]+\[^\{\n\]*\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtqq2phy\[ \\t\]+\[^\{\n\]*\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-times "vcvtuqq2phy\[ \\t\]+\[^\{\n\]*\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-times "vcvtqq2phx\[ \\t\]+\[^\{\n\]*\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-times "vcvtuqq2phx\[ \\t\]+\[^\{\n\]*\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-times "vcvtdq2ph\[ \\t\]+\[^\{\n\]*\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtudq2ph\[ \\t\]+\[^\{\n\]*\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtdq2phy\[ \\t\]+\[^\{\n\]*\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtudq2phy\[ \\t\]+\[^\{\n\]*\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtdq2phx\[ \\t\]+\[^\{\n\]*\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-times "vcvtudq2phx\[ \\t\]+\[^\{\n\]*\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-times "vcvtw2ph\[ \\t\]+\[^\{\n\]*\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtuw2ph\[ \\t\]+\[^\{\n\]*\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtw2ph\[ \\t\]+\[^\{\n\]*\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtuw2ph\[ \\t\]+\[^\{\n\]*\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtw2ph\[ \\t\]+\[^\{\n\]*\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtuw2ph\[ \\t\]+\[^\{\n\]*\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */