From patchwork Wed Sep 22 05:09:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: liuhongt X-Patchwork-Id: 1531038 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=DfeHBI3Q; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4HDmZ33LTGz9sRK for ; Wed, 22 Sep 2021 15:09:46 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C3FCB3858C27 for ; Wed, 22 Sep 2021 05:09:40 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org C3FCB3858C27 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1632287380; bh=gC0qWCzF937SsBxieoLCFGnhX3VkBkVdiz6+Pa1tzAE=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=DfeHBI3QkaPWN5vWyaQqfyJcF7XqsgsHgavd7vkByW53u2ETnHOCW1k/Ot6ZxlewN 6CcjO07hgvOm05XbdLqEG1aSwCXBQTuVixiKGdbYL7uZenXhE3d87ZxD7nr+9TtMOP faI067jZu8IPk/VY67NXtBfctpA1gyvNU5EtLvuk= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by sourceware.org (Postfix) with ESMTPS id B19423858D39 for ; Wed, 22 Sep 2021 05:09:19 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org B19423858D39 X-IronPort-AV: E=McAfee;i="6200,9189,10114"; a="210596975" X-IronPort-AV: E=Sophos;i="5.85,312,1624345200"; d="scan'208";a="210596975" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Sep 2021 22:09:18 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,312,1624345200"; d="scan'208";a="518458184" Received: from scymds01.sc.intel.com ([10.148.94.138]) by orsmga001.jf.intel.com with ESMTP; 21 Sep 2021 22:09:18 -0700 Received: from shliclel219.sh.intel.com (shliclel219.sh.intel.com [10.239.236.219]) by scymds01.sc.intel.com with ESMTP id 18M59Gpk002774; Tue, 21 Sep 2021 22:09:17 -0700 To: gcc-patches@gcc.gnu.org Subject: [PATCH] Support 64bit fma/fms/fnma/fnms under avx512vl. Date: Wed, 22 Sep 2021 13:09:16 +0800 Message-Id: <20210922050916.3877201-1-hongtao.liu@intel.com> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: liuhongt via Gcc-patches From: liuhongt Reply-To: liuhongt Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Hi: fma/fms/fnma/fnmsv2sf4 are defined only under (TARGET_FMA || TARGET_FMA4). The patch extend the expanders to TARGET_AVX512VL. Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}. Ok for trunk? gcc/ChangeLog: * config/i386/mmx.md (fmav2sf4): Extend to AVX512 fma. (fmsv2sf4): Ditto. (fnmav2sf4): Ditto. (fnmsv2sf4): Ditto. gcc/testsuite/ChangeLog: * gcc.target/i386/avx512vl-pr95046.c: New test. --- gcc/config/i386/i386.md | 4 +++- gcc/config/i386/mmx.md | 20 +++++++++++-------- .../gcc.target/i386/avx512vl-pr95046.c | 10 ++++++++++ 3 files changed, 25 insertions(+), 9 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-pr95046.c diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 188f431510a..c41fdd516c5 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -832,7 +832,7 @@ (define_attr "isa" "base,x64,nox64,x64_sse2,x64_sse4,x64_sse4_noavx, x64_avx,x64_avx512bw,x64_avx512dq, sse_noavx,sse2,sse2_noavx,sse3,sse3_noavx,sse4,sse4_noavx, avx,noavx,avx2,noavx2,bmi,bmi2,fma4,fma,avx512f,noavx512f, - avx512bw,noavx512bw,avx512dq,noavx512dq, + avx512bw,noavx512bw,avx512dq,noavx512dq,fma_or_avx512vl, avx512vl,noavx512vl,avxvnni,avx512vnnivl,avx512fp16" (const_string "base")) @@ -874,6 +874,8 @@ (define_attr "enabled" "" (eq_attr "isa" "bmi2") (symbol_ref "TARGET_BMI2") (eq_attr "isa" "fma4") (symbol_ref "TARGET_FMA4") (eq_attr "isa" "fma") (symbol_ref "TARGET_FMA") + (eq_attr "isa" "fma_or_avx512vl") + (symbol_ref "TARGET_FMA || TARGET_AVX512VL") (eq_attr "isa" "avx512f") (symbol_ref "TARGET_AVX512F") (eq_attr "isa" "noavx512f") (symbol_ref "!TARGET_AVX512F") (eq_attr "isa" "avx512bw") (symbol_ref "TARGET_AVX512BW") diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 2d3b63f0834..b0093778fc6 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -1019,12 +1019,13 @@ (define_insn "fmav2sf4" (match_operand:V2SF 1 "register_operand" "%0,v,x") (match_operand:V2SF 2 "register_operand" "v,v,x") (match_operand:V2SF 3 "register_operand" "v,0,x")))] - "(TARGET_FMA || TARGET_FMA4) && TARGET_MMX_WITH_SSE" + "(TARGET_FMA || TARGET_FMA4 || TARGET_AVX512VL) + && TARGET_MMX_WITH_SSE" "@ vfmadd132ps\t{%2, %3, %0|%0, %3, %2} vfmadd231ps\t{%2, %1, %0|%0, %1, %2} vfmaddps\t{%3, %2, %1, %0|%0, %1, %2, %3}" - [(set_attr "isa" "fma,fma,fma4") + [(set_attr "isa" "fma_or_avx512vl,fma_or_avx512vl,fma4") (set_attr "type" "ssemuladd") (set_attr "mode" "V4SF")]) @@ -1035,12 +1036,13 @@ (define_insn "fmsv2sf4" (match_operand:V2SF 2 "register_operand" "v,v,x") (neg:V2SF (match_operand:V2SF 3 "register_operand" "v,0,x"))))] - "(TARGET_FMA || TARGET_FMA4) && TARGET_MMX_WITH_SSE" + "(TARGET_FMA || TARGET_FMA4 || TARGET_AVX512VL) + && TARGET_MMX_WITH_SSE" "@ vfmsub132ps\t{%2, %3, %0|%0, %3, %2} vfmsub231ps\t{%2, %1, %0|%0, %1, %2} vfmsubps\t{%3, %2, %1, %0|%0, %1, %2, %3}" - [(set_attr "isa" "fma,fma,fma4") + [(set_attr "isa" "fma_or_avx512vl,fma_or_avx512vl,fma4") (set_attr "type" "ssemuladd") (set_attr "mode" "V4SF")]) @@ -1051,12 +1053,13 @@ (define_insn "fnmav2sf4" (match_operand:V2SF 1 "register_operand" "%0,v,x")) (match_operand:V2SF 2 "register_operand" "v,v,x") (match_operand:V2SF 3 "register_operand" "v,0,x")))] - "(TARGET_FMA || TARGET_FMA4) && TARGET_MMX_WITH_SSE" + "(TARGET_FMA || TARGET_FMA4 || TARGET_AVX512VL) + && TARGET_MMX_WITH_SSE" "@ vfnmadd132ps\t{%2, %3, %0|%0, %3, %2} vfnmadd231ps\t{%2, %1, %0|%0, %1, %2} vfnmaddps\t{%3, %2, %1, %0|%0, %1, %2, %3}" - [(set_attr "isa" "fma,fma,fma4") + [(set_attr "isa" "fma_or_avx512vl,fma_or_avx512vl,fma4") (set_attr "type" "ssemuladd") (set_attr "mode" "V4SF")]) @@ -1068,12 +1071,13 @@ (define_insn "fnmsv2sf4" (match_operand:V2SF 2 "register_operand" "v,v,x") (neg:V2SF (match_operand:V2SF 3 "register_operand" "v,0,x"))))] - "(TARGET_FMA || TARGET_FMA4) && TARGET_MMX_WITH_SSE" + "(TARGET_FMA || TARGET_FMA4 || TARGET_AVX512VL) + && TARGET_MMX_WITH_SSE" "@ vfnmsub132ps\t{%2, %3, %0|%0, %3, %2} vfnmsub231ps\t{%2, %1, %0|%0, %1, %2} vfnmsubps\t{%3, %2, %1, %0|%0, %1, %2, %3}" - [(set_attr "isa" "fma,fma,fma4") + [(set_attr "isa" "fma_or_avx512vl,fma_or_avx512vl,fma4") (set_attr "type" "ssemuladd") (set_attr "mode" "V4SF")]) diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-pr95046.c b/gcc/testsuite/gcc.target/i386/avx512vl-pr95046.c new file mode 100644 index 00000000000..02204d0e3c2 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512vl-pr95046.c @@ -0,0 +1,10 @@ +/* PR target/95046 */ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O3 -mavx512vl" } */ + +#include "pr95046-3.c" + +/* { dg-final { scan-assembler "\tvfmadd\[123\]+ps" } } */ +/* { dg-final { scan-assembler "\tvfmsub\[123\]+ps" } } */ +/* { dg-final { scan-assembler "\tvfnmadd\[123\]+ps" } } */ +/* { dg-final { scan-assembler "\tvfnmsub\[123\]+ps" } } */