@@ -9031,7 +9031,8 @@ (define_mode_attr extract_type
[(V16SF "avx512f") (V16SI "avx512f") (V8DF "avx512dq") (V8DI "avx512dq")])
(define_mode_attr extract_suf
- [(V16SF "32x4") (V16SI "32x4") (V8DF "64x2") (V8DI "64x2")])
+ [(V16SF "32x4") (V16SI "32x4") (V8DF "64x2") (V8DI "64x2")
+ (V8SF "32x4") (V8SI "32x4") (V4DF "64x2") (V4DI "64x2")])
(define_mode_iterator AVX512_VEC
[(V8DF "TARGET_AVX512DQ") (V8DI "TARGET_AVX512DQ") V16SF V16SI])
@@ -10603,9 +10604,21 @@ (define_insn "*vec_extract<mode><ssescalarmodelower>_valign"
(match_operand:V48_256_512_AVX512VL 1 "register_operand" "v")
(parallel [(match_operand 2 "<vec_extract_imm_predicate>")])))]
"TARGET_AVX512F
- && INTVAL(operands[2]) >= 16 / GET_MODE_SIZE (<ssescalarmode>mode)"
- "valign<ternlogsuffix>\t{%2, %1, %1, %<xtg_mode>0|%<xtg_mode>0, %1, %1, %2}";
- [(set_attr "prefix" "evex")
+ && INTVAL(operands[2]) * GET_MODE_SIZE (<ssescalarmode>mode) >= 16"
+{
+ int byte_offset = INTVAL (operands[2]) * GET_MODE_SIZE (<ssescalarmode>mode);
+ if (byte_offset % 16 == 0)
+ {
+ operands[2] = GEN_INT (byte_offset / 16);
+ if (byte_offset / 16 == 1)
+ return "vextract<shuffletype><extract_suf>\t{%2, %t1, %x0|%x0, %t1, %2}";
+ else
+ return "vextract<shuffletype><extract_suf>\t{%2, %1, %x0|%x0, %1, %2}";
+ }
+ else
+ return "valign<ternlogsuffix>\t{%2, %1, %1, %<xtg_mode>0|%<xtg_mode>0, %1, %1, %2}";
+}
+ [(set_attr "prefix" "maybe_evex")
(set_attr "mode" "<sseintvecinsnmode>")])
(define_expand "avx512f_shufps512_mask"
@@ -1,6 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-mavx512vl -O2" } */
-/* { dg-final { scan-assembler-times "valign\[dq\]" 16 } } */
+/* { dg-final { scan-assembler-times "valign\[dq\]" 8 } } */
+/* { dg-final { scan-assembler-times "vextract" 12 } } */
typedef float v8sf __attribute__((vector_size(32)));
typedef float v16sf __attribute__((vector_size(64)));
@@ -23,9 +24,13 @@ EXTRACT (v8sf, float, 4);
EXTRACT (v8sf, float, 7);
EXTRACT (v8si, int, 4);
EXTRACT (v8si, int, 7);
+EXTRACT (v16sf, float, 4);
EXTRACT (v16sf, float, 8);
+EXTRACT (v16sf, float, 12);
EXTRACT (v16sf, float, 15);
+EXTRACT (v16si, int, 4);
EXTRACT (v16si, int, 8);
+EXTRACT (v16si, int, 12);
EXTRACT (v16si, int, 15);
EXTRACT (v4df, double, 2);
EXTRACT (v4df, double, 3);
@@ -61,9 +61,13 @@ RUNCHECK (f2, v8sf, float, 4);
RUNCHECK (f2, v8sf, float, 7);
RUNCHECK (di2, v8si, int, 4);
RUNCHECK (di2, v8si, int, 7);
+RUNCHECK (f1, v16sf, float, 4);
RUNCHECK (f1, v16sf, float, 8);
+RUNCHECK (f1, v16sf, float, 12);
RUNCHECK (f1, v16sf, float, 15);
+RUNCHECK (di1, v16si, int, 4);
RUNCHECK (di1, v16si, int, 8);
+RUNCHECK (di1, v16si, int, 12);
RUNCHECK (di1, v16si, int, 15);
RUNCHECK (d2, v4df, double, 2);
RUNCHECK (d2, v4df, double, 3);