| Message ID | 20210907092101.1034733-1-christophe.lyon@foss.st.com |
|---|---|
| State | New |
| Headers | show |
| Series | ARM/MVE use vectors of boolean for predicates | expand |
Christophe Lyon via Gcc-patches <gcc-patches@gcc.gnu.org> writes: > This is mostly a mechanical change, only tested by the intrinsics > expansion tests. > > 2021-09-02 Christophe Lyon <christophe.lyon@foss.st.com> > > gcc/ > PR target/100757 > PR target/101325 > * config/arm/arm-builtins.c (BINOP_UNONE_NONE_NONE_QUALIFIERS): > Delete. > (TERNOP_UNONE_NONE_NONE_UNONE_QUALIFIERS): Change to ... > (TERNOP_PRED_NONE_NONE_PRED_QUALIFIERS): ... this. > (TERNOP_PRED_UNONE_UNONE_PRED_QUALIFIERS): New. > * config/arm/arm_mve_builtins.def (vcmp*q_n_, vcmp*q_m_f): Use new > predicated qualifiers. > * config/arm/mve.md (mve_vcmp<mve_cmp_op>q_n_<mode>) > (mve_vcmp*q_m_f<mode>): Use MVE_VPRED instead of HI. OK, thanks. Richard > > diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c > index 6e3638869f1..b3455d87d4f 100644 > --- a/gcc/config/arm/arm-builtins.c > +++ b/gcc/config/arm/arm-builtins.c > @@ -487,12 +487,6 @@ arm_binop_none_none_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] > #define BINOP_NONE_NONE_UNONE_QUALIFIERS \ > (arm_binop_none_none_unone_qualifiers) > > -static enum arm_type_qualifiers > -arm_binop_unone_none_none_qualifiers[SIMD_MAX_BUILTIN_ARGS] > - = { qualifier_unsigned, qualifier_none, qualifier_none }; > -#define BINOP_UNONE_NONE_NONE_QUALIFIERS \ > - (arm_binop_unone_none_none_qualifiers) > - > static enum arm_type_qualifiers > arm_binop_pred_none_none_qualifiers[SIMD_MAX_BUILTIN_ARGS] > = { qualifier_predicate, qualifier_none, qualifier_none }; > @@ -553,10 +547,10 @@ arm_ternop_unone_unone_imm_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] > (arm_ternop_unone_unone_imm_unone_qualifiers) > > static enum arm_type_qualifiers > -arm_ternop_unone_none_none_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] > - = { qualifier_unsigned, qualifier_none, qualifier_none, qualifier_unsigned }; > -#define TERNOP_UNONE_NONE_NONE_UNONE_QUALIFIERS \ > - (arm_ternop_unone_none_none_unone_qualifiers) > +arm_ternop_pred_none_none_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] > + = { qualifier_predicate, qualifier_none, qualifier_none, qualifier_predicate }; > +#define TERNOP_PRED_NONE_NONE_PRED_QUALIFIERS \ > + (arm_ternop_pred_none_none_pred_qualifiers) > > static enum arm_type_qualifiers > arm_ternop_none_none_none_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS] > @@ -602,6 +596,13 @@ arm_ternop_unone_unone_unone_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] > #define TERNOP_UNONE_UNONE_UNONE_PRED_QUALIFIERS \ > (arm_ternop_unone_unone_unone_pred_qualifiers) > > +static enum arm_type_qualifiers > +arm_ternop_pred_unone_unone_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] > + = { qualifier_predicate, qualifier_unsigned, qualifier_unsigned, > + qualifier_predicate }; > +#define TERNOP_PRED_UNONE_UNONE_PRED_QUALIFIERS \ > + (arm_ternop_pred_unone_unone_pred_qualifiers) > + > static enum arm_type_qualifiers > arm_ternop_none_none_none_none_qualifiers[SIMD_MAX_BUILTIN_ARGS] > = { qualifier_none, qualifier_none, qualifier_none, qualifier_none }; > diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def > index 58a05e61bd9..91ed2073918 100644 > --- a/gcc/config/arm/arm_mve_builtins.def > +++ b/gcc/config/arm/arm_mve_builtins.def > @@ -118,9 +118,9 @@ VAR3 (BINOP_UNONE_UNONE_UNONE, vhaddq_u, v16qi, v8hi, v4si) > VAR3 (BINOP_UNONE_UNONE_UNONE, vhaddq_n_u, v16qi, v8hi, v4si) > VAR3 (BINOP_UNONE_UNONE_UNONE, veorq_u, v16qi, v8hi, v4si) > VAR3 (BINOP_PRED_UNONE_UNONE, vcmphiq_, v16qi, v8hi, v4si) > -VAR3 (BINOP_UNONE_UNONE_UNONE, vcmphiq_n_, v16qi, v8hi, v4si) > +VAR3 (BINOP_PRED_UNONE_UNONE, vcmphiq_n_, v16qi, v8hi, v4si) > VAR3 (BINOP_PRED_UNONE_UNONE, vcmpcsq_, v16qi, v8hi, v4si) > -VAR3 (BINOP_UNONE_UNONE_UNONE, vcmpcsq_n_, v16qi, v8hi, v4si) > +VAR3 (BINOP_PRED_UNONE_UNONE, vcmpcsq_n_, v16qi, v8hi, v4si) > VAR3 (BINOP_UNONE_UNONE_UNONE, vbicq_u, v16qi, v8hi, v4si) > VAR3 (BINOP_UNONE_UNONE_UNONE, vandq_u, v16qi, v8hi, v4si) > VAR3 (BINOP_UNONE_UNONE_UNONE, vaddvq_p_u, v16qi, v8hi, v4si) > @@ -142,17 +142,17 @@ VAR3 (BINOP_UNONE_UNONE_NONE, vbrsrq_n_u, v16qi, v8hi, v4si) > VAR3 (BINOP_UNONE_UNONE_IMM, vshlq_n_u, v16qi, v8hi, v4si) > VAR3 (BINOP_UNONE_UNONE_IMM, vrshrq_n_u, v16qi, v8hi, v4si) > VAR3 (BINOP_UNONE_UNONE_IMM, vqshlq_n_u, v16qi, v8hi, v4si) > -VAR3 (BINOP_UNONE_NONE_NONE, vcmpneq_n_, v16qi, v8hi, v4si) > +VAR3 (BINOP_PRED_NONE_NONE, vcmpneq_n_, v16qi, v8hi, v4si) > VAR3 (BINOP_PRED_NONE_NONE, vcmpltq_, v16qi, v8hi, v4si) > -VAR3 (BINOP_UNONE_NONE_NONE, vcmpltq_n_, v16qi, v8hi, v4si) > +VAR3 (BINOP_PRED_NONE_NONE, vcmpltq_n_, v16qi, v8hi, v4si) > VAR3 (BINOP_PRED_NONE_NONE, vcmpleq_, v16qi, v8hi, v4si) > -VAR3 (BINOP_UNONE_NONE_NONE, vcmpleq_n_, v16qi, v8hi, v4si) > +VAR3 (BINOP_PRED_NONE_NONE, vcmpleq_n_, v16qi, v8hi, v4si) > VAR3 (BINOP_PRED_NONE_NONE, vcmpgtq_, v16qi, v8hi, v4si) > -VAR3 (BINOP_UNONE_NONE_NONE, vcmpgtq_n_, v16qi, v8hi, v4si) > +VAR3 (BINOP_PRED_NONE_NONE, vcmpgtq_n_, v16qi, v8hi, v4si) > VAR3 (BINOP_PRED_NONE_NONE, vcmpgeq_, v16qi, v8hi, v4si) > -VAR3 (BINOP_UNONE_NONE_NONE, vcmpgeq_n_, v16qi, v8hi, v4si) > +VAR3 (BINOP_PRED_NONE_NONE, vcmpgeq_n_, v16qi, v8hi, v4si) > VAR3 (BINOP_PRED_NONE_NONE, vcmpeqq_, v16qi, v8hi, v4si) > -VAR3 (BINOP_UNONE_NONE_NONE, vcmpeqq_n_, v16qi, v8hi, v4si) > +VAR3 (BINOP_PRED_NONE_NONE, vcmpeqq_n_, v16qi, v8hi, v4si) > VAR3 (BINOP_UNONE_NONE_IMM, vqshluq_n_s, v16qi, v8hi, v4si) > VAR3 (BINOP_NONE_NONE_UNONE, vaddvq_p_s, v16qi, v8hi, v4si) > VAR3 (BINOP_NONE_NONE_NONE, vsubq_s, v16qi, v8hi, v4si) > @@ -218,17 +218,17 @@ VAR2 (BINOP_UNONE_UNONE_IMM, vshlltq_n_u, v16qi, v8hi) > VAR2 (BINOP_UNONE_UNONE_IMM, vshllbq_n_u, v16qi, v8hi) > VAR2 (BINOP_UNONE_UNONE_IMM, vorrq_n_u, v8hi, v4si) > VAR2 (BINOP_UNONE_UNONE_IMM, vbicq_n_u, v8hi, v4si) > -VAR2 (BINOP_UNONE_NONE_NONE, vcmpneq_n_f, v8hf, v4sf) > +VAR2 (BINOP_PRED_NONE_NONE, vcmpneq_n_f, v8hf, v4sf) > VAR2 (BINOP_PRED_NONE_NONE, vcmpneq_f, v8hf, v4sf) > -VAR2 (BINOP_UNONE_NONE_NONE, vcmpltq_n_f, v8hf, v4sf) > +VAR2 (BINOP_PRED_NONE_NONE, vcmpltq_n_f, v8hf, v4sf) > VAR2 (BINOP_PRED_NONE_NONE, vcmpltq_f, v8hf, v4sf) > -VAR2 (BINOP_UNONE_NONE_NONE, vcmpleq_n_f, v8hf, v4sf) > +VAR2 (BINOP_PRED_NONE_NONE, vcmpleq_n_f, v8hf, v4sf) > VAR2 (BINOP_PRED_NONE_NONE, vcmpleq_f, v8hf, v4sf) > -VAR2 (BINOP_UNONE_NONE_NONE, vcmpgtq_n_f, v8hf, v4sf) > +VAR2 (BINOP_PRED_NONE_NONE, vcmpgtq_n_f, v8hf, v4sf) > VAR2 (BINOP_PRED_NONE_NONE, vcmpgtq_f, v8hf, v4sf) > -VAR2 (BINOP_UNONE_NONE_NONE, vcmpgeq_n_f, v8hf, v4sf) > +VAR2 (BINOP_PRED_NONE_NONE, vcmpgeq_n_f, v8hf, v4sf) > VAR2 (BINOP_PRED_NONE_NONE, vcmpgeq_f, v8hf, v4sf) > -VAR2 (BINOP_UNONE_NONE_NONE, vcmpeqq_n_f, v8hf, v4sf) > +VAR2 (BINOP_PRED_NONE_NONE, vcmpeqq_n_f, v8hf, v4sf) > VAR2 (BINOP_PRED_NONE_NONE, vcmpeqq_f, v8hf, v4sf) > VAR2 (BINOP_NONE_NONE_NONE, vsubq_f, v8hf, v4sf) > VAR2 (BINOP_NONE_NONE_NONE, vqmovntq_s, v8hi, v4si) > @@ -285,7 +285,7 @@ VAR1 (TERNOP_NONE_NONE_NONE_NONE, vrmlaldavhaq_s, v4si) > VAR1 (TERNOP_UNONE_UNONE_UNONE_UNONE, vrmlaldavhaq_u, v4si) > VAR2 (TERNOP_NONE_NONE_UNONE_UNONE, vcvtq_m_to_f_u, v8hf, v4sf) > VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vcvtq_m_to_f_s, v8hf, v4sf) > -VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpeqq_m_f, v8hf, v4sf) > +VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpeqq_m_f, v8hf, v4sf) > VAR3 (TERNOP_UNONE_NONE_UNONE_IMM, vshlcq_carry_s, v16qi, v8hi, v4si) > VAR3 (TERNOP_UNONE_UNONE_UNONE_IMM, vshlcq_carry_u, v16qi, v8hi, v4si) > VAR2 (TERNOP_UNONE_UNONE_NONE_IMM, vqrshrunbq_n_s, v8hi, v4si) > @@ -306,14 +306,14 @@ VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vmladavaq_u, v16qi, v8hi, v4si) > VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vminvq_p_u, v16qi, v8hi, v4si) > VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vmaxvq_p_u, v16qi, v8hi, v4si) > VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vdupq_m_n_u, v16qi, v8hi, v4si) > -VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vcmpneq_m_u, v16qi, v8hi, v4si) > -VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vcmpneq_m_n_u, v16qi, v8hi, v4si) > -VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vcmphiq_m_u, v16qi, v8hi, v4si) > -VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vcmphiq_m_n_u, v16qi, v8hi, v4si) > -VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vcmpeqq_m_u, v16qi, v8hi, v4si) > -VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vcmpeqq_m_n_u, v16qi, v8hi, v4si) > -VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vcmpcsq_m_u, v16qi, v8hi, v4si) > -VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vcmpcsq_m_n_u, v16qi, v8hi, v4si) > +VAR3 (TERNOP_PRED_UNONE_UNONE_PRED, vcmpneq_m_u, v16qi, v8hi, v4si) > +VAR3 (TERNOP_PRED_UNONE_UNONE_PRED, vcmpneq_m_n_u, v16qi, v8hi, v4si) > +VAR3 (TERNOP_PRED_UNONE_UNONE_PRED, vcmphiq_m_u, v16qi, v8hi, v4si) > +VAR3 (TERNOP_PRED_UNONE_UNONE_PRED, vcmphiq_m_n_u, v16qi, v8hi, v4si) > +VAR3 (TERNOP_PRED_UNONE_UNONE_PRED, vcmpeqq_m_u, v16qi, v8hi, v4si) > +VAR3 (TERNOP_PRED_UNONE_UNONE_PRED, vcmpeqq_m_n_u, v16qi, v8hi, v4si) > +VAR3 (TERNOP_PRED_UNONE_UNONE_PRED, vcmpcsq_m_u, v16qi, v8hi, v4si) > +VAR3 (TERNOP_PRED_UNONE_UNONE_PRED, vcmpcsq_m_n_u, v16qi, v8hi, v4si) > VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vclzq_m_u, v16qi, v8hi, v4si) > VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vaddvaq_p_u, v16qi, v8hi, v4si) > VAR3 (TERNOP_UNONE_UNONE_UNONE_IMM, vsriq_n_u, v16qi, v8hi, v4si) > @@ -326,18 +326,18 @@ VAR3 (TERNOP_UNONE_UNONE_NONE_UNONE, vminavq_p_s, v16qi, v8hi, v4si) > VAR3 (TERNOP_UNONE_UNONE_NONE_UNONE, vminaq_m_s, v16qi, v8hi, v4si) > VAR3 (TERNOP_UNONE_UNONE_NONE_UNONE, vmaxavq_p_s, v16qi, v8hi, v4si) > VAR3 (TERNOP_UNONE_UNONE_NONE_UNONE, vmaxaq_m_s, v16qi, v8hi, v4si) > -VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpneq_m_s, v16qi, v8hi, v4si) > -VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpneq_m_n_s, v16qi, v8hi, v4si) > -VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpltq_m_s, v16qi, v8hi, v4si) > -VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpltq_m_n_s, v16qi, v8hi, v4si) > -VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpleq_m_s, v16qi, v8hi, v4si) > -VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpleq_m_n_s, v16qi, v8hi, v4si) > -VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpgtq_m_s, v16qi, v8hi, v4si) > -VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpgtq_m_n_s, v16qi, v8hi, v4si) > -VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpgeq_m_s, v16qi, v8hi, v4si) > -VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpgeq_m_n_s, v16qi, v8hi, v4si) > -VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpeqq_m_s, v16qi, v8hi, v4si) > -VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpeqq_m_n_s, v16qi, v8hi, v4si) > +VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpneq_m_s, v16qi, v8hi, v4si) > +VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpneq_m_n_s, v16qi, v8hi, v4si) > +VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpltq_m_s, v16qi, v8hi, v4si) > +VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpltq_m_n_s, v16qi, v8hi, v4si) > +VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpleq_m_s, v16qi, v8hi, v4si) > +VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpleq_m_n_s, v16qi, v8hi, v4si) > +VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpgtq_m_s, v16qi, v8hi, v4si) > +VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpgtq_m_n_s, v16qi, v8hi, v4si) > +VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpgeq_m_s, v16qi, v8hi, v4si) > +VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpgeq_m_n_s, v16qi, v8hi, v4si) > +VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpeqq_m_s, v16qi, v8hi, v4si) > +VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpeqq_m_n_s, v16qi, v8hi, v4si) > VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vshlq_m_r_s, v16qi, v8hi, v4si) > VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vrshlq_m_n_s, v16qi, v8hi, v4si) > VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vrev64q_m_s, v16qi, v8hi, v4si) > @@ -405,17 +405,17 @@ VAR2 (TERNOP_UNONE_UNONE_NONE_IMM, vqshrunbq_n_s, v8hi, v4si) > VAR2 (TERNOP_UNONE_UNONE_NONE_IMM, vqrshruntq_n_s, v8hi, v4si) > VAR2 (TERNOP_UNONE_UNONE_IMM_UNONE, vorrq_m_n_u, v8hi, v4si) > VAR2 (TERNOP_UNONE_UNONE_IMM_UNONE, vmvnq_m_n_u, v8hi, v4si) > -VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpneq_m_n_f, v8hf, v4sf) > -VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpneq_m_f, v8hf, v4sf) > -VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpltq_m_n_f, v8hf, v4sf) > -VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpltq_m_f, v8hf, v4sf) > -VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpleq_m_n_f, v8hf, v4sf) > -VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpleq_m_f, v8hf, v4sf) > -VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpgtq_m_n_f, v8hf, v4sf) > -VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpgtq_m_f, v8hf, v4sf) > -VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpgeq_m_n_f, v8hf, v4sf) > -VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpgeq_m_f, v8hf, v4sf) > -VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpeqq_m_n_f, v8hf, v4sf) > +VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpneq_m_n_f, v8hf, v4sf) > +VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpneq_m_f, v8hf, v4sf) > +VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpltq_m_n_f, v8hf, v4sf) > +VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpltq_m_f, v8hf, v4sf) > +VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpleq_m_n_f, v8hf, v4sf) > +VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpleq_m_f, v8hf, v4sf) > +VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpgtq_m_n_f, v8hf, v4sf) > +VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpgtq_m_f, v8hf, v4sf) > +VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpgeq_m_n_f, v8hf, v4sf) > +VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpgeq_m_f, v8hf, v4sf) > +VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpeqq_m_n_f, v8hf, v4sf) > VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vrndxq_m_f, v8hf, v4sf) > VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vrndq_m_f, v8hf, v4sf) > VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vrndpq_m_f, v8hf, v4sf) > diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md > index d663c698cfb..4867aa79687 100644 > --- a/gcc/config/arm/mve.md > +++ b/gcc/config/arm/mve.md > @@ -853,8 +853,8 @@ (define_insn "@mve_vcmp<mve_cmp_op>q_<mode>" > ;; > (define_insn "mve_vcmp<mve_cmp_op>q_n_<mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (MVE_COMPARISONS:HI (match_operand:MVE_2 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (MVE_COMPARISONS:<MVE_VPRED> (match_operand:MVE_2 1 "s_register_operand" "w") > (match_operand:<V_elem> 2 "s_register_operand" "r"))) > ] > "TARGET_HAVE_MVE" > @@ -1943,8 +1943,8 @@ (define_insn "@mve_vcmp<mve_cmp_op>q_f<mode>" > ;; > (define_insn "@mve_vcmp<mve_cmp_op>q_n_f<mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (MVE_FP_COMPARISONS:HI (match_operand:MVE_0 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (MVE_FP_COMPARISONS:<MVE_VPRED> (match_operand:MVE_0 1 "s_register_operand" "w") > (match_operand:<V_elem> 2 "s_register_operand" "r"))) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -2593,10 +2593,10 @@ (define_insn "mve_vbicq_m_n_<supf><mode>" > ;; > (define_insn "mve_vcmpeqq_m_f<mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") > (match_operand:MVE_0 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCMPEQQ_M_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -2809,10 +2809,10 @@ (define_insn "mve_vclzq_m_<supf><mode>" > ;; > (define_insn "mve_vcmpcsq_m_n_u<mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") > (match_operand:<V_elem> 2 "s_register_operand" "r") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCMPCSQ_M_N_U)) > ] > "TARGET_HAVE_MVE" > @@ -2825,10 +2825,10 @@ (define_insn "mve_vcmpcsq_m_n_u<mode>" > ;; > (define_insn "mve_vcmpcsq_m_u<mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") > (match_operand:MVE_2 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCMPCSQ_M_U)) > ] > "TARGET_HAVE_MVE" > @@ -2841,10 +2841,10 @@ (define_insn "mve_vcmpcsq_m_u<mode>" > ;; > (define_insn "mve_vcmpeqq_m_n_<supf><mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") > (match_operand:<V_elem> 2 "s_register_operand" "r") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCMPEQQ_M_N)) > ] > "TARGET_HAVE_MVE" > @@ -2857,10 +2857,10 @@ (define_insn "mve_vcmpeqq_m_n_<supf><mode>" > ;; > (define_insn "mve_vcmpeqq_m_<supf><mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") > (match_operand:MVE_2 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCMPEQQ_M)) > ] > "TARGET_HAVE_MVE" > @@ -2873,10 +2873,10 @@ (define_insn "mve_vcmpeqq_m_<supf><mode>" > ;; > (define_insn "mve_vcmpgeq_m_n_s<mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") > (match_operand:<V_elem> 2 "s_register_operand" "r") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCMPGEQ_M_N_S)) > ] > "TARGET_HAVE_MVE" > @@ -2889,10 +2889,10 @@ (define_insn "mve_vcmpgeq_m_n_s<mode>" > ;; > (define_insn "mve_vcmpgeq_m_s<mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") > (match_operand:MVE_2 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCMPGEQ_M_S)) > ] > "TARGET_HAVE_MVE" > @@ -2905,10 +2905,10 @@ (define_insn "mve_vcmpgeq_m_s<mode>" > ;; > (define_insn "mve_vcmpgtq_m_n_s<mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") > (match_operand:<V_elem> 2 "s_register_operand" "r") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCMPGTQ_M_N_S)) > ] > "TARGET_HAVE_MVE" > @@ -2921,10 +2921,10 @@ (define_insn "mve_vcmpgtq_m_n_s<mode>" > ;; > (define_insn "mve_vcmpgtq_m_s<mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") > (match_operand:MVE_2 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCMPGTQ_M_S)) > ] > "TARGET_HAVE_MVE" > @@ -2937,10 +2937,10 @@ (define_insn "mve_vcmpgtq_m_s<mode>" > ;; > (define_insn "mve_vcmphiq_m_n_u<mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") > (match_operand:<V_elem> 2 "s_register_operand" "r") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCMPHIQ_M_N_U)) > ] > "TARGET_HAVE_MVE" > @@ -2953,10 +2953,10 @@ (define_insn "mve_vcmphiq_m_n_u<mode>" > ;; > (define_insn "mve_vcmphiq_m_u<mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") > (match_operand:MVE_2 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCMPHIQ_M_U)) > ] > "TARGET_HAVE_MVE" > @@ -2969,10 +2969,10 @@ (define_insn "mve_vcmphiq_m_u<mode>" > ;; > (define_insn "mve_vcmpleq_m_n_s<mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") > (match_operand:<V_elem> 2 "s_register_operand" "r") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCMPLEQ_M_N_S)) > ] > "TARGET_HAVE_MVE" > @@ -2985,10 +2985,10 @@ (define_insn "mve_vcmpleq_m_n_s<mode>" > ;; > (define_insn "mve_vcmpleq_m_s<mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") > (match_operand:MVE_2 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCMPLEQ_M_S)) > ] > "TARGET_HAVE_MVE" > @@ -3001,10 +3001,10 @@ (define_insn "mve_vcmpleq_m_s<mode>" > ;; > (define_insn "mve_vcmpltq_m_n_s<mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") > (match_operand:<V_elem> 2 "s_register_operand" "r") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCMPLTQ_M_N_S)) > ] > "TARGET_HAVE_MVE" > @@ -3017,10 +3017,10 @@ (define_insn "mve_vcmpltq_m_n_s<mode>" > ;; > (define_insn "mve_vcmpltq_m_s<mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") > (match_operand:MVE_2 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCMPLTQ_M_S)) > ] > "TARGET_HAVE_MVE" > @@ -3033,10 +3033,10 @@ (define_insn "mve_vcmpltq_m_s<mode>" > ;; > (define_insn "mve_vcmpneq_m_n_<supf><mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") > (match_operand:<V_elem> 2 "s_register_operand" "r") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCMPNEQ_M_N)) > ] > "TARGET_HAVE_MVE" > @@ -3049,10 +3049,10 @@ (define_insn "mve_vcmpneq_m_n_<supf><mode>" > ;; > (define_insn "mve_vcmpneq_m_<supf><mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") > (match_operand:MVE_2 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCMPNEQ_M)) > ] > "TARGET_HAVE_MVE" > @@ -3782,10 +3782,10 @@ (define_insn "mve_vcmlaq<mve_rot><mode>" > ;; > (define_insn "mve_vcmpeqq_m_n_f<mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") > (match_operand:<V_elem> 2 "s_register_operand" "r") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCMPEQQ_M_N_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -3798,10 +3798,10 @@ (define_insn "mve_vcmpeqq_m_n_f<mode>" > ;; > (define_insn "mve_vcmpgeq_m_f<mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") > (match_operand:MVE_0 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCMPGEQ_M_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -3814,10 +3814,10 @@ (define_insn "mve_vcmpgeq_m_f<mode>" > ;; > (define_insn "mve_vcmpgeq_m_n_f<mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") > (match_operand:<V_elem> 2 "s_register_operand" "r") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCMPGEQ_M_N_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -3830,10 +3830,10 @@ (define_insn "mve_vcmpgeq_m_n_f<mode>" > ;; > (define_insn "mve_vcmpgtq_m_f<mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") > (match_operand:MVE_0 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCMPGTQ_M_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -3846,10 +3846,10 @@ (define_insn "mve_vcmpgtq_m_f<mode>" > ;; > (define_insn "mve_vcmpgtq_m_n_f<mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") > (match_operand:<V_elem> 2 "s_register_operand" "r") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCMPGTQ_M_N_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -3862,10 +3862,10 @@ (define_insn "mve_vcmpgtq_m_n_f<mode>" > ;; > (define_insn "mve_vcmpleq_m_f<mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") > (match_operand:MVE_0 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCMPLEQ_M_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -3878,10 +3878,10 @@ (define_insn "mve_vcmpleq_m_f<mode>" > ;; > (define_insn "mve_vcmpleq_m_n_f<mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") > (match_operand:<V_elem> 2 "s_register_operand" "r") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCMPLEQ_M_N_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -3894,10 +3894,10 @@ (define_insn "mve_vcmpleq_m_n_f<mode>" > ;; > (define_insn "mve_vcmpltq_m_f<mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") > (match_operand:MVE_0 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCMPLTQ_M_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -3910,10 +3910,10 @@ (define_insn "mve_vcmpltq_m_f<mode>" > ;; > (define_insn "mve_vcmpltq_m_n_f<mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") > (match_operand:<V_elem> 2 "s_register_operand" "r") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCMPLTQ_M_N_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -3926,10 +3926,10 @@ (define_insn "mve_vcmpltq_m_n_f<mode>" > ;; > (define_insn "mve_vcmpneq_m_f<mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") > (match_operand:MVE_0 2 "s_register_operand" "w") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCMPNEQ_M_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > @@ -3942,10 +3942,10 @@ (define_insn "mve_vcmpneq_m_f<mode>" > ;; > (define_insn "mve_vcmpneq_m_n_f<mode>" > [ > - (set (match_operand:HI 0 "vpr_register_operand" "=Up") > - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") > + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") > + (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") > (match_operand:<V_elem> 2 "s_register_operand" "r") > - (match_operand:HI 3 "vpr_register_operand" "Up")] > + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] > VCMPNEQ_M_N_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c index 6e3638869f1..b3455d87d4f 100644 --- a/gcc/config/arm/arm-builtins.c +++ b/gcc/config/arm/arm-builtins.c @@ -487,12 +487,6 @@ arm_binop_none_none_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] #define BINOP_NONE_NONE_UNONE_QUALIFIERS \ (arm_binop_none_none_unone_qualifiers) -static enum arm_type_qualifiers -arm_binop_unone_none_none_qualifiers[SIMD_MAX_BUILTIN_ARGS] - = { qualifier_unsigned, qualifier_none, qualifier_none }; -#define BINOP_UNONE_NONE_NONE_QUALIFIERS \ - (arm_binop_unone_none_none_qualifiers) - static enum arm_type_qualifiers arm_binop_pred_none_none_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_predicate, qualifier_none, qualifier_none }; @@ -553,10 +547,10 @@ arm_ternop_unone_unone_imm_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] (arm_ternop_unone_unone_imm_unone_qualifiers) static enum arm_type_qualifiers -arm_ternop_unone_none_none_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] - = { qualifier_unsigned, qualifier_none, qualifier_none, qualifier_unsigned }; -#define TERNOP_UNONE_NONE_NONE_UNONE_QUALIFIERS \ - (arm_ternop_unone_none_none_unone_qualifiers) +arm_ternop_pred_none_none_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_predicate, qualifier_none, qualifier_none, qualifier_predicate }; +#define TERNOP_PRED_NONE_NONE_PRED_QUALIFIERS \ + (arm_ternop_pred_none_none_pred_qualifiers) static enum arm_type_qualifiers arm_ternop_none_none_none_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS] @@ -602,6 +596,13 @@ arm_ternop_unone_unone_unone_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] #define TERNOP_UNONE_UNONE_UNONE_PRED_QUALIFIERS \ (arm_ternop_unone_unone_unone_pred_qualifiers) +static enum arm_type_qualifiers +arm_ternop_pred_unone_unone_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_predicate, qualifier_unsigned, qualifier_unsigned, + qualifier_predicate }; +#define TERNOP_PRED_UNONE_UNONE_PRED_QUALIFIERS \ + (arm_ternop_pred_unone_unone_pred_qualifiers) + static enum arm_type_qualifiers arm_ternop_none_none_none_none_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_none, qualifier_none, qualifier_none, qualifier_none }; diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def index 58a05e61bd9..91ed2073918 100644 --- a/gcc/config/arm/arm_mve_builtins.def +++ b/gcc/config/arm/arm_mve_builtins.def @@ -118,9 +118,9 @@ VAR3 (BINOP_UNONE_UNONE_UNONE, vhaddq_u, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_UNONE_UNONE, vhaddq_n_u, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_UNONE_UNONE, veorq_u, v16qi, v8hi, v4si) VAR3 (BINOP_PRED_UNONE_UNONE, vcmphiq_, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_UNONE, vcmphiq_n_, v16qi, v8hi, v4si) +VAR3 (BINOP_PRED_UNONE_UNONE, vcmphiq_n_, v16qi, v8hi, v4si) VAR3 (BINOP_PRED_UNONE_UNONE, vcmpcsq_, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_UNONE, vcmpcsq_n_, v16qi, v8hi, v4si) +VAR3 (BINOP_PRED_UNONE_UNONE, vcmpcsq_n_, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_UNONE_UNONE, vbicq_u, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_UNONE_UNONE, vandq_u, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_UNONE_UNONE, vaddvq_p_u, v16qi, v8hi, v4si) @@ -142,17 +142,17 @@ VAR3 (BINOP_UNONE_UNONE_NONE, vbrsrq_n_u, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_UNONE_IMM, vshlq_n_u, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_UNONE_IMM, vrshrq_n_u, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_UNONE_IMM, vqshlq_n_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_NONE_NONE, vcmpneq_n_, v16qi, v8hi, v4si) +VAR3 (BINOP_PRED_NONE_NONE, vcmpneq_n_, v16qi, v8hi, v4si) VAR3 (BINOP_PRED_NONE_NONE, vcmpltq_, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_NONE_NONE, vcmpltq_n_, v16qi, v8hi, v4si) +VAR3 (BINOP_PRED_NONE_NONE, vcmpltq_n_, v16qi, v8hi, v4si) VAR3 (BINOP_PRED_NONE_NONE, vcmpleq_, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_NONE_NONE, vcmpleq_n_, v16qi, v8hi, v4si) +VAR3 (BINOP_PRED_NONE_NONE, vcmpleq_n_, v16qi, v8hi, v4si) VAR3 (BINOP_PRED_NONE_NONE, vcmpgtq_, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_NONE_NONE, vcmpgtq_n_, v16qi, v8hi, v4si) +VAR3 (BINOP_PRED_NONE_NONE, vcmpgtq_n_, v16qi, v8hi, v4si) VAR3 (BINOP_PRED_NONE_NONE, vcmpgeq_, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_NONE_NONE, vcmpgeq_n_, v16qi, v8hi, v4si) +VAR3 (BINOP_PRED_NONE_NONE, vcmpgeq_n_, v16qi, v8hi, v4si) VAR3 (BINOP_PRED_NONE_NONE, vcmpeqq_, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_NONE_NONE, vcmpeqq_n_, v16qi, v8hi, v4si) +VAR3 (BINOP_PRED_NONE_NONE, vcmpeqq_n_, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_NONE_IMM, vqshluq_n_s, v16qi, v8hi, v4si) VAR3 (BINOP_NONE_NONE_UNONE, vaddvq_p_s, v16qi, v8hi, v4si) VAR3 (BINOP_NONE_NONE_NONE, vsubq_s, v16qi, v8hi, v4si) @@ -218,17 +218,17 @@ VAR2 (BINOP_UNONE_UNONE_IMM, vshlltq_n_u, v16qi, v8hi) VAR2 (BINOP_UNONE_UNONE_IMM, vshllbq_n_u, v16qi, v8hi) VAR2 (BINOP_UNONE_UNONE_IMM, vorrq_n_u, v8hi, v4si) VAR2 (BINOP_UNONE_UNONE_IMM, vbicq_n_u, v8hi, v4si) -VAR2 (BINOP_UNONE_NONE_NONE, vcmpneq_n_f, v8hf, v4sf) +VAR2 (BINOP_PRED_NONE_NONE, vcmpneq_n_f, v8hf, v4sf) VAR2 (BINOP_PRED_NONE_NONE, vcmpneq_f, v8hf, v4sf) -VAR2 (BINOP_UNONE_NONE_NONE, vcmpltq_n_f, v8hf, v4sf) +VAR2 (BINOP_PRED_NONE_NONE, vcmpltq_n_f, v8hf, v4sf) VAR2 (BINOP_PRED_NONE_NONE, vcmpltq_f, v8hf, v4sf) -VAR2 (BINOP_UNONE_NONE_NONE, vcmpleq_n_f, v8hf, v4sf) +VAR2 (BINOP_PRED_NONE_NONE, vcmpleq_n_f, v8hf, v4sf) VAR2 (BINOP_PRED_NONE_NONE, vcmpleq_f, v8hf, v4sf) -VAR2 (BINOP_UNONE_NONE_NONE, vcmpgtq_n_f, v8hf, v4sf) +VAR2 (BINOP_PRED_NONE_NONE, vcmpgtq_n_f, v8hf, v4sf) VAR2 (BINOP_PRED_NONE_NONE, vcmpgtq_f, v8hf, v4sf) -VAR2 (BINOP_UNONE_NONE_NONE, vcmpgeq_n_f, v8hf, v4sf) +VAR2 (BINOP_PRED_NONE_NONE, vcmpgeq_n_f, v8hf, v4sf) VAR2 (BINOP_PRED_NONE_NONE, vcmpgeq_f, v8hf, v4sf) -VAR2 (BINOP_UNONE_NONE_NONE, vcmpeqq_n_f, v8hf, v4sf) +VAR2 (BINOP_PRED_NONE_NONE, vcmpeqq_n_f, v8hf, v4sf) VAR2 (BINOP_PRED_NONE_NONE, vcmpeqq_f, v8hf, v4sf) VAR2 (BINOP_NONE_NONE_NONE, vsubq_f, v8hf, v4sf) VAR2 (BINOP_NONE_NONE_NONE, vqmovntq_s, v8hi, v4si) @@ -285,7 +285,7 @@ VAR1 (TERNOP_NONE_NONE_NONE_NONE, vrmlaldavhaq_s, v4si) VAR1 (TERNOP_UNONE_UNONE_UNONE_UNONE, vrmlaldavhaq_u, v4si) VAR2 (TERNOP_NONE_NONE_UNONE_UNONE, vcvtq_m_to_f_u, v8hf, v4sf) VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vcvtq_m_to_f_s, v8hf, v4sf) -VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpeqq_m_f, v8hf, v4sf) +VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpeqq_m_f, v8hf, v4sf) VAR3 (TERNOP_UNONE_NONE_UNONE_IMM, vshlcq_carry_s, v16qi, v8hi, v4si) VAR3 (TERNOP_UNONE_UNONE_UNONE_IMM, vshlcq_carry_u, v16qi, v8hi, v4si) VAR2 (TERNOP_UNONE_UNONE_NONE_IMM, vqrshrunbq_n_s, v8hi, v4si) @@ -306,14 +306,14 @@ VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vmladavaq_u, v16qi, v8hi, v4si) VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vminvq_p_u, v16qi, v8hi, v4si) VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vmaxvq_p_u, v16qi, v8hi, v4si) VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vdupq_m_n_u, v16qi, v8hi, v4si) -VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vcmpneq_m_u, v16qi, v8hi, v4si) -VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vcmpneq_m_n_u, v16qi, v8hi, v4si) -VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vcmphiq_m_u, v16qi, v8hi, v4si) -VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vcmphiq_m_n_u, v16qi, v8hi, v4si) -VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vcmpeqq_m_u, v16qi, v8hi, v4si) -VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vcmpeqq_m_n_u, v16qi, v8hi, v4si) -VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vcmpcsq_m_u, v16qi, v8hi, v4si) -VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vcmpcsq_m_n_u, v16qi, v8hi, v4si) +VAR3 (TERNOP_PRED_UNONE_UNONE_PRED, vcmpneq_m_u, v16qi, v8hi, v4si) +VAR3 (TERNOP_PRED_UNONE_UNONE_PRED, vcmpneq_m_n_u, v16qi, v8hi, v4si) +VAR3 (TERNOP_PRED_UNONE_UNONE_PRED, vcmphiq_m_u, v16qi, v8hi, v4si) +VAR3 (TERNOP_PRED_UNONE_UNONE_PRED, vcmphiq_m_n_u, v16qi, v8hi, v4si) +VAR3 (TERNOP_PRED_UNONE_UNONE_PRED, vcmpeqq_m_u, v16qi, v8hi, v4si) +VAR3 (TERNOP_PRED_UNONE_UNONE_PRED, vcmpeqq_m_n_u, v16qi, v8hi, v4si) +VAR3 (TERNOP_PRED_UNONE_UNONE_PRED, vcmpcsq_m_u, v16qi, v8hi, v4si) +VAR3 (TERNOP_PRED_UNONE_UNONE_PRED, vcmpcsq_m_n_u, v16qi, v8hi, v4si) VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vclzq_m_u, v16qi, v8hi, v4si) VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vaddvaq_p_u, v16qi, v8hi, v4si) VAR3 (TERNOP_UNONE_UNONE_UNONE_IMM, vsriq_n_u, v16qi, v8hi, v4si) @@ -326,18 +326,18 @@ VAR3 (TERNOP_UNONE_UNONE_NONE_UNONE, vminavq_p_s, v16qi, v8hi, v4si) VAR3 (TERNOP_UNONE_UNONE_NONE_UNONE, vminaq_m_s, v16qi, v8hi, v4si) VAR3 (TERNOP_UNONE_UNONE_NONE_UNONE, vmaxavq_p_s, v16qi, v8hi, v4si) VAR3 (TERNOP_UNONE_UNONE_NONE_UNONE, vmaxaq_m_s, v16qi, v8hi, v4si) -VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpneq_m_s, v16qi, v8hi, v4si) -VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpneq_m_n_s, v16qi, v8hi, v4si) -VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpltq_m_s, v16qi, v8hi, v4si) -VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpltq_m_n_s, v16qi, v8hi, v4si) -VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpleq_m_s, v16qi, v8hi, v4si) -VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpleq_m_n_s, v16qi, v8hi, v4si) -VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpgtq_m_s, v16qi, v8hi, v4si) -VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpgtq_m_n_s, v16qi, v8hi, v4si) -VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpgeq_m_s, v16qi, v8hi, v4si) -VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpgeq_m_n_s, v16qi, v8hi, v4si) -VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpeqq_m_s, v16qi, v8hi, v4si) -VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpeqq_m_n_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpneq_m_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpneq_m_n_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpltq_m_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpltq_m_n_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpleq_m_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpleq_m_n_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpgtq_m_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpgtq_m_n_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpgeq_m_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpgeq_m_n_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpeqq_m_s, v16qi, v8hi, v4si) +VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpeqq_m_n_s, v16qi, v8hi, v4si) VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vshlq_m_r_s, v16qi, v8hi, v4si) VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vrshlq_m_n_s, v16qi, v8hi, v4si) VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vrev64q_m_s, v16qi, v8hi, v4si) @@ -405,17 +405,17 @@ VAR2 (TERNOP_UNONE_UNONE_NONE_IMM, vqshrunbq_n_s, v8hi, v4si) VAR2 (TERNOP_UNONE_UNONE_NONE_IMM, vqrshruntq_n_s, v8hi, v4si) VAR2 (TERNOP_UNONE_UNONE_IMM_UNONE, vorrq_m_n_u, v8hi, v4si) VAR2 (TERNOP_UNONE_UNONE_IMM_UNONE, vmvnq_m_n_u, v8hi, v4si) -VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpneq_m_n_f, v8hf, v4sf) -VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpneq_m_f, v8hf, v4sf) -VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpltq_m_n_f, v8hf, v4sf) -VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpltq_m_f, v8hf, v4sf) -VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpleq_m_n_f, v8hf, v4sf) -VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpleq_m_f, v8hf, v4sf) -VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpgtq_m_n_f, v8hf, v4sf) -VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpgtq_m_f, v8hf, v4sf) -VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpgeq_m_n_f, v8hf, v4sf) -VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpgeq_m_f, v8hf, v4sf) -VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpeqq_m_n_f, v8hf, v4sf) +VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpneq_m_n_f, v8hf, v4sf) +VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpneq_m_f, v8hf, v4sf) +VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpltq_m_n_f, v8hf, v4sf) +VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpltq_m_f, v8hf, v4sf) +VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpleq_m_n_f, v8hf, v4sf) +VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpleq_m_f, v8hf, v4sf) +VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpgtq_m_n_f, v8hf, v4sf) +VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpgtq_m_f, v8hf, v4sf) +VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpgeq_m_n_f, v8hf, v4sf) +VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpgeq_m_f, v8hf, v4sf) +VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpeqq_m_n_f, v8hf, v4sf) VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vrndxq_m_f, v8hf, v4sf) VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vrndq_m_f, v8hf, v4sf) VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vrndpq_m_f, v8hf, v4sf) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index d663c698cfb..4867aa79687 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -853,8 +853,8 @@ (define_insn "@mve_vcmp<mve_cmp_op>q_<mode>" ;; (define_insn "mve_vcmp<mve_cmp_op>q_n_<mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (MVE_COMPARISONS:HI (match_operand:MVE_2 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (MVE_COMPARISONS:<MVE_VPRED> (match_operand:MVE_2 1 "s_register_operand" "w") (match_operand:<V_elem> 2 "s_register_operand" "r"))) ] "TARGET_HAVE_MVE" @@ -1943,8 +1943,8 @@ (define_insn "@mve_vcmp<mve_cmp_op>q_f<mode>" ;; (define_insn "@mve_vcmp<mve_cmp_op>q_n_f<mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (MVE_FP_COMPARISONS:HI (match_operand:MVE_0 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (MVE_FP_COMPARISONS:<MVE_VPRED> (match_operand:MVE_0 1 "s_register_operand" "w") (match_operand:<V_elem> 2 "s_register_operand" "r"))) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -2593,10 +2593,10 @@ (define_insn "mve_vbicq_m_n_<supf><mode>" ;; (define_insn "mve_vcmpeqq_m_f<mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") (match_operand:MVE_0 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCMPEQQ_M_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -2809,10 +2809,10 @@ (define_insn "mve_vclzq_m_<supf><mode>" ;; (define_insn "mve_vcmpcsq_m_n_u<mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") (match_operand:<V_elem> 2 "s_register_operand" "r") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCMPCSQ_M_N_U)) ] "TARGET_HAVE_MVE" @@ -2825,10 +2825,10 @@ (define_insn "mve_vcmpcsq_m_n_u<mode>" ;; (define_insn "mve_vcmpcsq_m_u<mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCMPCSQ_M_U)) ] "TARGET_HAVE_MVE" @@ -2841,10 +2841,10 @@ (define_insn "mve_vcmpcsq_m_u<mode>" ;; (define_insn "mve_vcmpeqq_m_n_<supf><mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") (match_operand:<V_elem> 2 "s_register_operand" "r") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCMPEQQ_M_N)) ] "TARGET_HAVE_MVE" @@ -2857,10 +2857,10 @@ (define_insn "mve_vcmpeqq_m_n_<supf><mode>" ;; (define_insn "mve_vcmpeqq_m_<supf><mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCMPEQQ_M)) ] "TARGET_HAVE_MVE" @@ -2873,10 +2873,10 @@ (define_insn "mve_vcmpeqq_m_<supf><mode>" ;; (define_insn "mve_vcmpgeq_m_n_s<mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") (match_operand:<V_elem> 2 "s_register_operand" "r") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCMPGEQ_M_N_S)) ] "TARGET_HAVE_MVE" @@ -2889,10 +2889,10 @@ (define_insn "mve_vcmpgeq_m_n_s<mode>" ;; (define_insn "mve_vcmpgeq_m_s<mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCMPGEQ_M_S)) ] "TARGET_HAVE_MVE" @@ -2905,10 +2905,10 @@ (define_insn "mve_vcmpgeq_m_s<mode>" ;; (define_insn "mve_vcmpgtq_m_n_s<mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") (match_operand:<V_elem> 2 "s_register_operand" "r") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCMPGTQ_M_N_S)) ] "TARGET_HAVE_MVE" @@ -2921,10 +2921,10 @@ (define_insn "mve_vcmpgtq_m_n_s<mode>" ;; (define_insn "mve_vcmpgtq_m_s<mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCMPGTQ_M_S)) ] "TARGET_HAVE_MVE" @@ -2937,10 +2937,10 @@ (define_insn "mve_vcmpgtq_m_s<mode>" ;; (define_insn "mve_vcmphiq_m_n_u<mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") (match_operand:<V_elem> 2 "s_register_operand" "r") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCMPHIQ_M_N_U)) ] "TARGET_HAVE_MVE" @@ -2953,10 +2953,10 @@ (define_insn "mve_vcmphiq_m_n_u<mode>" ;; (define_insn "mve_vcmphiq_m_u<mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCMPHIQ_M_U)) ] "TARGET_HAVE_MVE" @@ -2969,10 +2969,10 @@ (define_insn "mve_vcmphiq_m_u<mode>" ;; (define_insn "mve_vcmpleq_m_n_s<mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") (match_operand:<V_elem> 2 "s_register_operand" "r") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCMPLEQ_M_N_S)) ] "TARGET_HAVE_MVE" @@ -2985,10 +2985,10 @@ (define_insn "mve_vcmpleq_m_n_s<mode>" ;; (define_insn "mve_vcmpleq_m_s<mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCMPLEQ_M_S)) ] "TARGET_HAVE_MVE" @@ -3001,10 +3001,10 @@ (define_insn "mve_vcmpleq_m_s<mode>" ;; (define_insn "mve_vcmpltq_m_n_s<mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") (match_operand:<V_elem> 2 "s_register_operand" "r") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCMPLTQ_M_N_S)) ] "TARGET_HAVE_MVE" @@ -3017,10 +3017,10 @@ (define_insn "mve_vcmpltq_m_n_s<mode>" ;; (define_insn "mve_vcmpltq_m_s<mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCMPLTQ_M_S)) ] "TARGET_HAVE_MVE" @@ -3033,10 +3033,10 @@ (define_insn "mve_vcmpltq_m_s<mode>" ;; (define_insn "mve_vcmpneq_m_n_<supf><mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") (match_operand:<V_elem> 2 "s_register_operand" "r") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCMPNEQ_M_N)) ] "TARGET_HAVE_MVE" @@ -3049,10 +3049,10 @@ (define_insn "mve_vcmpneq_m_n_<supf><mode>" ;; (define_insn "mve_vcmpneq_m_<supf><mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCMPNEQ_M)) ] "TARGET_HAVE_MVE" @@ -3782,10 +3782,10 @@ (define_insn "mve_vcmlaq<mve_rot><mode>" ;; (define_insn "mve_vcmpeqq_m_n_f<mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") (match_operand:<V_elem> 2 "s_register_operand" "r") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCMPEQQ_M_N_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -3798,10 +3798,10 @@ (define_insn "mve_vcmpeqq_m_n_f<mode>" ;; (define_insn "mve_vcmpgeq_m_f<mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") (match_operand:MVE_0 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCMPGEQ_M_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -3814,10 +3814,10 @@ (define_insn "mve_vcmpgeq_m_f<mode>" ;; (define_insn "mve_vcmpgeq_m_n_f<mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") (match_operand:<V_elem> 2 "s_register_operand" "r") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCMPGEQ_M_N_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -3830,10 +3830,10 @@ (define_insn "mve_vcmpgeq_m_n_f<mode>" ;; (define_insn "mve_vcmpgtq_m_f<mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") (match_operand:MVE_0 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCMPGTQ_M_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -3846,10 +3846,10 @@ (define_insn "mve_vcmpgtq_m_f<mode>" ;; (define_insn "mve_vcmpgtq_m_n_f<mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") (match_operand:<V_elem> 2 "s_register_operand" "r") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCMPGTQ_M_N_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -3862,10 +3862,10 @@ (define_insn "mve_vcmpgtq_m_n_f<mode>" ;; (define_insn "mve_vcmpleq_m_f<mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") (match_operand:MVE_0 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCMPLEQ_M_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -3878,10 +3878,10 @@ (define_insn "mve_vcmpleq_m_f<mode>" ;; (define_insn "mve_vcmpleq_m_n_f<mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") (match_operand:<V_elem> 2 "s_register_operand" "r") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCMPLEQ_M_N_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -3894,10 +3894,10 @@ (define_insn "mve_vcmpleq_m_n_f<mode>" ;; (define_insn "mve_vcmpltq_m_f<mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") (match_operand:MVE_0 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCMPLTQ_M_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -3910,10 +3910,10 @@ (define_insn "mve_vcmpltq_m_f<mode>" ;; (define_insn "mve_vcmpltq_m_n_f<mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") (match_operand:<V_elem> 2 "s_register_operand" "r") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCMPLTQ_M_N_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -3926,10 +3926,10 @@ (define_insn "mve_vcmpltq_m_n_f<mode>" ;; (define_insn "mve_vcmpneq_m_f<mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") (match_operand:MVE_0 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCMPNEQ_M_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -3942,10 +3942,10 @@ (define_insn "mve_vcmpneq_m_f<mode>" ;; (define_insn "mve_vcmpneq_m_n_f<mode>" [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") + (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") + (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") (match_operand:<V_elem> 2 "s_register_operand" "r") - (match_operand:HI 3 "vpr_register_operand" "Up")] + (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] VCMPNEQ_M_N_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"