From patchwork Fri Aug 13 13:51:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 1516671 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=WF4eBBqk; dkim-atps=neutral Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GmQ4S6vVhz9sRN for ; Fri, 13 Aug 2021 23:53:11 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 781F73998031 for ; Fri, 13 Aug 2021 13:53:08 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 781F73998031 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1628862788; bh=wD4NRjYrNZlBtGV+ExIFYq2Pw77uj7GVurZsuUhYcNE=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=WF4eBBqkEclzCZ7f+y9nfW01eDw4S3HNHg73kiAbpAWBppLY22GCzYPPEGWXg9LkR 35Hh/3uWYexTtl3PWV4han/5h03oaK4o8Bt1FMY4KCEVmJlYqjXXlCF0/fIq3khedc mTrqoPaAvbtwLppXtQE6Bh2gyC684jbvFPEMzPNU= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pj1-x102a.google.com (mail-pj1-x102a.google.com [IPv6:2607:f8b0:4864:20::102a]) by sourceware.org (Postfix) with ESMTPS id EF993399900F for ; Fri, 13 Aug 2021 13:51:16 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org EF993399900F Received: by mail-pj1-x102a.google.com with SMTP id m24-20020a17090a7f98b0290178b1a81700so16080230pjl.4 for ; Fri, 13 Aug 2021 06:51:16 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wD4NRjYrNZlBtGV+ExIFYq2Pw77uj7GVurZsuUhYcNE=; b=WV6a8crLtQXSP0R5C+M3NyyGgybmkKyRvgr6ZCkuv09SJGMccQWQtk+4sJoa72P28a /76qp5knAGqpZ3u1hbzEaQqYX/Z0HRwVN+S9jpM0lVfb6drcG6X/NR09nvR6wsoI7mFy jJboZ+Xj8U10QaM5FNH4DgU/vdrCG9pHJ6jKwlL6Ie7GvJWnA6XDFnkrNIyqrdlUYP7n QL30mEDA/o5Q4i4opT0SwNYs2C9dcudBSkcwwnH0M6UA/nCVcHDS/7JcZccehCt1xJhh 1kpQrpuaHjm+srQnNFVoEWXKGeXaLv+ch7zjh1AaeC7rgsdt6nOij25R5GFTH2BBI4wS 3c3A== X-Gm-Message-State: AOAM532N5N8ET0vNZob/SRLm01/KNjLPblVy4n+mFLtvboD/f75A50vy C/6JIXV/bRaWJEZyad9v6bRztq5RHNE= X-Google-Smtp-Source: ABdhPJx7Tktgm1YMuP7QCQ5w5HMAxyFUR6soexSbI0zmGZdajkWHwP7Oaovg6YC0vSj2fYkr8Neuew== X-Received: by 2002:a63:f241:: with SMTP id d1mr2415708pgk.424.1628862675760; Fri, 13 Aug 2021 06:51:15 -0700 (PDT) Received: from gnu-cfl-2.localdomain ([172.58.38.240]) by smtp.gmail.com with ESMTPSA id w3sm2484240pfn.96.2021.08.13.06.51.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Aug 2021 06:51:15 -0700 (PDT) Received: from gnu-tgl-2.localdomain (gnu-tgl-2 [192.168.1.34]) by gnu-cfl-2.localdomain (Postfix) with ESMTPS id BA16CC0302; Fri, 13 Aug 2021 06:51:13 -0700 (PDT) Received: from gnu-tgl-2.lan (localhost [IPv6:::1]) by gnu-tgl-2.localdomain (Postfix) with ESMTP id AC4E83002F1; Fri, 13 Aug 2021 06:51:03 -0700 (PDT) To: gcc-patches@gcc.gnu.org Subject: [PATCH 2/5] x86: Use crc32 target option for CRC32 intrinsics Date: Fri, 13 Aug 2021 06:51:00 -0700 Message-Id: <20210813135103.46696-3-hjl.tools@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210813135103.46696-1-hjl.tools@gmail.com> References: <20210813135103.46696-1-hjl.tools@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-3033.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "H.J. Lu via Gcc-patches" From: "H.J. Lu" Reply-To: "H.J. Lu" Cc: Jakub Jelinek Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Use crc32 target option for CRC32 intrinsics to support CRC32 intrinsics without enabling SSE vector instructions. * config/i386/i386-c.c (ix86_target_macros_internal): Define __CRC32__ for -mcrc32. * config/i386/i386-options.c (ix86_option_override_internal): Enable crc32 instruction for -msse4.2. * config/i386/i386.md (sse4_2_crc32): Remove TARGET_SSE4_2 check. (sse4_2_crc32di): Likewise. * config/i386/ia32intrin.h: Use crc32 target option for CRC32 intrinsics. (cherry picked from commit 39671f87b2df6a1894cc11a161e4a7949d1ddccd) --- gcc/config/i386/i386-c.c | 2 ++ gcc/config/i386/i386-options.c | 5 +++++ gcc/config/i386/i386.md | 4 ++-- gcc/config/i386/ia32intrin.h | 28 ++++++++++++++-------------- 4 files changed, 23 insertions(+), 16 deletions(-) diff --git a/gcc/config/i386/i386-c.c b/gcc/config/i386/i386-c.c index be46d0506ad..5ed0de006fb 100644 --- a/gcc/config/i386/i386-c.c +++ b/gcc/config/i386/i386-c.c @@ -532,6 +532,8 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, def_or_undef (parse_in, "__LZCNT__"); if (isa_flag & OPTION_MASK_ISA_TBM) def_or_undef (parse_in, "__TBM__"); + if (isa_flag & OPTION_MASK_ISA_CRC32) + def_or_undef (parse_in, "__CRC32__"); if (isa_flag & OPTION_MASK_ISA_POPCNT) def_or_undef (parse_in, "__POPCNT__"); if (isa_flag & OPTION_MASK_ISA_FSGSBASE) diff --git a/gcc/config/i386/i386-options.c b/gcc/config/i386/i386-options.c index 7ecd0cf8b8c..19632b5fd6b 100644 --- a/gcc/config/i386/i386-options.c +++ b/gcc/config/i386/i386-options.c @@ -2625,6 +2625,11 @@ ix86_option_override_internal (bool main_args_p, opts->x_ix86_isa_flags |= OPTION_MASK_ISA_POPCNT & ~opts->x_ix86_isa_flags_explicit; + /* Enable crc32 instruction for -msse4.2. */ + if (TARGET_SSE4_2_P (opts->x_ix86_isa_flags)) + opts->x_ix86_isa_flags + |= OPTION_MASK_ISA_CRC32 & ~opts->x_ix86_isa_flags_explicit; + /* Enable lzcnt instruction for -mabm. */ if (TARGET_ABM_P(opts->x_ix86_isa_flags)) opts->x_ix86_isa_flags diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 2fdf98266cd..1d528a4434a 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -20992,7 +20992,7 @@ (define_insn "sse4_2_crc32" [(match_operand:SI 1 "register_operand" "0") (match_operand:SWI124 2 "nonimmediate_operand" "m")] UNSPEC_CRC32))] - "TARGET_SSE4_2 || TARGET_CRC32" + "TARGET_CRC32" "crc32{}\t{%2, %0|%0, %2}" [(set_attr "type" "sselog1") (set_attr "prefix_rep" "1") @@ -21013,7 +21013,7 @@ (define_insn "sse4_2_crc32di" [(match_operand:DI 1 "register_operand" "0") (match_operand:DI 2 "nonimmediate_operand" "rm")] UNSPEC_CRC32))] - "TARGET_64BIT && (TARGET_SSE4_2 || TARGET_CRC32)" + "TARGET_64BIT && TARGET_CRC32" "crc32{q}\t{%2, %0|%0, %2}" [(set_attr "type" "sselog1") (set_attr "prefix_rep" "1") diff --git a/gcc/config/i386/ia32intrin.h b/gcc/config/i386/ia32intrin.h index 591394076cc..5422b0fc9e0 100644 --- a/gcc/config/i386/ia32intrin.h +++ b/gcc/config/i386/ia32intrin.h @@ -51,11 +51,11 @@ __bswapd (int __X) #ifndef __iamcu__ -#ifndef __SSE4_2__ +#ifndef __CRC32__ #pragma GCC push_options -#pragma GCC target("sse4.2") -#define __DISABLE_SSE4_2__ -#endif /* __SSE4_2__ */ +#pragma GCC target("crc32") +#define __DISABLE_CRC32__ +#endif /* __CRC32__ */ /* 32bit accumulate CRC32 (polynomial 0x11EDC6F41) value. */ extern __inline unsigned int @@ -79,10 +79,10 @@ __crc32d (unsigned int __C, unsigned int __V) return __builtin_ia32_crc32si (__C, __V); } -#ifdef __DISABLE_SSE4_2__ -#undef __DISABLE_SSE4_2__ +#ifdef __DISABLE_CRC32__ +#undef __DISABLE_CRC32__ #pragma GCC pop_options -#endif /* __DISABLE_SSE4_2__ */ +#endif /* __DISABLE_CRC32__ */ #endif /* __iamcu__ */ @@ -199,11 +199,11 @@ __bswapq (long long __X) return __builtin_bswap64 (__X); } -#ifndef __SSE4_2__ +#ifndef __CRC32__ #pragma GCC push_options -#pragma GCC target("sse4.2") -#define __DISABLE_SSE4_2__ -#endif /* __SSE4_2__ */ +#pragma GCC target("crc32") +#define __DISABLE_CRC32__ +#endif /* __CRC32__ */ /* 64bit accumulate CRC32 (polynomial 0x11EDC6F41) value. */ extern __inline unsigned long long @@ -213,10 +213,10 @@ __crc32q (unsigned long long __C, unsigned long long __V) return __builtin_ia32_crc32di (__C, __V); } -#ifdef __DISABLE_SSE4_2__ -#undef __DISABLE_SSE4_2__ +#ifdef __DISABLE_CRC32__ +#undef __DISABLE_CRC32__ #pragma GCC pop_options -#endif /* __DISABLE_SSE4_2__ */ +#endif /* __DISABLE_CRC32__ */ /* 64bit popcnt */ extern __inline long long