| Message ID | 20210701061648.9447-50-hongtao.liu@intel.com |
|---|---|
| State | New |
| Headers | show |
| Series | Support all AVX512FP16 intrinsics. | expand |
I'm going to check in 7 patches.
[PATCH 49/62] AVX512FP16: Add vfcmaddcph/vfmaddcph/vfcmulcph/vfmulcph
[PATCH 50/62] AVX512FP16: Add testcases for
vfcmaddcph/vfmaddcph/vfcmulcph/vfmulcph.
[PATCH 51/62] AVX512FP16: Add vfcmaddcsh/vfmaddcsh/vfcmulcsh/vfmulcsh.
[PATCH 52/62] AVX512FP16: Add testcases for
vfcmaddcsh/vfmaddcsh/vfcmulcsh/vfmulcsh.
[PATCH 53/62] AVX512FP16: Add expander for sqrthf2.
[PATCH 54/62] AVX512FP16: Add expander for ceil/floor/trunc/roundeven.
[PATCH 55/62] AVX512FP16: Add expander for cstorehf4.
bootstrapped and regtest on x86_64-pc-linux-gnu{-m32,}
Newly added runtime tests passed on sde{-m32,}.
On Thu, Jul 1, 2021 at 2:18 PM liuhongt <hongtao.liu@intel.com> wrote:
>
> gcc/ChangeLog:
>
> * config/i386/avx512fp16intrin.h (_mm512_fcmadd_pch):
> New intrinsic.
> (_mm512_mask_fcmadd_pch): Likewise.
> (_mm512_mask3_fcmadd_pch): Likewise.
> (_mm512_maskz_fcmadd_pch): Likewise.
> (_mm512_fmadd_pch): Likewise.
> (_mm512_mask_fmadd_pch): Likewise.
> (_mm512_mask3_fmadd_pch): Likewise.
> (_mm512_maskz_fmadd_pch): Likewise.
> (_mm512_fcmadd_round_pch): Likewise.
> (_mm512_mask_fcmadd_round_pch): Likewise.
> (_mm512_mask3_fcmadd_round_pch): Likewise.
> (_mm512_maskz_fcmadd_round_pch): Likewise.
> (_mm512_fmadd_round_pch): Likewise.
> (_mm512_mask_fmadd_round_pch): Likewise.
> (_mm512_mask3_fmadd_round_pch): Likewise.
> (_mm512_maskz_fmadd_round_pch): Likewise.
> (_mm512_fcmul_pch): Likewise.
> (_mm512_mask_fcmul_pch): Likewise.
> (_mm512_maskz_fcmul_pch): Likewise.
> (_mm512_fmul_pch): Likewise.
> (_mm512_mask_fmul_pch): Likewise.
> (_mm512_maskz_fmul_pch): Likewise.
> (_mm512_fcmul_round_pch): Likewise.
> (_mm512_mask_fcmul_round_pch): Likewise.
> (_mm512_maskz_fcmul_round_pch): Likewise.
> (_mm512_fmul_round_pch): Likewise.
> (_mm512_mask_fmul_round_pch): Likewise.
> (_mm512_maskz_fmul_round_pch): Likewise.
> * config/i386/avx512fp16vlintrin.h (_mm_fmadd_pch):
> New intrinsic.
> (_mm_mask_fmadd_pch): Likewise.
> (_mm_mask3_fmadd_pch): Likewise.
> (_mm_maskz_fmadd_pch): Likewise.
> (_mm256_fmadd_pch): Likewise.
> (_mm256_mask_fmadd_pch): Likewise.
> (_mm256_mask3_fmadd_pch): Likewise.
> (_mm256_maskz_fmadd_pch): Likewise.
> (_mm_fcmadd_pch): Likewise.
> (_mm_mask_fcmadd_pch): Likewise.
> (_mm_mask3_fcmadd_pch): Likewise.
> (_mm_maskz_fcmadd_pch): Likewise.
> (_mm256_fcmadd_pch): Likewise.
> (_mm256_mask_fcmadd_pch): Likewise.
> (_mm256_mask3_fcmadd_pch): Likewise.
> (_mm256_maskz_fcmadd_pch): Likewise.
> (_mm_fmul_pch): Likewise.
> (_mm_mask_fmul_pch): Likewise.
> (_mm_maskz_fmul_pch): Likewise.
> (_mm256_fmul_pch): Likewise.
> (_mm256_mask_fmul_pch): Likewise.
> (_mm256_maskz_fmul_pch): Likewise.
> (_mm_fcmul_pch): Likewise.
> (_mm_mask_fcmul_pch): Likewise.
> (_mm_maskz_fcmul_pch): Likewise.
> (_mm256_fcmul_pch): Likewise.
> (_mm256_mask_fcmul_pch): Likewise.
> (_mm256_maskz_fcmul_pch): Likewise.
> * config/i386/i386-builtin-types.def (V8HF_FTYPE_V8HF_V8HF_V8HF,
> V8HF_FTYPE_V16HF_V16HF_V16HF, V16HF_FTYPE_V16HF_V16HF_V16HF_UQI,
> V32HF_FTYPE_V32HF_V32HF_V32HF_INT,
> V32HF_FTYPE_V32HF_V32HF_V32HF_UHI_INT): Add new builtin types.
> * config/i386/i386-builtin.def: Add new builtins.
> * config/i386/i386-expand.c: Handle new builtin types.
> * config/i386/subst.md (SUBST_CV): New.
> (maskc_name): Ditto.
> (maskc_operand3): Ditto.
> (maskc): Ditto.
> (sdc_maskz_name): Ditto.
> (sdc_mask_op4): Ditto.
> (sdc_mask_op5): Ditto.
> (sdc_mask_mode512bit_condition): Ditto.
> (sdc): Ditto.
> (round_maskc_operand3): Ditto.
> (round_sdc_mask_operand4): Ditto.
> (round_maskc_op3): Ditto.
> (round_sdc_mask_op4): Ditto.
> (round_saeonly_sdc_mask_operand5): Ditto.
> * config/i386/sse.md (unspec): Add complex fma unspecs.
> (avx512fmaskcmode): New.
> (UNSPEC_COMPLEX_F_C_MA): Ditto.
> (UNSPEC_COMPLEX_F_C_MUL): Ditto.
> (complexopname): Ditto.
> (<avx512>_fmaddc_<mode>_maskz<round_expand_name>): New expander.
> (<avx512>_fcmaddc_<mode>_maskz<round_expand_name>): Ditto.
> (fma_<complexopname>_<mode><sdc_maskz_name><round_name>): New
> define insn.
> (<avx512>_<complexopname>_<mode>_mask<round_name>): Ditto.
> (<avx512>_<complexopname>_<mode><maskc_name><round_name>): Ditto.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/i386/avx-1.c: Add test for new builtins.
> * gcc.target/i386/sse-13.c: Ditto.
> * gcc.target/i386/sse-23.c: Ditto.
> * gcc.target/i386/sse-14.c: Add test for new intrinsics.
> * gcc.target/i386/sse-22.c: Ditto.
> ---
> gcc/config/i386/avx512fp16intrin.h | 386 +++++++++++++++++++++++++
> gcc/config/i386/avx512fp16vlintrin.h | 257 ++++++++++++++++
> gcc/config/i386/i386-builtin-types.def | 5 +
> gcc/config/i386/i386-builtin.def | 30 ++
> gcc/config/i386/i386-expand.c | 5 +
> gcc/config/i386/sse.md | 98 +++++++
> gcc/config/i386/subst.md | 40 +++
> gcc/testsuite/gcc.target/i386/avx-1.c | 10 +
> gcc/testsuite/gcc.target/i386/sse-13.c | 10 +
> gcc/testsuite/gcc.target/i386/sse-14.c | 14 +
> gcc/testsuite/gcc.target/i386/sse-22.c | 14 +
> gcc/testsuite/gcc.target/i386/sse-23.c | 10 +
> 12 files changed, 879 insertions(+)
>
> diff --git a/gcc/config/i386/avx512fp16intrin.h b/gcc/config/i386/avx512fp16intrin.h
> index 5c85ec15b22..9dd71019972 100644
> --- a/gcc/config/i386/avx512fp16intrin.h
> +++ b/gcc/config/i386/avx512fp16intrin.h
> @@ -6109,6 +6109,392 @@ _mm_maskz_fnmsub_round_sh (__mmask8 __U, __m128h __W, __m128h __A,
>
> #endif /* __OPTIMIZE__ */
>
> +/* Intrinsics vf[,c]maddcph. */
> +extern __inline __m512h
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm512_fcmadd_pch (__m512h __A, __m512h __B, __m512h __C)
> +{
> + return (__m512h)
> + __builtin_ia32_vfcmaddcph_v32hf_round ((__v32hf) __C,
> + (__v32hf) __A,
> + (__v32hf) __B,
> + _MM_FROUND_CUR_DIRECTION);
> +}
> +
> +extern __inline __m512h
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm512_mask_fcmadd_pch (__m512h __A, __mmask16 __B, __m512h __C, __m512h __D)
> +{
> + return (__m512h) __builtin_ia32_movaps512_mask
> + ((__v16sf)
> + __builtin_ia32_vfcmaddcph_v32hf_mask_round ((__v32hf) __D,
> + (__v32hf) __A,
> + (__v32hf) __C, __B,
> + _MM_FROUND_CUR_DIRECTION),
> + (__v16sf) __A, __B);
> +}
> +
> +extern __inline __m512h
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm512_mask3_fcmadd_pch (__m512h __A, __m512h __B, __m512h __C, __mmask16 __D)
> +{
> + return (__m512h)
> + __builtin_ia32_vfcmaddcph_v32hf_mask_round ((__v32hf) __C,
> + (__v32hf) __A,
> + (__v32hf) __B,
> + __D, _MM_FROUND_CUR_DIRECTION);
> +}
> +
> +extern __inline __m512h
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm512_maskz_fcmadd_pch (__mmask16 __A, __m512h __B, __m512h __C, __m512h __D)
> +{
> + return (__m512h)
> + __builtin_ia32_vfcmaddcph_v32hf_maskz_round((__v32hf) __D,
> + (__v32hf) __B,
> + (__v32hf) __C,
> + __A, _MM_FROUND_CUR_DIRECTION);
> +}
> +
> +extern __inline __m512h
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm512_fmadd_pch (__m512h __A, __m512h __B, __m512h __C)
> +{
> + return (__m512h)
> + __builtin_ia32_vfmaddcph_v32hf_round((__v32hf) __C,
> + (__v32hf) __A,
> + (__v32hf) __B,
> + _MM_FROUND_CUR_DIRECTION);
> +}
> +
> +extern __inline __m512h
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm512_mask_fmadd_pch (__m512h __A, __mmask16 __B, __m512h __C, __m512h __D)
> +{
> + return (__m512h) __builtin_ia32_movaps512_mask
> + ((__v16sf)
> + __builtin_ia32_vfmaddcph_v32hf_mask_round ((__v32hf) __D,
> + (__v32hf) __A,
> + (__v32hf) __C, __B,
> + _MM_FROUND_CUR_DIRECTION),
> + (__v16sf) __A, __B);
> +}
> +
> +extern __inline __m512h
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm512_mask3_fmadd_pch (__m512h __A, __m512h __B, __m512h __C, __mmask16 __D)
> +{
> + return (__m512h)
> + __builtin_ia32_vfmaddcph_v32hf_mask_round((__v32hf) __C,
> + (__v32hf) __A,
> + (__v32hf) __B,
> + __D, _MM_FROUND_CUR_DIRECTION);
> +}
> +
> +extern __inline __m512h
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm512_maskz_fmadd_pch (__mmask16 __A, __m512h __B, __m512h __C, __m512h __D)
> +{
> + return (__m512h)
> + __builtin_ia32_vfmaddcph_v32hf_maskz_round((__v32hf) __D,
> + (__v32hf) __B,
> + (__v32hf) __C,
> + __A, _MM_FROUND_CUR_DIRECTION);
> +}
> +
> +#ifdef __OPTIMIZE__
> +extern __inline __m512h
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm512_fcmadd_round_pch (__m512h __A, __m512h __B, __m512h __C, const int __D)
> +{
> + return (__m512h)__builtin_ia32_vfcmaddcph_v32hf_round((__v32hf) __C,
> + (__v32hf) __A,
> + (__v32hf) __B,
> + __D);
> +}
> +
> +extern __inline __m512h
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm512_mask_fcmadd_round_pch (__m512h __A, __mmask16 __B, __m512h __C,
> + __m512h __D, const int __E)
> +{
> + return (__m512h) __builtin_ia32_movaps512_mask
> + ((__v16sf)
> + __builtin_ia32_vfcmaddcph_v32hf_mask_round ((__v32hf) __D,
> + (__v32hf) __A,
> + (__v32hf) __C, __B,
> + __E),
> + (__v16sf) __A, __B);
> +}
> +
> +extern __inline __m512h
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm512_mask3_fcmadd_round_pch (__m512h __A, __m512h __B, __m512h __C,
> + __mmask16 __D, const int __E)
> +{
> + return (__m512h)
> + __builtin_ia32_vfcmaddcph_v32hf_mask_round ((__v32hf) __C,
> + (__v32hf) __A,
> + (__v32hf) __B,
> + __D, __E);
> +}
> +
> +extern __inline __m512h
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm512_maskz_fcmadd_round_pch (__mmask16 __A, __m512h __B, __m512h __C,
> + __m512h __D, const int __E)
> +{
> + return (__m512h)__builtin_ia32_vfcmaddcph_v32hf_maskz_round((__v32hf) __D,
> + (__v32hf) __B,
> + (__v32hf) __C,
> + __A,
> + __E);
> +}
> +
> +extern __inline __m512h
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm512_fmadd_round_pch (__m512h __A, __m512h __B, __m512h __C, const int __D)
> +{
> + return (__m512h)
> + __builtin_ia32_vfmaddcph_v32hf_round ((__v32hf) __C,
> + (__v32hf) __A,
> + (__v32hf) __B,
> + __D);
> +}
> +
> +extern __inline __m512h
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm512_mask_fmadd_round_pch (__m512h __A, __mmask16 __B, __m512h __C,
> + __m512h __D, const int __E)
> +{
> + return (__m512h) __builtin_ia32_movaps512_mask
> + ((__v16sf)
> + __builtin_ia32_vfmaddcph_v32hf_mask_round ((__v32hf) __D,
> + (__v32hf) __A,
> + (__v32hf) __C, __B,
> + __E),
> + (__v16sf) __A, __B);
> +}
> +
> +extern __inline __m512h
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm512_mask3_fmadd_round_pch (__m512h __A, __m512h __B, __m512h __C,
> + __mmask16 __D, const int __E)
> +{
> + return (__m512h)
> + __builtin_ia32_vfmaddcph_v32hf_mask_round ((__v32hf) __C,
> + (__v32hf) __A,
> + (__v32hf) __B,
> + __D, __E);
> +}
> +
> +extern __inline __m512h
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm512_maskz_fmadd_round_pch (__mmask16 __A, __m512h __B, __m512h __C,
> + __m512h __D, const int __E)
> +{
> + return (__m512h)__builtin_ia32_vfmaddcph_v32hf_maskz_round((__v32hf) __D,
> + (__v32hf) __B,
> + (__v32hf) __C,
> + __A, __E);
> +}
> +
> +#else
> +#define _mm512_fcmadd_round_pch(A, B, C, D) \
> + (__m512h) __builtin_ia32_vfcmaddcph_v32hf_round ((C), (A), (B), (D))
> +
> +#define _mm512_mask_fcmadd_round_pch(A, B, C, D, E) \
> + ((__m512h) __builtin_ia32_movaps512_mask ( \
> + (__v16sf) \
> + __builtin_ia32_vfcmaddcph_v32hf_mask_round ((__v32hf) (D), \
> + (__v32hf) (A), \
> + (__v32hf) (C), \
> + (B), (E)), \
> + (__v16sf) (A), (B)));
> +
> +
> +#define _mm512_mask3_fcmadd_round_pch(A, B, C, D, E) \
> + ((__m512h) \
> + __builtin_ia32_vfcmaddcph_v32hf_mask_round ((C), (A), (B), (D), (E)))
> +
> +#define _mm512_maskz_fcmadd_round_pch(A, B, C, D, E) \
> + (__m512h) \
> + __builtin_ia32_vfcmaddcph_v32hf_maskz_round((D), (B), (C), (A), (E))
> +
> +#define _mm512_fmadd_round_pch(A, B, C, D) \
> + (__m512h) __builtin_ia32_vfmaddcph_v32hf_round((C), (A), (B), (D))
> +
> +#define _mm512_mask_fmadd_round_pch(A, B, C, D, E) \
> + ((__m512h) __builtin_ia32_movaps512_mask ( \
> + (__v16sf) \
> + __builtin_ia32_vfmaddcph_v32hf_mask_round ((__v32hf) (D), \
> + (__v32hf) (A), \
> + (__v32hf) (C), \
> + (B), (E)), \
> + (__v16sf) (A), (B)));
> +
> +#define _mm512_mask3_fmadd_round_pch(A, B, C, D, E) \
> + (__m512h) \
> + __builtin_ia32_vfmaddcph_v32hf_mask_round((C), (A), (B), (D), (E))
> +
> +#define _mm512_maskz_fmadd_round_pch(A, B, C, D, E) \
> + (__m512h) \
> + __builtin_ia32_vfmaddcph_v32hf_maskz_round((D), (B), (C), (A), (E))
> +
> +#endif /* __OPTIMIZE__ */
> +
> +/* Intrinsics vf[,c]mulcph. */
> +extern __inline __m512h
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm512_fcmul_pch (__m512h __A, __m512h __B)
> +{
> + return (__m512h)
> + __builtin_ia32_vfcmulcph_v32hf_round((__v32hf) __A,
> + (__v32hf) __B,
> + _MM_FROUND_CUR_DIRECTION);
> +}
> +
> +extern __inline __m512h
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm512_mask_fcmul_pch (__m512h __A, __mmask16 __B, __m512h __C, __m512h __D)
> +{
> + return (__m512h)
> + __builtin_ia32_vfcmulcph_v32hf_mask_round((__v32hf) __C,
> + (__v32hf) __D,
> + (__v32hf) __A,
> + __B, _MM_FROUND_CUR_DIRECTION);
> +}
> +
> +extern __inline __m512h
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm512_maskz_fcmul_pch (__mmask16 __A, __m512h __B, __m512h __C)
> +{
> + return (__m512h)
> + __builtin_ia32_vfcmulcph_v32hf_mask_round((__v32hf) __B,
> + (__v32hf) __C,
> + _mm512_setzero_ph (),
> + __A, _MM_FROUND_CUR_DIRECTION);
> +}
> +
> +extern __inline __m512h
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm512_fmul_pch (__m512h __A, __m512h __B)
> +{
> + return (__m512h)
> + __builtin_ia32_vfmulcph_v32hf_round((__v32hf) __A,
> + (__v32hf) __B,
> + _MM_FROUND_CUR_DIRECTION);
> +}
> +
> +extern __inline __m512h
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm512_mask_fmul_pch (__m512h __A, __mmask16 __B, __m512h __C, __m512h __D)
> +{
> + return (__m512h)
> + __builtin_ia32_vfmulcph_v32hf_mask_round((__v32hf) __C,
> + (__v32hf) __D,
> + (__v32hf) __A,
> + __B, _MM_FROUND_CUR_DIRECTION);
> +}
> +
> +extern __inline __m512h
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm512_maskz_fmul_pch (__mmask16 __A, __m512h __B, __m512h __C)
> +{
> + return (__m512h)
> + __builtin_ia32_vfmulcph_v32hf_mask_round((__v32hf) __B,
> + (__v32hf) __C,
> + _mm512_setzero_ph (),
> + __A, _MM_FROUND_CUR_DIRECTION);
> +}
> +
> +#ifdef __OPTIMIZE__
> +extern __inline __m512h
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm512_fcmul_round_pch (__m512h __A, __m512h __B, const int __D)
> +{
> + return (__m512h)__builtin_ia32_vfcmulcph_v32hf_round((__v32hf) __A,
> + (__v32hf) __B, __D);
> +}
> +
> +extern __inline __m512h
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm512_mask_fcmul_round_pch (__m512h __A, __mmask16 __B, __m512h __C,
> + __m512h __D, const int __E)
> +{
> + return (__m512h)__builtin_ia32_vfcmulcph_v32hf_mask_round((__v32hf) __C,
> + (__v32hf) __D,
> + (__v32hf) __A,
> + __B, __E);
> +}
> +
> +extern __inline __m512h
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm512_maskz_fcmul_round_pch (__mmask16 __A, __m512h __B,
> + __m512h __C, const int __E)
> +{
> + return (__m512h)__builtin_ia32_vfcmulcph_v32hf_mask_round((__v32hf) __B,
> + (__v32hf) __C,
> + _mm512_setzero_ph (),
> + __A, __E);
> +}
> +
> +extern __inline __m512h
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm512_fmul_round_pch (__m512h __A, __m512h __B, const int __D)
> +{
> + return (__m512h)__builtin_ia32_vfmulcph_v32hf_round((__v32hf) __A,
> + (__v32hf) __B,
> + __D);
> +}
> +
> +extern __inline __m512h
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm512_mask_fmul_round_pch (__m512h __A, __mmask16 __B, __m512h __C,
> + __m512h __D, const int __E)
> +{
> + return (__m512h)__builtin_ia32_vfmulcph_v32hf_mask_round((__v32hf) __C,
> + (__v32hf) __D,
> + (__v32hf) __A,
> + __B, __E);
> +}
> +
> +extern __inline __m512h
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm512_maskz_fmul_round_pch (__mmask16 __A, __m512h __B,
> + __m512h __C, const int __E)
> +{
> + return (__m512h)__builtin_ia32_vfmulcph_v32hf_mask_round((__v32hf) __B,
> + (__v32hf) __C,
> + _mm512_setzero_ph (),
> + __A, __E);
> +}
> +
> +#else
> +#define _mm512_fcmul_round_pch(A, B, D) \
> + (__m512h)__builtin_ia32_vfcmulcph_v32hf_round(A, B, D)
> +
> +#define _mm512_mask_fcmul_round_pch(A, B, C, D, E) \
> + (__m512h)__builtin_ia32_vfcmulcph_v32hf_mask_round(C, D, A, B, E)
> +
> +#define _mm512_maskz_fcmul_round_pch(A, B, C, E) \
> + (__m512h)__builtin_ia32_vfcmulcph_v32hf_mask_round(B, C, \
> + _mm512_setzero_ph(), \
> + A, E)
> +
> +#define _mm512_fmul_round_pch(A, B, D) \
> + (__m512h)__builtin_ia32_vfmulcph_v32hf_round(A, B, D)
> +
> +#define _mm512_mask_fmul_round_pch(A, B, C, D, E) \
> + (__m512h)__builtin_ia32_vfmulcph_v32hf_mask_round(C, D, A, B, E)
> +
> +#define _mm512_maskz_fmul_round_pch(A, B, C, E) \
> + (__m512h)__builtin_ia32_vfmulcph_v32hf_mask_round(B, C, \
> + _mm512_setzero_ph (), \
> + A, E)
> +
> +#endif /* __OPTIMIZE__ */
> +
> #ifdef __DISABLE_AVX512FP16__
> #undef __DISABLE_AVX512FP16__
> #pragma GCC pop_options
> diff --git a/gcc/config/i386/avx512fp16vlintrin.h b/gcc/config/i386/avx512fp16vlintrin.h
> index bba98f105ac..c7bdfbc0517 100644
> --- a/gcc/config/i386/avx512fp16vlintrin.h
> +++ b/gcc/config/i386/avx512fp16vlintrin.h
> @@ -2815,6 +2815,263 @@ _mm_maskz_fnmsub_ph (__mmask8 __U, __m128h __A, __m128h __B,
> __U);
> }
>
> +/* Intrinsics vf[,c]maddcph. */
> +extern __inline __m128h
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm_fmadd_pch (__m128h __A, __m128h __B, __m128h __C)
> +{
> + return (__m128h)__builtin_ia32_vfmaddcph_v8hf((__v8hf) __C, (__v8hf) __A,
> + (__v8hf) __B);
> +}
> +
> +extern __inline __m128h
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm_mask_fmadd_pch (__m128h __A, __mmask8 __B, __m128h __C, __m128h __D)
> +{
> + return (__m128h) __builtin_ia32_movaps128_mask
> + ((__v4sf)
> + __builtin_ia32_vfmaddcph_v8hf_mask ((__v8hf) __D,
> + (__v8hf) __A,
> + (__v8hf) __C, __B),
> + (__v4sf) __A, __B);
> +}
> +
> +extern __inline __m128h
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm_mask3_fmadd_pch (__m128h __A, __m128h __B, __m128h __C, __mmask8 __D)
> +{
> + return (__m128h) __builtin_ia32_vfmaddcph_v8hf_mask ((__v8hf) __C,
> + (__v8hf) __A,
> + (__v8hf) __B, __D);
> +}
> +
> +extern __inline __m128h
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm_maskz_fmadd_pch (__mmask8 __A, __m128h __B, __m128h __C, __m128h __D)
> +{
> + return (__m128h)__builtin_ia32_vfmaddcph_v8hf_maskz((__v8hf) __D,
> + (__v8hf) __B,
> + (__v8hf) __C, __A);
> +}
> +
> +extern __inline __m256h
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm256_fmadd_pch (__m256h __A, __m256h __B, __m256h __C)
> +{
> + return (__m256h)__builtin_ia32_vfmaddcph_v16hf((__v16hf) __C, (__v16hf) __A,
> + (__v16hf) __B);
> +}
> +
> +extern __inline __m256h
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm256_mask_fmadd_pch (__m256h __A, __mmask8 __B, __m256h __C, __m256h __D)
> +{
> + return (__m256h) __builtin_ia32_movaps256_mask
> + ((__v8sf)
> + __builtin_ia32_vfmaddcph_v16hf_mask ((__v16hf) __D,
> + (__v16hf) __A,
> + (__v16hf) __C, __B),
> + (__v8sf) __A, __B);
> +}
> +
> +extern __inline __m256h
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm256_mask3_fmadd_pch (__m256h __A, __m256h __B, __m256h __C, __mmask8 __D)
> +{
> + return (__m256h) __builtin_ia32_vfmaddcph_v16hf_mask ((__v16hf) __C,
> + (__v16hf) __A,
> + (__v16hf) __B, __D);
> +}
> +
> +extern __inline __m256h
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm256_maskz_fmadd_pch (__mmask8 __A, __m256h __B, __m256h __C, __m256h __D)
> +{
> + return (__m256h)__builtin_ia32_vfmaddcph_v16hf_maskz((__v16hf) __D,
> + (__v16hf) __B,
> + (__v16hf) __C, __A);
> +}
> +
> +extern __inline __m128h
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm_fcmadd_pch (__m128h __A, __m128h __B, __m128h __C)
> +{
> + return (__m128h)__builtin_ia32_vfcmaddcph_v8hf ((__v8hf) __C,
> + (__v8hf) __A, (__v8hf) __B);
> +}
> +
> +extern __inline __m128h
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm_mask_fcmadd_pch (__m128h __A, __mmask8 __B, __m128h __C, __m128h __D)
> +{
> + return (__m128h)__builtin_ia32_movaps128_mask
> + ((__v4sf)
> + __builtin_ia32_vfcmaddcph_v8hf_mask ((__v8hf) __D,
> + (__v8hf) __A,
> + (__v8hf) __C, __B),
> + (__v4sf) __A, __B);
> +}
> +
> +extern __inline __m128h
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm_mask3_fcmadd_pch (__m128h __A, __m128h __B, __m128h __C, __mmask8 __D)
> +{
> + return (__m128h) __builtin_ia32_vfcmaddcph_v8hf_mask ((__v8hf) __C,
> + (__v8hf) __A,
> + (__v8hf) __B, __D);
> +}
> +
> +extern __inline __m128h
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm_maskz_fcmadd_pch (__mmask8 __A, __m128h __B, __m128h __C, __m128h __D)
> +{
> + return (__m128h)__builtin_ia32_vfcmaddcph_v8hf_maskz ((__v8hf) __D,
> + (__v8hf) __B,
> + (__v8hf) __C, __A);
> +}
> +
> +extern __inline __m256h
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm256_fcmadd_pch (__m256h __A, __m256h __B, __m256h __C)
> +{
> + return (__m256h)__builtin_ia32_vfcmaddcph_v16hf((__v16hf) __C,
> + (__v16hf) __A, (__v16hf) __B);
> +}
> +
> +extern __inline __m256h
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm256_mask_fcmadd_pch (__m256h __A, __mmask8 __B, __m256h __C, __m256h __D)
> +{
> + return (__m256h) __builtin_ia32_movaps256_mask
> + ((__v8sf)
> + __builtin_ia32_vfcmaddcph_v16hf_mask ((__v16hf) __D,
> + (__v16hf) __A,
> + (__v16hf) __C, __B),
> + (__v8sf) __A, __B);
> +}
> +
> +extern __inline __m256h
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm256_mask3_fcmadd_pch (__m256h __A, __m256h __B, __m256h __C, __mmask8 __D)
> +{
> + return (__m256h) __builtin_ia32_vfcmaddcph_v16hf_mask ((__v16hf) __C,
> + (__v16hf) __A,
> + (__v16hf) __B, __D);
> +}
> +
> +extern __inline __m256h
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm256_maskz_fcmadd_pch (__mmask8 __A, __m256h __B, __m256h __C, __m256h __D)
> +{
> + return (__m256h)__builtin_ia32_vfcmaddcph_v16hf_maskz((__v16hf) __D,
> + (__v16hf) __B,
> + (__v16hf) __C, __A);
> +}
> +
> +/* Intrinsics vf[,c]mulcph. */
> +extern __inline __m128h
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm_fmul_pch (__m128h __A, __m128h __B)
> +{
> + return (__m128h)__builtin_ia32_vfmulcph_v8hf((__v8hf) __A, (__v8hf) __B);
> +}
> +
> +extern __inline __m128h
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm_mask_fmul_pch (__m128h __A, __mmask8 __B, __m128h __C, __m128h __D)
> +{
> + return (__m128h)__builtin_ia32_vfmulcph_v8hf_mask((__v8hf) __C,
> + (__v8hf) __D,
> + (__v8hf) __A, __B);
> +}
> +
> +extern __inline __m128h
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm_maskz_fmul_pch (__mmask8 __A, __m128h __B, __m128h __C)
> +{
> + return (__m128h)__builtin_ia32_vfmulcph_v8hf_mask((__v8hf) __B,
> + (__v8hf) __C,
> + _mm_setzero_ph (),
> + __A);
> +}
> +
> +extern __inline __m256h
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm256_fmul_pch (__m256h __A, __m256h __B)
> +{
> + return (__m256h)__builtin_ia32_vfmulcph_v16hf((__v16hf) __A, (__v16hf) __B);
> +}
> +
> +extern __inline __m256h
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm256_mask_fmul_pch (__m256h __A, __mmask8 __B, __m256h __C, __m256h __D)
> +{
> + return (__m256h)__builtin_ia32_vfmulcph_v16hf_mask((__v16hf) __C,
> + (__v16hf) __D,
> + (__v16hf) __A, __B);
> +}
> +
> +extern __inline __m256h
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm256_maskz_fmul_pch (__mmask8 __A, __m256h __B, __m256h __C)
> +{
> + return (__m256h)__builtin_ia32_vfmulcph_v16hf_mask((__v16hf) __B,
> + (__v16hf) __C,
> + _mm256_setzero_ph (),
> + __A);
> +}
> +
> +extern __inline __m128h
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm_fcmul_pch (__m128h __A, __m128h __B)
> +{
> + return (__m128h)__builtin_ia32_vfcmulcph_v8hf((__v8hf) __A, (__v8hf) __B);
> +}
> +
> +extern __inline __m128h
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm_mask_fcmul_pch (__m128h __A, __mmask8 __B, __m128h __C, __m128h __D)
> +{
> + return (__m128h)__builtin_ia32_vfcmulcph_v8hf_mask((__v8hf) __C, (__v8hf) __D,
> + (__v8hf) __A, __B);
> +}
> +
> +extern __inline __m128h
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm_maskz_fcmul_pch (__mmask8 __A, __m128h __B, __m128h __C)
> +{
> + return (__m128h)__builtin_ia32_vfcmulcph_v8hf_mask((__v8hf) __B,
> + (__v8hf) __C,
> + _mm_setzero_ph (),
> + __A);
> +}
> +
> +extern __inline __m256h
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm256_fcmul_pch (__m256h __A, __m256h __B)
> +{
> + return (__m256h)__builtin_ia32_vfcmulcph_v16hf((__v16hf) __A, (__v16hf) __B);
> +}
> +
> +extern __inline __m256h
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm256_mask_fcmul_pch (__m256h __A, __mmask8 __B, __m256h __C, __m256h __D)
> +{
> + return (__m256h)__builtin_ia32_vfcmulcph_v16hf_mask((__v16hf) __C,
> + (__v16hf) __D,
> + (__v16hf) __A, __B);
> +}
> +
> +extern __inline __m256h
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +_mm256_maskz_fcmul_pch (__mmask8 __A, __m256h __B, __m256h __C)
> +{
> + return (__m256h)__builtin_ia32_vfcmulcph_v16hf_mask((__v16hf) __B,
> + (__v16hf) __C,
> + _mm256_setzero_ph (),
> + __A);
> +}
> +
> #ifdef __DISABLE_AVX512FP16VL__
> #undef __DISABLE_AVX512FP16VL__
> #pragma GCC pop_options
> diff --git a/gcc/config/i386/i386-builtin-types.def b/gcc/config/i386/i386-builtin-types.def
> index 22b924bf98d..35bcafd14e3 100644
> --- a/gcc/config/i386/i386-builtin-types.def
> +++ b/gcc/config/i386/i386-builtin-types.def
> @@ -1348,6 +1348,7 @@ DEF_FUNCTION_TYPE (V8DI, V8HF, V8DI, UQI, INT)
> DEF_FUNCTION_TYPE (V8DF, V8HF, V8DF, UQI, INT)
> DEF_FUNCTION_TYPE (V8HF, V8DI, V8HF, UQI, INT)
> DEF_FUNCTION_TYPE (V8HF, V8DF, V8HF, UQI, INT)
> +DEF_FUNCTION_TYPE (V8HF, V8HF, V8HF, V8HF)
> DEF_FUNCTION_TYPE (V8HF, V8HF, V8HF, V8HF, UQI, INT)
> DEF_FUNCTION_TYPE (V8HF, V2DF, V8HF, V8HF, UQI, INT)
> DEF_FUNCTION_TYPE (V8HF, V4SF, V8HF, V8HF, UQI, INT)
> @@ -1358,12 +1359,14 @@ DEF_FUNCTION_TYPE (V16HF, V16HF, V16HF)
> DEF_FUNCTION_TYPE (V16HI, V16HF, V16HI, UHI)
> DEF_FUNCTION_TYPE (V16HF, V16HI, V16HF, UHI)
> DEF_FUNCTION_TYPE (V16HF, V16HF, V16HF, UHI)
> +DEF_FUNCTION_TYPE (V16HF, V16HF, V16HF, V16HF)
> DEF_FUNCTION_TYPE (V16SI, V16HF, V16SI, UHI, INT)
> DEF_FUNCTION_TYPE (V16SF, V16HF, V16SF, UHI, INT)
> DEF_FUNCTION_TYPE (V16HF, V16HF, INT, V16HF, UHI)
> DEF_FUNCTION_TYPE (UHI, V16HF, V16HF, INT, UHI)
> DEF_FUNCTION_TYPE (V16HF, V16SI, V16HF, UHI, INT)
> DEF_FUNCTION_TYPE (V16HF, V16SF, V16HF, UHI, INT)
> +DEF_FUNCTION_TYPE (V16HF, V16HF, V16HF, V16HF, UQI)
> DEF_FUNCTION_TYPE (V16HF, V16HF, V16HF, V16HF, UHI)
> DEF_FUNCTION_TYPE (V32HF, V32HF, V32HF, USI)
> DEF_FUNCTION_TYPE (V32HF, V32HF, V32HF, INT)
> @@ -1371,7 +1374,9 @@ DEF_FUNCTION_TYPE (V32HI, V32HF, V32HI, USI, INT)
> DEF_FUNCTION_TYPE (V32HF, V32HI, V32HF, USI, INT)
> DEF_FUNCTION_TYPE (USI, V32HF, V32HF, INT, USI)
> DEF_FUNCTION_TYPE (V32HF, V32HF, V32HF, USI, INT)
> +DEF_FUNCTION_TYPE (V32HF, V32HF, V32HF, V32HF, INT)
> DEF_FUNCTION_TYPE (V32HF, V32HF, V32HF, V32HF, USI)
> DEF_FUNCTION_TYPE (USI, V32HF, V32HF, INT, USI, INT)
> +DEF_FUNCTION_TYPE (V32HF, V32HF, V32HF, V32HF, UHI, INT)
> DEF_FUNCTION_TYPE (V32HF, V32HF, V32HF, V32HF, USI, INT)
> DEF_FUNCTION_TYPE (V32HF, V32HF, INT, V32HF, USI, INT)
> diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def
> index f446a6ce5d3..448f9f75fa4 100644
> --- a/gcc/config/i386/i386-builtin.def
> +++ b/gcc/config/i386/i386-builtin.def
> @@ -2911,6 +2911,26 @@ BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512vl_
> BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512fp16_fnmsub_v8hf_mask, "__builtin_ia32_vfnmsubph128_mask", IX86_BUILTIN_VFNMSUBPH128_MASK, UNKNOWN, (int) V8HF_FTYPE_V8HF_V8HF_V8HF_UQI)
> BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512fp16_fnmsub_v8hf_mask3, "__builtin_ia32_vfnmsubph128_mask3", IX86_BUILTIN_VFNMSUBPH128_MASK3, UNKNOWN, (int) V8HF_FTYPE_V8HF_V8HF_V8HF_UQI)
> BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512fp16_fnmsub_v8hf_maskz, "__builtin_ia32_vfnmsubph128_maskz", IX86_BUILTIN_VFNMSUBPH128_MASKZ, UNKNOWN, (int) V8HF_FTYPE_V8HF_V8HF_V8HF_UQI)
> +BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_fma_fmaddc_v8hf, "__builtin_ia32_vfmaddcph_v8hf", IX86_BUILTIN_VFMADDCPH_V8HF, UNKNOWN, (int) V8HF_FTYPE_V8HF_V8HF_V8HF)
> +BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512fp16_fmaddc_v8hf_mask, "__builtin_ia32_vfmaddcph_v8hf_mask", IX86_BUILTIN_VFMADDCPH_V8HF_MASK, UNKNOWN, (int) V8HF_FTYPE_V8HF_V8HF_V8HF_UQI)
> +BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512fp16_fmaddc_v8hf_maskz, "__builtin_ia32_vfmaddcph_v8hf_maskz", IX86_BUILTIN_VFMADDCPH_V8HF_MASKZ, UNKNOWN, (int) V8HF_FTYPE_V8HF_V8HF_V8HF_UQI)
> +BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_fma_fmaddc_v16hf, "__builtin_ia32_vfmaddcph_v16hf", IX86_BUILTIN_VFMADDCPH_V16HF, UNKNOWN, (int) V16HF_FTYPE_V16HF_V16HF_V16HF)
> +BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512vl_fmaddc_v16hf_mask, "__builtin_ia32_vfmaddcph_v16hf_mask", IX86_BUILTIN_VFMADDCPH_V16HF_MASK, UNKNOWN, (int) V16HF_FTYPE_V16HF_V16HF_V16HF_UQI)
> +BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512vl_fmaddc_v16hf_maskz, "__builtin_ia32_vfmaddcph_v16hf_maskz", IX86_BUILTIN_VFMADDCPH_V16HF_MASKZ, UNKNOWN, (int) V16HF_FTYPE_V16HF_V16HF_V16HF_UQI)
> +BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_fma_fcmaddc_v8hf, "__builtin_ia32_vfcmaddcph_v8hf", IX86_BUILTIN_VFCMADDCPH_V8HF, UNKNOWN, (int) V8HF_FTYPE_V8HF_V8HF_V8HF)
> +BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512fp16_fcmaddc_v8hf_mask, "__builtin_ia32_vfcmaddcph_v8hf_mask", IX86_BUILTIN_VFCMADDCPH_V8HF_MASK, UNKNOWN, (int) V8HF_FTYPE_V8HF_V8HF_V8HF_UQI)
> +BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512fp16_fcmaddc_v8hf_maskz, "__builtin_ia32_vfcmaddcph_v8hf_maskz", IX86_BUILTIN_VFCMADDCPH_V8HF_MASKZ, UNKNOWN, (int) V8HF_FTYPE_V8HF_V8HF_V8HF_UQI)
> +BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_fma_fcmaddc_v16hf, "__builtin_ia32_vfcmaddcph_v16hf", IX86_BUILTIN_VFCMADDCPH_V16HF, UNKNOWN, (int) V16HF_FTYPE_V16HF_V16HF_V16HF)
> +BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512vl_fcmaddc_v16hf_mask, "__builtin_ia32_vfcmaddcph_v16hf_mask", IX86_BUILTIN_VFCMADDCPH_V16HF_MASK, UNKNOWN, (int) V16HF_FTYPE_V16HF_V16HF_V16HF_UQI)
> +BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512vl_fcmaddc_v16hf_maskz, "__builtin_ia32_vfcmaddcph_v16hf_maskz", IX86_BUILTIN_VFCMADDCPH_V16HF_MASKZ, UNKNOWN, (int) V16HF_FTYPE_V16HF_V16HF_V16HF_UQI)
> +BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512fp16_fcmulc_v8hf, "__builtin_ia32_vfcmulcph_v8hf", IX86_BUILTIN_VFCMULCPH_V8HF, UNKNOWN, (int) V8HF_FTYPE_V8HF_V8HF)
> +BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512fp16_fcmulc_v8hf_mask, "__builtin_ia32_vfcmulcph_v8hf_mask", IX86_BUILTIN_VFCMULCPH_V8HF_MASK, UNKNOWN, (int) V8HF_FTYPE_V8HF_V8HF_V8HF_UQI)
> +BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512vl_fcmulc_v16hf, "__builtin_ia32_vfcmulcph_v16hf", IX86_BUILTIN_VFCMULCPH_V16HF, UNKNOWN, (int) V16HF_FTYPE_V16HF_V16HF)
> +BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512vl_fcmulc_v16hf_mask, "__builtin_ia32_vfcmulcph_v16hf_mask", IX86_BUILTIN_VFCMULCPH_V16HF_MASK, UNKNOWN, (int) V16HF_FTYPE_V16HF_V16HF_V16HF_UQI)
> +BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512fp16_fmulc_v8hf, "__builtin_ia32_vfmulcph_v8hf", IX86_BUILTIN_VFMULCPH_V8HF, UNKNOWN, (int) V8HF_FTYPE_V8HF_V8HF)
> +BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512fp16_fmulc_v8hf_mask, "__builtin_ia32_vfmulcph_v8hf_mask", IX86_BUILTIN_VFMULCPH_V8HF_MASK, UNKNOWN, (int) V8HF_FTYPE_V8HF_V8HF_V8HF_UQI)
> +BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512vl_fmulc_v16hf, "__builtin_ia32_vfmulcph_v16hf", IX86_BUILTIN_VFMULCPH_V16HF, UNKNOWN, (int) V16HF_FTYPE_V16HF_V16HF)
> +BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512vl_fmulc_v16hf_mask, "__builtin_ia32_vfmulcph_v16hf_mask", IX86_BUILTIN_VFMULCPH_V16HF_MASK, UNKNOWN, (int) V16HF_FTYPE_V16HF_V16HF_V16HF_UQI)
>
> /* Builtins with rounding support. */
> BDESC_END (ARGS, ROUND_ARGS)
> @@ -3201,6 +3221,16 @@ BDESC (0, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512f_vmfnmadd_v8hf_mask_round
> BDESC (0, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512f_vmfnmadd_v8hf_mask3_round, "__builtin_ia32_vfnmaddsh3_mask3", IX86_BUILTIN_VFNMADDSH3_MASK3, UNKNOWN, (int) V8HF_FTYPE_V8HF_V8HF_V8HF_UQI_INT)
> BDESC (0, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512f_vmfnmadd_v8hf_maskz_round, "__builtin_ia32_vfnmaddsh3_maskz", IX86_BUILTIN_VFNMADDSH3_MASKZ, UNKNOWN, (int) V8HF_FTYPE_V8HF_V8HF_V8HF_UQI_INT)
> BDESC (0, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512f_vmfmsub_v8hf_mask3_round, "__builtin_ia32_vfmsubsh3_mask3", IX86_BUILTIN_VFMSUBSH3_MASK3, UNKNOWN, (int) V8HF_FTYPE_V8HF_V8HF_V8HF_UQI_INT)
> +BDESC (0, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_fma_fmaddc_v32hf_round, "__builtin_ia32_vfmaddcph_v32hf_round", IX86_BUILTIN_VFMADDCPH_V32HF_ROUND, UNKNOWN, (int) V32HF_FTYPE_V32HF_V32HF_V32HF_INT)
> +BDESC (0, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512bw_fmaddc_v32hf_mask_round, "__builtin_ia32_vfmaddcph_v32hf_mask_round", IX86_BUILTIN_VFMADDCPH_V32HF_MASK_ROUND, UNKNOWN, (int) V32HF_FTYPE_V32HF_V32HF_V32HF_UHI_INT)
> +BDESC (0, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512bw_fmaddc_v32hf_maskz_round, "__builtin_ia32_vfmaddcph_v32hf_maskz_round", IX86_BUILTIN_VFMADDCPH_V32HF_MASKZ_ROUND, UNKNOWN, (int) V32HF_FTYPE_V32HF_V32HF_V32HF_UHI_INT)
> +BDESC (0, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_fma_fcmaddc_v32hf_round, "__builtin_ia32_vfcmaddcph_v32hf_round", IX86_BUILTIN_VFCMADDCPH_V32HF_ROUND, UNKNOWN, (int) V32HF_FTYPE_V32HF_V32HF_V32HF_INT)
> +BDESC (0, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512bw_fcmaddc_v32hf_mask_round, "__builtin_ia32_vfcmaddcph_v32hf_mask_round", IX86_BUILTIN_VFCMADDCPH_V32HF_MASK_ROUND, UNKNOWN, (int) V32HF_FTYPE_V32HF_V32HF_V32HF_UHI_INT)
> +BDESC (0, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512bw_fcmaddc_v32hf_maskz_round, "__builtin_ia32_vfcmaddcph_v32hf_maskz_round", IX86_BUILTIN_VFCMADDCPH_V32HF_MASKZ_ROUND, UNKNOWN, (int) V32HF_FTYPE_V32HF_V32HF_V32HF_UHI_INT)
> +BDESC (0, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512bw_fcmulc_v32hf_round, "__builtin_ia32_vfcmulcph_v32hf_round", IX86_BUILTIN_VFCMULCPH_V32HF_ROUND, UNKNOWN, (int) V32HF_FTYPE_V32HF_V32HF_INT)
> +BDESC (0, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512bw_fcmulc_v32hf_mask_round, "__builtin_ia32_vfcmulcph_v32hf_mask_round", IX86_BUILTIN_VFCMULCPH_V32HF_MASK_ROUND, UNKNOWN, (int) V32HF_FTYPE_V32HF_V32HF_V32HF_UHI_INT)
> +BDESC (0, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512bw_fmulc_v32hf_round, "__builtin_ia32_vfmulcph_v32hf_round", IX86_BUILTIN_VFMULCPH_V32HF_ROUND, UNKNOWN, (int) V32HF_FTYPE_V32HF_V32HF_INT)
> +BDESC (0, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512bw_fmulc_v32hf_mask_round, "__builtin_ia32_vfmulcph_v32hf_mask_round", IX86_BUILTIN_VFMULCPH_V32HF_MASK_ROUND, UNKNOWN, (int) V32HF_FTYPE_V32HF_V32HF_V32HF_UHI_INT)
>
> BDESC_END (ROUND_ARGS, MULTI_ARG)
>
> diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c
> index f6de05c769a..f6d74549dc2 100644
> --- a/gcc/config/i386/i386-expand.c
> +++ b/gcc/config/i386/i386-expand.c
> @@ -9582,6 +9582,7 @@ ix86_expand_args_builtin (const struct builtin_description *d,
> case V2DI_FTYPE_V8HF_V2DI_UQI:
> case V2DI_FTYPE_V4SF_V2DI_UQI:
> case V8HF_FTYPE_V8HF_V8HF_UQI:
> + case V8HF_FTYPE_V8HF_V8HF_V8HF:
> case V8HF_FTYPE_V8HI_V8HF_UQI:
> case V8HF_FTYPE_V8SI_V8HF_UQI:
> case V8HF_FTYPE_V8SF_V8HF_UQI:
> @@ -9660,6 +9661,7 @@ ix86_expand_args_builtin (const struct builtin_description *d,
> case V16SF_FTYPE_V8SF_V16SF_UHI:
> case V16SI_FTYPE_V8SI_V16SI_UHI:
> case V16HF_FTYPE_V16HI_V16HF_UHI:
> + case V16HF_FTYPE_V16HF_V16HF_V16HF:
> case V16HI_FTYPE_V16HF_V16HI_UHI:
> case V16HI_FTYPE_V16HI_V16HI_UHI:
> case V8HI_FTYPE_V16QI_V8HI_UQI:
> @@ -9816,6 +9818,7 @@ ix86_expand_args_builtin (const struct builtin_description *d,
> case V8HI_FTYPE_V8HI_V8HI_V8HI_UQI:
> case V8SI_FTYPE_V8SI_V8SI_V8SI_UQI:
> case V4SI_FTYPE_V4SI_V4SI_V4SI_UQI:
> + case V16HF_FTYPE_V16HF_V16HF_V16HF_UQI:
> case V16HF_FTYPE_V16HF_V16HF_V16HF_UHI:
> case V8SF_FTYPE_V8SF_V8SF_V8SF_UQI:
> case V16QI_FTYPE_V16QI_V16QI_V16QI_UHI:
> @@ -10545,6 +10548,7 @@ ix86_expand_round_builtin (const struct builtin_description *d,
> case V16SF_FTYPE_V16HF_V16SF_UHI_INT:
> case V32HF_FTYPE_V32HI_V32HF_USI_INT:
> case V32HF_FTYPE_V32HF_V32HF_USI_INT:
> + case V32HF_FTYPE_V32HF_V32HF_V32HF_INT:
> case V16SF_FTYPE_V16SF_V16SF_HI_INT:
> case V8DI_FTYPE_V8SF_V8DI_QI_INT:
> case V16SF_FTYPE_V16SI_V16SF_HI_INT:
> @@ -10574,6 +10578,7 @@ ix86_expand_round_builtin (const struct builtin_description *d,
> case V4SF_FTYPE_V4SF_V4SF_V4SF_UQI_INT:
> case V4SF_FTYPE_V8HF_V4SF_V4SF_UQI_INT:
> case V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT:
> + case V32HF_FTYPE_V32HF_V32HF_V32HF_UHI_INT:
> case V32HF_FTYPE_V32HF_V32HF_V32HF_USI_INT:
> case V2DF_FTYPE_V8HF_V2DF_V2DF_UQI_INT:
> case V2DF_FTYPE_V2DF_V2DF_V2DF_QI_INT:
> diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
> index 31f8fc68c65..ddd93f739e3 100644
> --- a/gcc/config/i386/sse.md
> +++ b/gcc/config/i386/sse.md
> @@ -194,6 +194,14 @@ (define_c_enum "unspec" [
> UNSPEC_VCVTNE2PS2BF16
> UNSPEC_VCVTNEPS2BF16
> UNSPEC_VDPBF16PS
> +
> + ;; For AVX512FP16 suppport
> + UNSPEC_COMPLEX_FMA
> + UNSPEC_COMPLEX_FCMA
> + UNSPEC_COMPLEX_FMUL
> + UNSPEC_COMPLEX_FCMUL
> + UNSPEC_COMPLEX_MASK
> +
> ])
>
> (define_c_enum "unspecv" [
> @@ -909,6 +917,10 @@ (define_mode_attr avx512fmaskmode
> (V16SF "HI") (V8SF "QI") (V4SF "QI")
> (V8DF "QI") (V4DF "QI") (V2DF "QI")])
>
> +;; Mapping of vector modes to corresponding complex mask size
> +(define_mode_attr avx512fmaskcmode
> + [(V32HF "HI") (V16HF "QI") (V8HF "QI")])
> +
> ;; Mapping of vector modes to corresponding mask size
> (define_mode_attr avx512fmaskmodelower
> [(V64QI "di") (V32QI "si") (V16QI "hi")
> @@ -5499,6 +5511,92 @@ (define_insn "*fma4i_vmfnmsub_<mode>"
> [(set_attr "type" "ssemuladd")
> (set_attr "mode" "<MODE>")])
>
> +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
> +;;
> +;; Complex type operations
> +;;
> +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
> +
> +(define_int_iterator UNSPEC_COMPLEX_F_C_MA
> + [UNSPEC_COMPLEX_FMA UNSPEC_COMPLEX_FCMA])
> +
> +(define_int_iterator UNSPEC_COMPLEX_F_C_MUL
> + [UNSPEC_COMPLEX_FMUL UNSPEC_COMPLEX_FCMUL])
> +
> +(define_int_attr complexopname
> + [(UNSPEC_COMPLEX_FMA "fmaddc")
> + (UNSPEC_COMPLEX_FCMA "fcmaddc")
> + (UNSPEC_COMPLEX_FMUL "fmulc")
> + (UNSPEC_COMPLEX_FCMUL "fcmulc")])
> +
> +(define_expand "<avx512>_fmaddc_<mode>_maskz<round_expand_name>"
> + [(match_operand:VF_AVX512FP16VL 0 "register_operand")
> + (match_operand:VF_AVX512FP16VL 1 "<round_expand_nimm_predicate>")
> + (match_operand:VF_AVX512FP16VL 2 "<round_expand_nimm_predicate>")
> + (match_operand:VF_AVX512FP16VL 3 "<round_expand_nimm_predicate>")
> + (match_operand:<avx512fmaskcmode> 4 "register_operand")]
> + "TARGET_AVX512FP16 && <round_mode512bit_condition>"
> +{
> + emit_insn (gen_fma_fmaddc_<mode>_maskz_1<round_expand_name> (
> + operands[0], operands[1], operands[2], operands[3],
> + CONST0_RTX (<MODE>mode), operands[4]<round_expand_operand>));
> + DONE;
> +})
> +
> +(define_expand "<avx512>_fcmaddc_<mode>_maskz<round_expand_name>"
> + [(match_operand:VF_AVX512FP16VL 0 "register_operand")
> + (match_operand:VF_AVX512FP16VL 1 "<round_expand_nimm_predicate>")
> + (match_operand:VF_AVX512FP16VL 2 "<round_expand_nimm_predicate>")
> + (match_operand:VF_AVX512FP16VL 3 "<round_expand_nimm_predicate>")
> + (match_operand:<avx512fmaskcmode> 4 "register_operand")]
> + "TARGET_AVX512FP16 && <round_mode512bit_condition>"
> +{
> + emit_insn (gen_fma_fcmaddc_<mode>_maskz_1<round_expand_name> (
> + operands[0], operands[1], operands[2], operands[3],
> + CONST0_RTX (<MODE>mode), operands[4]<round_expand_operand>));
> + DONE;
> +})
> +
> +(define_insn "fma_<complexopname>_<mode><sdc_maskz_name><round_name>"
> + [(set (match_operand:VF_AVX512FP16VL 0 "register_operand" "=v")
> + (unspec:VF_AVX512FP16VL
> + [(match_operand:VF_AVX512FP16VL 1 "<round_nimm_predicate>" "0")
> + (match_operand:VF_AVX512FP16VL 2 "<round_nimm_predicate>" "%v")
> + (match_operand:VF_AVX512FP16VL 3 "<round_nimm_predicate>" "<round_constraint>")]
> + UNSPEC_COMPLEX_F_C_MA))]
> + "TARGET_AVX512FP16 && <sdc_mask_mode512bit_condition> && <round_mode512bit_condition>"
> + "v<complexopname><ssemodesuffix>\t{<round_sdc_mask_op4>%3, %2, %0<sdc_mask_op4>|%0<sdc_mask_op4>, %2, %3<round_sdc_mask_op4>}"
> + [(set_attr "type" "ssemuladd")
> + (set_attr "mode" "<MODE>")])
> +
> +(define_insn "<avx512>_<complexopname>_<mode>_mask<round_name>"
> + [(set (match_operand:VF_AVX512FP16VL 0 "register_operand" "=v")
> + (vec_merge:VF_AVX512FP16VL
> + (unspec:VF_AVX512FP16VL
> + [(match_operand:VF_AVX512FP16VL 1 "register_operand" "0")
> + (match_operand:VF_AVX512FP16VL 2 "nonimmediate_operand" "%v")
> + (match_operand:VF_AVX512FP16VL 3 "nonimmediate_operand" "<round_constraint>")]
> + UNSPEC_COMPLEX_F_C_MA)
> + (match_dup 1)
> + (unspec:<avx512fmaskmode>
> + [(match_operand:<avx512fmaskcmode> 4 "register_operand" "Yk")]
> + UNSPEC_COMPLEX_MASK)))]
> + "TARGET_AVX512FP16 && <round_mode512bit_condition>"
> + "v<complexopname><ssemodesuffix>\t{<round_op5>%3, %2, %0%{%4%}|%0%{%4%}, %2, %3<round_op5>}"
> + [(set_attr "type" "ssemuladd")
> + (set_attr "mode" "<MODE>")])
> +
> +(define_insn "<avx512>_<complexopname>_<mode><maskc_name><round_name>"
> + [(set (match_operand:VF_AVX512FP16VL 0 "register_operand" "=v")
> + (unspec:VF_AVX512FP16VL
> + [(match_operand:VF_AVX512FP16VL 1 "nonimmediate_operand" "%v")
> + (match_operand:VF_AVX512FP16VL 2 "nonimmediate_operand" "<round_constraint>")]
> + UNSPEC_COMPLEX_F_C_MUL))]
> + "TARGET_AVX512FP16 && <round_mode512bit_condition>"
> + "v<complexopname><ssemodesuffix>\t{<round_maskc_op3>%2, %1, %0<maskc_operand3>|%0<maskc_operand3>, %1, %2<round_maskc_op3>}"
> + [(set_attr "type" "ssemul")
> + (set_attr "mode" "<MODE>")])
> +
> ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
> ;;
> ;; Parallel half-precision floating point conversion operations
> diff --git a/gcc/config/i386/subst.md b/gcc/config/i386/subst.md
> index 2e9c2b38e25..3a1f554e9b9 100644
> --- a/gcc/config/i386/subst.md
> +++ b/gcc/config/i386/subst.md
> @@ -28,6 +28,9 @@ (define_mode_iterator SUBST_V
> V16SF V8SF V4SF
> V8DF V4DF V2DF])
>
> +(define_mode_iterator SUBST_CV
> + [V32HF V16HF V8HF])
> +
> (define_mode_iterator SUBST_S
> [QI HI SI DI])
>
> @@ -42,9 +45,11 @@ (define_mode_iterator SUBST_A
> QI HI SI DI SF DF])
>
> (define_subst_attr "mask_name" "mask" "" "_mask")
> +(define_subst_attr "maskc_name" "maskc" "" "_mask")
> (define_subst_attr "mask_applied" "mask" "false" "true")
> (define_subst_attr "mask_operand2" "mask" "" "%{%3%}%N2")
> (define_subst_attr "mask_operand3" "mask" "" "%{%4%}%N3")
> +(define_subst_attr "maskc_operand3" "maskc" "" "%{%4%}%N3")
> (define_subst_attr "mask_operand3_1" "mask" "" "%%{%%4%%}%%N3") ;; for sprintf
> (define_subst_attr "mask_operand4" "mask" "" "%{%5%}%N4")
> (define_subst_attr "mask_operand6" "mask" "" "%{%7%}%N6")
> @@ -89,6 +94,18 @@ (define_subst "merge_mask"
> (match_dup 0)
> (match_operand:<avx512fmaskmode> 2 "register_operand" "Yk")))])
>
> +(define_subst "maskc"
> + [(set (match_operand:SUBST_CV 0)
> + (match_operand:SUBST_CV 1))]
> + "TARGET_AVX512F"
> + [(set (match_dup 0)
> + (vec_merge:SUBST_CV
> + (match_dup 1)
> + (match_operand:SUBST_CV 2 "nonimm_or_0_operand" "0C")
> + (unspec:<avx512fmaskmode>
> + [(match_operand:<avx512fmaskcmode> 3 "register_operand" "Yk")]
> + UNSPEC_COMPLEX_MASK)))])
> +
> (define_subst_attr "mask_scalar_merge_name" "mask_scalar_merge" "" "_mask")
> (define_subst_attr "mask_scalar_merge_operand3" "mask_scalar_merge" "" "%{%3%}")
> (define_subst_attr "mask_scalar_merge_operand4" "mask_scalar_merge" "" "%{%4%}")
> @@ -119,11 +136,31 @@ (define_subst "sd"
> (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk")))
> ])
>
> +(define_subst_attr "sdc_maskz_name" "sdc" "" "_maskz_1")
> +(define_subst_attr "sdc_mask_op4" "sdc" "" "%{%5%}%N4")
> +(define_subst_attr "sdc_mask_op5" "sdc" "" "%{%6%}%N5")
> +(define_subst_attr "sdc_mask_mode512bit_condition" "sdc" "1" "(<MODE_SIZE> == 64 || TARGET_AVX512VL)")
> +
> +(define_subst "sdc"
> + [(set (match_operand:SUBST_CV 0)
> + (match_operand:SUBST_CV 1))]
> + ""
> + [(set (match_dup 0)
> + (vec_merge:SUBST_CV
> + (match_dup 1)
> + (match_operand:SUBST_CV 2 "const0_operand" "C")
> + (unspec:<avx512fmaskmode>
> + [(match_operand:<avx512fmaskcmode> 3 "register_operand" "Yk")]
> + UNSPEC_COMPLEX_MASK)))
> +])
> +
> (define_subst_attr "round_name" "round" "" "_round")
> (define_subst_attr "round_mask_operand2" "mask" "%R2" "%R4")
> (define_subst_attr "round_mask_operand3" "mask" "%R3" "%R5")
> +(define_subst_attr "round_maskc_operand3" "maskc" "%R3" "%R5")
> (define_subst_attr "round_mask_operand4" "mask" "%R4" "%R6")
> (define_subst_attr "round_sd_mask_operand4" "sd" "%R4" "%R6")
> +(define_subst_attr "round_sdc_mask_operand4" "sdc" "%R4" "%R6")
> (define_subst_attr "round_op2" "round" "" "%R2")
> (define_subst_attr "round_op3" "round" "" "%R3")
> (define_subst_attr "round_op4" "round" "" "%R4")
> @@ -131,8 +168,10 @@ (define_subst_attr "round_op5" "round" "" "%R5")
> (define_subst_attr "round_op6" "round" "" "%R6")
> (define_subst_attr "round_mask_op2" "round" "" "<round_mask_operand2>")
> (define_subst_attr "round_mask_op3" "round" "" "<round_mask_operand3>")
> +(define_subst_attr "round_maskc_op3" "round" "" "<round_maskc_operand3>")
> (define_subst_attr "round_mask_op4" "round" "" "<round_mask_operand4>")
> (define_subst_attr "round_sd_mask_op4" "round" "" "<round_sd_mask_operand4>")
> +(define_subst_attr "round_sdc_mask_op4" "round" "" "<round_sdc_mask_operand4>")
> (define_subst_attr "round_constraint" "round" "vm" "v")
> (define_subst_attr "round_qq2phsuff" "round" "<qq2phsuff>" "")
> (define_subst_attr "bcst_round_constraint" "round" "vmBr" "v")
> @@ -169,6 +208,7 @@ (define_subst_attr "round_saeonly_mask_operand3" "mask" "%r3" "%r5")
> (define_subst_attr "round_saeonly_mask_operand4" "mask" "%r4" "%r6")
> (define_subst_attr "round_saeonly_mask_scalar_merge_operand4" "mask_scalar_merge" "%r4" "%r5")
> (define_subst_attr "round_saeonly_sd_mask_operand5" "sd" "%r5" "%r7")
> +(define_subst_attr "round_saeonly_sdc_mask_operand5" "sdc" "%r5" "%r7")
> (define_subst_attr "round_saeonly_op2" "round_saeonly" "" "%r2")
> (define_subst_attr "round_saeonly_op3" "round_saeonly" "" "%r3")
> (define_subst_attr "round_saeonly_op4" "round_saeonly" "" "%r4")
> diff --git a/gcc/testsuite/gcc.target/i386/avx-1.c b/gcc/testsuite/gcc.target/i386/avx-1.c
> index 6c2d1dc3df4..56e90d9f9a5 100644
> --- a/gcc/testsuite/gcc.target/i386/avx-1.c
> +++ b/gcc/testsuite/gcc.target/i386/avx-1.c
> @@ -787,6 +787,16 @@
> #define __builtin_ia32_vfnmsubsh3_mask(A, B, C, D, E) __builtin_ia32_vfnmsubsh3_mask(A, B, C, D, 8)
> #define __builtin_ia32_vfnmsubsh3_mask3(A, B, C, D, E) __builtin_ia32_vfnmsubsh3_mask3(A, B, C, D, 8)
> #define __builtin_ia32_vfnmsubsh3_maskz(A, B, C, D, E) __builtin_ia32_vfnmsubsh3_maskz(A, B, C, D, 8)
> +#define __builtin_ia32_vfcmaddcph_v32hf_round(A, B, C, D) __builtin_ia32_vfcmaddcph_v32hf_round(A, B, C, 8)
> +#define __builtin_ia32_vfcmaddcph_v32hf_mask_round(A, C, D, B, E) __builtin_ia32_vfcmaddcph_v32hf_mask_round(A, C, D, B, 8)
> +#define __builtin_ia32_vfcmaddcph_v32hf_maskz_round(B, C, D, A, E) __builtin_ia32_vfcmaddcph_v32hf_maskz_round(B, C, D, A, 8)
> +#define __builtin_ia32_vfmaddcph_v32hf_round(A, B, C, D) __builtin_ia32_vfmaddcph_v32hf_round(A, B, C, 8)
> +#define __builtin_ia32_vfmaddcph_v32hf_mask_round(A, C, D, B, E) __builtin_ia32_vfmaddcph_v32hf_mask_round(A, C, D, B, 8)
> +#define __builtin_ia32_vfmaddcph_v32hf_maskz_round(B, C, D, A, E) __builtin_ia32_vfmaddcph_v32hf_maskz_round(B, C, D, A, 8)
> +#define __builtin_ia32_vfmulcph_v32hf_round(A, B, C) __builtin_ia32_vfmulcph_v32hf_round(A, B, 8)
> +#define __builtin_ia32_vfmulcph_v32hf_mask_round(A, C, D, B, E) __builtin_ia32_vfmulcph_v32hf_mask_round(A, C, D, B, 8)
> +#define __builtin_ia32_vfcmulcph_v32hf_round(A, B, C) __builtin_ia32_vfcmulcph_v32hf_round(A, B, 8)
> +#define __builtin_ia32_vfcmulcph_v32hf_mask_round(A, C, D, B, E) __builtin_ia32_vfcmulcph_v32hf_mask_round(A, C, D, B, 8)
>
> /* avx512fp16vlintrin.h */
> #define __builtin_ia32_vcmpph_v8hf_mask(A, B, C, D) __builtin_ia32_vcmpph_v8hf_mask(A, B, 1, D)
> diff --git a/gcc/testsuite/gcc.target/i386/sse-13.c b/gcc/testsuite/gcc.target/i386/sse-13.c
> index f16be008909..ef9f8aad853 100644
> --- a/gcc/testsuite/gcc.target/i386/sse-13.c
> +++ b/gcc/testsuite/gcc.target/i386/sse-13.c
> @@ -804,6 +804,16 @@
> #define __builtin_ia32_vfnmsubsh3_mask(A, B, C, D, E) __builtin_ia32_vfnmsubsh3_mask(A, B, C, D, 8)
> #define __builtin_ia32_vfnmsubsh3_mask3(A, B, C, D, E) __builtin_ia32_vfnmsubsh3_mask3(A, B, C, D, 8)
> #define __builtin_ia32_vfnmsubsh3_maskz(A, B, C, D, E) __builtin_ia32_vfnmsubsh3_maskz(A, B, C, D, 8)
> +#define __builtin_ia32_vfcmaddcph_v32hf_round(A, B, C, D) __builtin_ia32_vfcmaddcph_v32hf_round(A, B, C, 8)
> +#define __builtin_ia32_vfcmaddcph_v32hf_mask_round(A, C, D, B, E) __builtin_ia32_vfcmaddcph_v32hf_mask_round(A, C, D, B, 8)
> +#define __builtin_ia32_vfcmaddcph_v32hf_maskz_round(B, C, D, A, E) __builtin_ia32_vfcmaddcph_v32hf_maskz_round(B, C, D, A, 8)
> +#define __builtin_ia32_vfmaddcph_v32hf_round(A, B, C, D) __builtin_ia32_vfmaddcph_v32hf_round(A, B, C, 8)
> +#define __builtin_ia32_vfmaddcph_v32hf_mask_round(A, C, D, B, E) __builtin_ia32_vfmaddcph_v32hf_mask_round(A, C, D, B, 8)
> +#define __builtin_ia32_vfmaddcph_v32hf_maskz_round(B, C, D, A, E) __builtin_ia32_vfmaddcph_v32hf_maskz_round(B, C, D, A, 8)
> +#define __builtin_ia32_vfmulcph_v32hf_round(A, B, C) __builtin_ia32_vfmulcph_v32hf_round(A, B, 8)
> +#define __builtin_ia32_vfmulcph_v32hf_mask_round(A, C, D, B, E) __builtin_ia32_vfmulcph_v32hf_mask_round(A, C, D, B, 8)
> +#define __builtin_ia32_vfcmulcph_v32hf_round(A, B, C) __builtin_ia32_vfcmulcph_v32hf_round(A, B, 8)
> +#define __builtin_ia32_vfcmulcph_v32hf_mask_round(A, C, D, B, E) __builtin_ia32_vfcmulcph_v32hf_mask_round(A, C, D, B, 8)
>
> /* avx512fp16vlintrin.h */
> #define __builtin_ia32_vcmpph_v8hf_mask(A, B, C, D) __builtin_ia32_vcmpph_v8hf_mask(A, B, 1, D)
> diff --git a/gcc/testsuite/gcc.target/i386/sse-14.c b/gcc/testsuite/gcc.target/i386/sse-14.c
> index 01ac4e04173..f27c73fd4cc 100644
> --- a/gcc/testsuite/gcc.target/i386/sse-14.c
> +++ b/gcc/testsuite/gcc.target/i386/sse-14.c
> @@ -772,6 +772,8 @@ test_2 (_mm_cvt_roundss_sh, __m128h, __m128h, __m128, 8)
> test_2 (_mm_cvt_roundsd_sh, __m128h, __m128h, __m128d, 8)
> test_2 (_mm_cvt_roundi32_sh, __m128h, __m128h, int, 8)
> test_2 (_mm_cvt_roundu32_sh, __m128h, __m128h, unsigned, 8)
> +test_2 (_mm512_fmul_round_pch, __m512h, __m512h, __m512h, 8)
> +test_2 (_mm512_fcmul_round_pch, __m512h, __m512h, __m512h, 8)
> test_2x (_mm512_cmp_round_ph_mask, __mmask32, __m512h, __m512h, 1, 8)
> test_2x (_mm_cmp_round_sh_mask, __mmask8, __m128h, __m128h, 1, 8)
> test_2x (_mm_comi_round_sh, int, __m128h, __m128h, 1, 8)
> @@ -846,6 +848,10 @@ test_3 (_mm_fmadd_round_sh, __m128h, __m128h, __m128h, __m128h, 9)
> test_3 (_mm_fnmadd_round_sh, __m128h, __m128h, __m128h, __m128h, 9)
> test_3 (_mm_fmsub_round_sh, __m128h, __m128h, __m128h, __m128h, 9)
> test_3 (_mm_fnmsub_round_sh, __m128h, __m128h, __m128h, __m128h, 9)
> +test_3 (_mm512_fmadd_round_pch, __m512h, __m512h, __m512h, __m512h, 8)
> +test_3 (_mm512_fcmadd_round_pch, __m512h, __m512h, __m512h, __m512h, 8)
> +test_3 (_mm512_maskz_fmul_round_pch, __m512h, __mmask16, __m512h, __m512h, 8)
> +test_3 (_mm512_maskz_fcmul_round_pch, __m512h, __mmask16, __m512h, __m512h, 8)
> test_3x (_mm512_mask_cmp_round_ph_mask, __mmask32, __mmask32, __m512h, __m512h, 1, 8)
> test_3x (_mm_mask_cmp_round_sh_mask, __mmask8, __mmask8, __m128h, __m128h, 1, 8)
> test_3x (_mm512_mask_reduce_round_ph, __m512h, __m512h, __mmask32, __m512h, 123, 8)
> @@ -908,6 +914,14 @@ test_4 (_mm_maskz_fmsub_round_sh, __m128h, __mmask8, __m128h, __m128h, __m128h,
> test_4 (_mm_mask_fnmsub_round_sh, __m128h, __m128h, __mmask8, __m128h, __m128h, 9)
> test_4 (_mm_mask3_fnmsub_round_sh, __m128h, __m128h, __m128h, __m128h, __mmask8, 9)
> test_4 (_mm_maskz_fnmsub_round_sh, __m128h, __mmask8, __m128h, __m128h, __m128h, 9)
> +test_4 (_mm512_mask_fmadd_round_pch, __m512h, __m512h, __mmask16, __m512h, __m512h, 8)
> +test_4 (_mm512_mask_fcmadd_round_pch, __m512h, __m512h, __mmask16, __m512h, __m512h, 8)
> +test_4 (_mm512_mask3_fmadd_round_pch, __m512h, __m512h, __m512h, __m512h, __mmask16, 8)
> +test_4 (_mm512_mask3_fcmadd_round_pch, __m512h, __m512h, __m512h, __m512h, __mmask16, 8)
> +test_4 (_mm512_maskz_fmadd_round_pch, __m512h, __mmask16, __m512h, __m512h, __m512h, 8)
> +test_4 (_mm512_maskz_fcmadd_round_pch, __m512h, __mmask16, __m512h, __m512h, __m512h, 8)
> +test_4 (_mm512_mask_fmul_round_pch, __m512h, __m512h, __mmask16, __m512h, __m512h, 8)
> +test_4 (_mm512_mask_fcmul_round_pch, __m512h, __m512h, __mmask16, __m512h, __m512h, 8)
> test_4x (_mm_mask_reduce_round_sh, __m128h, __m128h, __mmask8, __m128h, __m128h, 123, 8)
> test_4x (_mm_mask_roundscale_round_sh, __m128h, __m128h, __mmask8, __m128h, __m128h, 123, 8)
> test_4x (_mm_mask_getmant_sh, __m128h, __m128h, __mmask8, __m128h, __m128h, 1, 1)
> diff --git a/gcc/testsuite/gcc.target/i386/sse-22.c b/gcc/testsuite/gcc.target/i386/sse-22.c
> index 79e3f35ab86..ccf8c3a6c03 100644
> --- a/gcc/testsuite/gcc.target/i386/sse-22.c
> +++ b/gcc/testsuite/gcc.target/i386/sse-22.c
> @@ -876,6 +876,8 @@ test_2 (_mm_cvt_roundsh_ss, __m128, __m128, __m128h, 8)
> test_2 (_mm_cvt_roundsh_sd, __m128d, __m128d, __m128h, 8)
> test_2 (_mm_cvt_roundss_sh, __m128h, __m128h, __m128, 8)
> test_2 (_mm_cvt_roundsd_sh, __m128h, __m128h, __m128d, 8)
> +test_2 (_mm512_fmul_round_pch, __m512h, __m512h, __m512h, 8)
> +test_2 (_mm512_fcmul_round_pch, __m512h, __m512h, __m512h, 8)
> test_2x (_mm512_cmp_round_ph_mask, __mmask32, __m512h, __m512h, 1, 8)
> test_2x (_mm_cmp_round_sh_mask, __mmask8, __m128h, __m128h, 1, 8)
> test_2x (_mm_comi_round_sh, int, __m128h, __m128h, 1, 8)
> @@ -949,6 +951,10 @@ test_3 (_mm_fmadd_round_sh, __m128h, __m128h, __m128h, __m128h, 9)
> test_3 (_mm_fnmadd_round_sh, __m128h, __m128h, __m128h, __m128h, 9)
> test_3 (_mm_fmsub_round_sh, __m128h, __m128h, __m128h, __m128h, 9)
> test_3 (_mm_fnmsub_round_sh, __m128h, __m128h, __m128h, __m128h, 9)
> +test_3 (_mm512_fmadd_round_pch, __m512h, __m512h, __m512h, __m512h, 8)
> +test_3 (_mm512_fcmadd_round_pch, __m512h, __m512h, __m512h, __m512h, 8)
> +test_3 (_mm512_maskz_fmul_round_pch, __m512h, __mmask16, __m512h, __m512h, 8)
> +test_3 (_mm512_maskz_fcmul_round_pch, __m512h, __mmask16, __m512h, __m512h, 8)
> test_3x (_mm512_mask_cmp_round_ph_mask, __mmask32, __mmask32, __m512h, __m512h, 1, 8)
> test_3x (_mm_mask_cmp_round_sh_mask, __mmask8, __mmask8, __m128h, __m128h, 1, 8)
> test_3x (_mm512_mask_reduce_round_ph, __m512h, __m512h, __mmask32, __m512h, 123, 8)
> @@ -1010,6 +1016,14 @@ test_4 (_mm_maskz_fmsub_round_sh, __m128h, __mmask8, __m128h, __m128h, __m128h,
> test_4 (_mm_mask_fnmsub_round_sh, __m128h, __m128h, __mmask8, __m128h, __m128h, 9)
> test_4 (_mm_mask3_fnmsub_round_sh, __m128h, __m128h, __m128h, __m128h, __mmask8, 9)
> test_4 (_mm_maskz_fnmsub_round_sh, __m128h, __mmask8, __m128h, __m128h, __m128h, 9)
> +test_4 (_mm512_mask_fmadd_round_pch, __m512h, __m512h, __mmask16, __m512h, __m512h, 8)
> +test_4 (_mm512_mask_fcmadd_round_pch, __m512h, __m512h, __mmask16, __m512h, __m512h, 8)
> +test_4 (_mm512_mask3_fmadd_round_pch, __m512h, __m512h, __m512h, __m512h, __mmask16, 8)
> +test_4 (_mm512_mask3_fcmadd_round_pch, __m512h, __m512h, __m512h, __m512h, __mmask16, 8)
> +test_4 (_mm512_maskz_fmadd_round_pch, __m512h, __mmask16, __m512h, __m512h, __m512h, 8)
> +test_4 (_mm512_maskz_fcmadd_round_pch, __m512h, __mmask16, __m512h, __m512h, __m512h, 8)
> +test_4 (_mm512_mask_fmul_round_pch, __m512h, __m512h, __mmask16, __m512h, __m512h, 8)
> +test_4 (_mm512_mask_fcmul_round_pch, __m512h, __m512h, __mmask16, __m512h, __m512h, 8)
> test_4x (_mm_mask_reduce_round_sh, __m128h, __m128h, __mmask8, __m128h, __m128h, 123, 8)
> test_4x (_mm_mask_roundscale_round_sh, __m128h, __m128h, __mmask8, __m128h, __m128h, 123, 8)
> test_4x (_mm_mask_getmant_sh, __m128h, __m128h, __mmask8, __m128h, __m128h, 1, 1)
> diff --git a/gcc/testsuite/gcc.target/i386/sse-23.c b/gcc/testsuite/gcc.target/i386/sse-23.c
> index caf14408b91..dc39d7e2012 100644
> --- a/gcc/testsuite/gcc.target/i386/sse-23.c
> +++ b/gcc/testsuite/gcc.target/i386/sse-23.c
> @@ -805,6 +805,16 @@
> #define __builtin_ia32_vfnmsubsh3_mask(A, B, C, D, E) __builtin_ia32_vfnmsubsh3_mask(A, B, C, D, 8)
> #define __builtin_ia32_vfnmsubsh3_mask3(A, B, C, D, E) __builtin_ia32_vfnmsubsh3_mask3(A, B, C, D, 8)
> #define __builtin_ia32_vfnmsubsh3_maskz(A, B, C, D, E) __builtin_ia32_vfnmsubsh3_maskz(A, B, C, D, 8)
> +#define __builtin_ia32_vfcmaddcph_v32hf_round(A, B, C, D) __builtin_ia32_vfcmaddcph_v32hf_round(A, B, C, 8)
> +#define __builtin_ia32_vfcmaddcph_v32hf_mask_round(A, C, D, B, E) __builtin_ia32_vfcmaddcph_v32hf_mask_round(A, C, D, B, 8)
> +#define __builtin_ia32_vfcmaddcph_v32hf_maskz_round(B, C, D, A, E) __builtin_ia32_vfcmaddcph_v32hf_maskz_round(B, C, D, A, 8)
> +#define __builtin_ia32_vfmaddcph_v32hf_round(A, B, C, D) __builtin_ia32_vfmaddcph_v32hf_round(A, B, C, 8)
> +#define __builtin_ia32_vfmaddcph_v32hf_mask_round(A, C, D, B, E) __builtin_ia32_vfmaddcph_v32hf_mask_round(A, C, D, B, 8)
> +#define __builtin_ia32_vfmaddcph_v32hf_maskz_round(B, C, D, A, E) __builtin_ia32_vfmaddcph_v32hf_maskz_round(B, C, D, A, 8)
> +#define __builtin_ia32_vfmulcph_v32hf_round(A, B, C) __builtin_ia32_vfmulcph_v32hf_round(A, B, 8)
> +#define __builtin_ia32_vfmulcph_v32hf_mask_round(A, C, D, B, E) __builtin_ia32_vfmulcph_v32hf_mask_round(A, C, D, B, 8)
> +#define __builtin_ia32_vfcmulcph_v32hf_round(A, B, C) __builtin_ia32_vfcmulcph_v32hf_round(A, B, 8)
> +#define __builtin_ia32_vfcmulcph_v32hf_mask_round(A, C, D, B, E) __builtin_ia32_vfcmulcph_v32hf_mask_round(A, C, D, B, 8)
>
> /* avx512fp16vlintrin.h */
> #define __builtin_ia32_vcmpph_v8hf_mask(A, B, C, D) __builtin_ia32_vcmpph_v8hf_mask(A, B, 1, D)
> --
> 2.18.1
>
diff --git a/gcc/config/i386/avx512fp16intrin.h b/gcc/config/i386/avx512fp16intrin.h index 5c85ec15b22..9dd71019972 100644 --- a/gcc/config/i386/avx512fp16intrin.h +++ b/gcc/config/i386/avx512fp16intrin.h @@ -6109,6 +6109,392 @@ _mm_maskz_fnmsub_round_sh (__mmask8 __U, __m128h __W, __m128h __A, #endif /* __OPTIMIZE__ */ +/* Intrinsics vf[,c]maddcph. */ +extern __inline __m512h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_fcmadd_pch (__m512h __A, __m512h __B, __m512h __C) +{ + return (__m512h) + __builtin_ia32_vfcmaddcph_v32hf_round ((__v32hf) __C, + (__v32hf) __A, + (__v32hf) __B, + _MM_FROUND_CUR_DIRECTION); +} + +extern __inline __m512h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_mask_fcmadd_pch (__m512h __A, __mmask16 __B, __m512h __C, __m512h __D) +{ + return (__m512h) __builtin_ia32_movaps512_mask + ((__v16sf) + __builtin_ia32_vfcmaddcph_v32hf_mask_round ((__v32hf) __D, + (__v32hf) __A, + (__v32hf) __C, __B, + _MM_FROUND_CUR_DIRECTION), + (__v16sf) __A, __B); +} + +extern __inline __m512h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_mask3_fcmadd_pch (__m512h __A, __m512h __B, __m512h __C, __mmask16 __D) +{ + return (__m512h) + __builtin_ia32_vfcmaddcph_v32hf_mask_round ((__v32hf) __C, + (__v32hf) __A, + (__v32hf) __B, + __D, _MM_FROUND_CUR_DIRECTION); +} + +extern __inline __m512h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_maskz_fcmadd_pch (__mmask16 __A, __m512h __B, __m512h __C, __m512h __D) +{ + return (__m512h) + __builtin_ia32_vfcmaddcph_v32hf_maskz_round((__v32hf) __D, + (__v32hf) __B, + (__v32hf) __C, + __A, _MM_FROUND_CUR_DIRECTION); +} + +extern __inline __m512h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_fmadd_pch (__m512h __A, __m512h __B, __m512h __C) +{ + return (__m512h) + __builtin_ia32_vfmaddcph_v32hf_round((__v32hf) __C, + (__v32hf) __A, + (__v32hf) __B, + _MM_FROUND_CUR_DIRECTION); +} + +extern __inline __m512h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_mask_fmadd_pch (__m512h __A, __mmask16 __B, __m512h __C, __m512h __D) +{ + return (__m512h) __builtin_ia32_movaps512_mask + ((__v16sf) + __builtin_ia32_vfmaddcph_v32hf_mask_round ((__v32hf) __D, + (__v32hf) __A, + (__v32hf) __C, __B, + _MM_FROUND_CUR_DIRECTION), + (__v16sf) __A, __B); +} + +extern __inline __m512h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_mask3_fmadd_pch (__m512h __A, __m512h __B, __m512h __C, __mmask16 __D) +{ + return (__m512h) + __builtin_ia32_vfmaddcph_v32hf_mask_round((__v32hf) __C, + (__v32hf) __A, + (__v32hf) __B, + __D, _MM_FROUND_CUR_DIRECTION); +} + +extern __inline __m512h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_maskz_fmadd_pch (__mmask16 __A, __m512h __B, __m512h __C, __m512h __D) +{ + return (__m512h) + __builtin_ia32_vfmaddcph_v32hf_maskz_round((__v32hf) __D, + (__v32hf) __B, + (__v32hf) __C, + __A, _MM_FROUND_CUR_DIRECTION); +} + +#ifdef __OPTIMIZE__ +extern __inline __m512h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_fcmadd_round_pch (__m512h __A, __m512h __B, __m512h __C, const int __D) +{ + return (__m512h)__builtin_ia32_vfcmaddcph_v32hf_round((__v32hf) __C, + (__v32hf) __A, + (__v32hf) __B, + __D); +} + +extern __inline __m512h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_mask_fcmadd_round_pch (__m512h __A, __mmask16 __B, __m512h __C, + __m512h __D, const int __E) +{ + return (__m512h) __builtin_ia32_movaps512_mask + ((__v16sf) + __builtin_ia32_vfcmaddcph_v32hf_mask_round ((__v32hf) __D, + (__v32hf) __A, + (__v32hf) __C, __B, + __E), + (__v16sf) __A, __B); +} + +extern __inline __m512h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_mask3_fcmadd_round_pch (__m512h __A, __m512h __B, __m512h __C, + __mmask16 __D, const int __E) +{ + return (__m512h) + __builtin_ia32_vfcmaddcph_v32hf_mask_round ((__v32hf) __C, + (__v32hf) __A, + (__v32hf) __B, + __D, __E); +} + +extern __inline __m512h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_maskz_fcmadd_round_pch (__mmask16 __A, __m512h __B, __m512h __C, + __m512h __D, const int __E) +{ + return (__m512h)__builtin_ia32_vfcmaddcph_v32hf_maskz_round((__v32hf) __D, + (__v32hf) __B, + (__v32hf) __C, + __A, + __E); +} + +extern __inline __m512h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_fmadd_round_pch (__m512h __A, __m512h __B, __m512h __C, const int __D) +{ + return (__m512h) + __builtin_ia32_vfmaddcph_v32hf_round ((__v32hf) __C, + (__v32hf) __A, + (__v32hf) __B, + __D); +} + +extern __inline __m512h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_mask_fmadd_round_pch (__m512h __A, __mmask16 __B, __m512h __C, + __m512h __D, const int __E) +{ + return (__m512h) __builtin_ia32_movaps512_mask + ((__v16sf) + __builtin_ia32_vfmaddcph_v32hf_mask_round ((__v32hf) __D, + (__v32hf) __A, + (__v32hf) __C, __B, + __E), + (__v16sf) __A, __B); +} + +extern __inline __m512h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_mask3_fmadd_round_pch (__m512h __A, __m512h __B, __m512h __C, + __mmask16 __D, const int __E) +{ + return (__m512h) + __builtin_ia32_vfmaddcph_v32hf_mask_round ((__v32hf) __C, + (__v32hf) __A, + (__v32hf) __B, + __D, __E); +} + +extern __inline __m512h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_maskz_fmadd_round_pch (__mmask16 __A, __m512h __B, __m512h __C, + __m512h __D, const int __E) +{ + return (__m512h)__builtin_ia32_vfmaddcph_v32hf_maskz_round((__v32hf) __D, + (__v32hf) __B, + (__v32hf) __C, + __A, __E); +} + +#else +#define _mm512_fcmadd_round_pch(A, B, C, D) \ + (__m512h) __builtin_ia32_vfcmaddcph_v32hf_round ((C), (A), (B), (D)) + +#define _mm512_mask_fcmadd_round_pch(A, B, C, D, E) \ + ((__m512h) __builtin_ia32_movaps512_mask ( \ + (__v16sf) \ + __builtin_ia32_vfcmaddcph_v32hf_mask_round ((__v32hf) (D), \ + (__v32hf) (A), \ + (__v32hf) (C), \ + (B), (E)), \ + (__v16sf) (A), (B))); + + +#define _mm512_mask3_fcmadd_round_pch(A, B, C, D, E) \ + ((__m512h) \ + __builtin_ia32_vfcmaddcph_v32hf_mask_round ((C), (A), (B), (D), (E))) + +#define _mm512_maskz_fcmadd_round_pch(A, B, C, D, E) \ + (__m512h) \ + __builtin_ia32_vfcmaddcph_v32hf_maskz_round((D), (B), (C), (A), (E)) + +#define _mm512_fmadd_round_pch(A, B, C, D) \ + (__m512h) __builtin_ia32_vfmaddcph_v32hf_round((C), (A), (B), (D)) + +#define _mm512_mask_fmadd_round_pch(A, B, C, D, E) \ + ((__m512h) __builtin_ia32_movaps512_mask ( \ + (__v16sf) \ + __builtin_ia32_vfmaddcph_v32hf_mask_round ((__v32hf) (D), \ + (__v32hf) (A), \ + (__v32hf) (C), \ + (B), (E)), \ + (__v16sf) (A), (B))); + +#define _mm512_mask3_fmadd_round_pch(A, B, C, D, E) \ + (__m512h) \ + __builtin_ia32_vfmaddcph_v32hf_mask_round((C), (A), (B), (D), (E)) + +#define _mm512_maskz_fmadd_round_pch(A, B, C, D, E) \ + (__m512h) \ + __builtin_ia32_vfmaddcph_v32hf_maskz_round((D), (B), (C), (A), (E)) + +#endif /* __OPTIMIZE__ */ + +/* Intrinsics vf[,c]mulcph. */ +extern __inline __m512h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_fcmul_pch (__m512h __A, __m512h __B) +{ + return (__m512h) + __builtin_ia32_vfcmulcph_v32hf_round((__v32hf) __A, + (__v32hf) __B, + _MM_FROUND_CUR_DIRECTION); +} + +extern __inline __m512h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_mask_fcmul_pch (__m512h __A, __mmask16 __B, __m512h __C, __m512h __D) +{ + return (__m512h) + __builtin_ia32_vfcmulcph_v32hf_mask_round((__v32hf) __C, + (__v32hf) __D, + (__v32hf) __A, + __B, _MM_FROUND_CUR_DIRECTION); +} + +extern __inline __m512h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_maskz_fcmul_pch (__mmask16 __A, __m512h __B, __m512h __C) +{ + return (__m512h) + __builtin_ia32_vfcmulcph_v32hf_mask_round((__v32hf) __B, + (__v32hf) __C, + _mm512_setzero_ph (), + __A, _MM_FROUND_CUR_DIRECTION); +} + +extern __inline __m512h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_fmul_pch (__m512h __A, __m512h __B) +{ + return (__m512h) + __builtin_ia32_vfmulcph_v32hf_round((__v32hf) __A, + (__v32hf) __B, + _MM_FROUND_CUR_DIRECTION); +} + +extern __inline __m512h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_mask_fmul_pch (__m512h __A, __mmask16 __B, __m512h __C, __m512h __D) +{ + return (__m512h) + __builtin_ia32_vfmulcph_v32hf_mask_round((__v32hf) __C, + (__v32hf) __D, + (__v32hf) __A, + __B, _MM_FROUND_CUR_DIRECTION); +} + +extern __inline __m512h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_maskz_fmul_pch (__mmask16 __A, __m512h __B, __m512h __C) +{ + return (__m512h) + __builtin_ia32_vfmulcph_v32hf_mask_round((__v32hf) __B, + (__v32hf) __C, + _mm512_setzero_ph (), + __A, _MM_FROUND_CUR_DIRECTION); +} + +#ifdef __OPTIMIZE__ +extern __inline __m512h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_fcmul_round_pch (__m512h __A, __m512h __B, const int __D) +{ + return (__m512h)__builtin_ia32_vfcmulcph_v32hf_round((__v32hf) __A, + (__v32hf) __B, __D); +} + +extern __inline __m512h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_mask_fcmul_round_pch (__m512h __A, __mmask16 __B, __m512h __C, + __m512h __D, const int __E) +{ + return (__m512h)__builtin_ia32_vfcmulcph_v32hf_mask_round((__v32hf) __C, + (__v32hf) __D, + (__v32hf) __A, + __B, __E); +} + +extern __inline __m512h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_maskz_fcmul_round_pch (__mmask16 __A, __m512h __B, + __m512h __C, const int __E) +{ + return (__m512h)__builtin_ia32_vfcmulcph_v32hf_mask_round((__v32hf) __B, + (__v32hf) __C, + _mm512_setzero_ph (), + __A, __E); +} + +extern __inline __m512h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_fmul_round_pch (__m512h __A, __m512h __B, const int __D) +{ + return (__m512h)__builtin_ia32_vfmulcph_v32hf_round((__v32hf) __A, + (__v32hf) __B, + __D); +} + +extern __inline __m512h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_mask_fmul_round_pch (__m512h __A, __mmask16 __B, __m512h __C, + __m512h __D, const int __E) +{ + return (__m512h)__builtin_ia32_vfmulcph_v32hf_mask_round((__v32hf) __C, + (__v32hf) __D, + (__v32hf) __A, + __B, __E); +} + +extern __inline __m512h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_maskz_fmul_round_pch (__mmask16 __A, __m512h __B, + __m512h __C, const int __E) +{ + return (__m512h)__builtin_ia32_vfmulcph_v32hf_mask_round((__v32hf) __B, + (__v32hf) __C, + _mm512_setzero_ph (), + __A, __E); +} + +#else +#define _mm512_fcmul_round_pch(A, B, D) \ + (__m512h)__builtin_ia32_vfcmulcph_v32hf_round(A, B, D) + +#define _mm512_mask_fcmul_round_pch(A, B, C, D, E) \ + (__m512h)__builtin_ia32_vfcmulcph_v32hf_mask_round(C, D, A, B, E) + +#define _mm512_maskz_fcmul_round_pch(A, B, C, E) \ + (__m512h)__builtin_ia32_vfcmulcph_v32hf_mask_round(B, C, \ + _mm512_setzero_ph(), \ + A, E) + +#define _mm512_fmul_round_pch(A, B, D) \ + (__m512h)__builtin_ia32_vfmulcph_v32hf_round(A, B, D) + +#define _mm512_mask_fmul_round_pch(A, B, C, D, E) \ + (__m512h)__builtin_ia32_vfmulcph_v32hf_mask_round(C, D, A, B, E) + +#define _mm512_maskz_fmul_round_pch(A, B, C, E) \ + (__m512h)__builtin_ia32_vfmulcph_v32hf_mask_round(B, C, \ + _mm512_setzero_ph (), \ + A, E) + +#endif /* __OPTIMIZE__ */ + #ifdef __DISABLE_AVX512FP16__ #undef __DISABLE_AVX512FP16__ #pragma GCC pop_options diff --git a/gcc/config/i386/avx512fp16vlintrin.h b/gcc/config/i386/avx512fp16vlintrin.h index bba98f105ac..c7bdfbc0517 100644 --- a/gcc/config/i386/avx512fp16vlintrin.h +++ b/gcc/config/i386/avx512fp16vlintrin.h @@ -2815,6 +2815,263 @@ _mm_maskz_fnmsub_ph (__mmask8 __U, __m128h __A, __m128h __B, __U); } +/* Intrinsics vf[,c]maddcph. */ +extern __inline __m128h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_fmadd_pch (__m128h __A, __m128h __B, __m128h __C) +{ + return (__m128h)__builtin_ia32_vfmaddcph_v8hf((__v8hf) __C, (__v8hf) __A, + (__v8hf) __B); +} + +extern __inline __m128h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_mask_fmadd_pch (__m128h __A, __mmask8 __B, __m128h __C, __m128h __D) +{ + return (__m128h) __builtin_ia32_movaps128_mask + ((__v4sf) + __builtin_ia32_vfmaddcph_v8hf_mask ((__v8hf) __D, + (__v8hf) __A, + (__v8hf) __C, __B), + (__v4sf) __A, __B); +} + +extern __inline __m128h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_mask3_fmadd_pch (__m128h __A, __m128h __B, __m128h __C, __mmask8 __D) +{ + return (__m128h) __builtin_ia32_vfmaddcph_v8hf_mask ((__v8hf) __C, + (__v8hf) __A, + (__v8hf) __B, __D); +} + +extern __inline __m128h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_maskz_fmadd_pch (__mmask8 __A, __m128h __B, __m128h __C, __m128h __D) +{ + return (__m128h)__builtin_ia32_vfmaddcph_v8hf_maskz((__v8hf) __D, + (__v8hf) __B, + (__v8hf) __C, __A); +} + +extern __inline __m256h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_fmadd_pch (__m256h __A, __m256h __B, __m256h __C) +{ + return (__m256h)__builtin_ia32_vfmaddcph_v16hf((__v16hf) __C, (__v16hf) __A, + (__v16hf) __B); +} + +extern __inline __m256h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_mask_fmadd_pch (__m256h __A, __mmask8 __B, __m256h __C, __m256h __D) +{ + return (__m256h) __builtin_ia32_movaps256_mask + ((__v8sf) + __builtin_ia32_vfmaddcph_v16hf_mask ((__v16hf) __D, + (__v16hf) __A, + (__v16hf) __C, __B), + (__v8sf) __A, __B); +} + +extern __inline __m256h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_mask3_fmadd_pch (__m256h __A, __m256h __B, __m256h __C, __mmask8 __D) +{ + return (__m256h) __builtin_ia32_vfmaddcph_v16hf_mask ((__v16hf) __C, + (__v16hf) __A, + (__v16hf) __B, __D); +} + +extern __inline __m256h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_maskz_fmadd_pch (__mmask8 __A, __m256h __B, __m256h __C, __m256h __D) +{ + return (__m256h)__builtin_ia32_vfmaddcph_v16hf_maskz((__v16hf) __D, + (__v16hf) __B, + (__v16hf) __C, __A); +} + +extern __inline __m128h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_fcmadd_pch (__m128h __A, __m128h __B, __m128h __C) +{ + return (__m128h)__builtin_ia32_vfcmaddcph_v8hf ((__v8hf) __C, + (__v8hf) __A, (__v8hf) __B); +} + +extern __inline __m128h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_mask_fcmadd_pch (__m128h __A, __mmask8 __B, __m128h __C, __m128h __D) +{ + return (__m128h)__builtin_ia32_movaps128_mask + ((__v4sf) + __builtin_ia32_vfcmaddcph_v8hf_mask ((__v8hf) __D, + (__v8hf) __A, + (__v8hf) __C, __B), + (__v4sf) __A, __B); +} + +extern __inline __m128h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_mask3_fcmadd_pch (__m128h __A, __m128h __B, __m128h __C, __mmask8 __D) +{ + return (__m128h) __builtin_ia32_vfcmaddcph_v8hf_mask ((__v8hf) __C, + (__v8hf) __A, + (__v8hf) __B, __D); +} + +extern __inline __m128h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_maskz_fcmadd_pch (__mmask8 __A, __m128h __B, __m128h __C, __m128h __D) +{ + return (__m128h)__builtin_ia32_vfcmaddcph_v8hf_maskz ((__v8hf) __D, + (__v8hf) __B, + (__v8hf) __C, __A); +} + +extern __inline __m256h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_fcmadd_pch (__m256h __A, __m256h __B, __m256h __C) +{ + return (__m256h)__builtin_ia32_vfcmaddcph_v16hf((__v16hf) __C, + (__v16hf) __A, (__v16hf) __B); +} + +extern __inline __m256h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_mask_fcmadd_pch (__m256h __A, __mmask8 __B, __m256h __C, __m256h __D) +{ + return (__m256h) __builtin_ia32_movaps256_mask + ((__v8sf) + __builtin_ia32_vfcmaddcph_v16hf_mask ((__v16hf) __D, + (__v16hf) __A, + (__v16hf) __C, __B), + (__v8sf) __A, __B); +} + +extern __inline __m256h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_mask3_fcmadd_pch (__m256h __A, __m256h __B, __m256h __C, __mmask8 __D) +{ + return (__m256h) __builtin_ia32_vfcmaddcph_v16hf_mask ((__v16hf) __C, + (__v16hf) __A, + (__v16hf) __B, __D); +} + +extern __inline __m256h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_maskz_fcmadd_pch (__mmask8 __A, __m256h __B, __m256h __C, __m256h __D) +{ + return (__m256h)__builtin_ia32_vfcmaddcph_v16hf_maskz((__v16hf) __D, + (__v16hf) __B, + (__v16hf) __C, __A); +} + +/* Intrinsics vf[,c]mulcph. */ +extern __inline __m128h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_fmul_pch (__m128h __A, __m128h __B) +{ + return (__m128h)__builtin_ia32_vfmulcph_v8hf((__v8hf) __A, (__v8hf) __B); +} + +extern __inline __m128h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_mask_fmul_pch (__m128h __A, __mmask8 __B, __m128h __C, __m128h __D) +{ + return (__m128h)__builtin_ia32_vfmulcph_v8hf_mask((__v8hf) __C, + (__v8hf) __D, + (__v8hf) __A, __B); +} + +extern __inline __m128h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_maskz_fmul_pch (__mmask8 __A, __m128h __B, __m128h __C) +{ + return (__m128h)__builtin_ia32_vfmulcph_v8hf_mask((__v8hf) __B, + (__v8hf) __C, + _mm_setzero_ph (), + __A); +} + +extern __inline __m256h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_fmul_pch (__m256h __A, __m256h __B) +{ + return (__m256h)__builtin_ia32_vfmulcph_v16hf((__v16hf) __A, (__v16hf) __B); +} + +extern __inline __m256h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_mask_fmul_pch (__m256h __A, __mmask8 __B, __m256h __C, __m256h __D) +{ + return (__m256h)__builtin_ia32_vfmulcph_v16hf_mask((__v16hf) __C, + (__v16hf) __D, + (__v16hf) __A, __B); +} + +extern __inline __m256h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_maskz_fmul_pch (__mmask8 __A, __m256h __B, __m256h __C) +{ + return (__m256h)__builtin_ia32_vfmulcph_v16hf_mask((__v16hf) __B, + (__v16hf) __C, + _mm256_setzero_ph (), + __A); +} + +extern __inline __m128h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_fcmul_pch (__m128h __A, __m128h __B) +{ + return (__m128h)__builtin_ia32_vfcmulcph_v8hf((__v8hf) __A, (__v8hf) __B); +} + +extern __inline __m128h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_mask_fcmul_pch (__m128h __A, __mmask8 __B, __m128h __C, __m128h __D) +{ + return (__m128h)__builtin_ia32_vfcmulcph_v8hf_mask((__v8hf) __C, (__v8hf) __D, + (__v8hf) __A, __B); +} + +extern __inline __m128h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_maskz_fcmul_pch (__mmask8 __A, __m128h __B, __m128h __C) +{ + return (__m128h)__builtin_ia32_vfcmulcph_v8hf_mask((__v8hf) __B, + (__v8hf) __C, + _mm_setzero_ph (), + __A); +} + +extern __inline __m256h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_fcmul_pch (__m256h __A, __m256h __B) +{ + return (__m256h)__builtin_ia32_vfcmulcph_v16hf((__v16hf) __A, (__v16hf) __B); +} + +extern __inline __m256h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_mask_fcmul_pch (__m256h __A, __mmask8 __B, __m256h __C, __m256h __D) +{ + return (__m256h)__builtin_ia32_vfcmulcph_v16hf_mask((__v16hf) __C, + (__v16hf) __D, + (__v16hf) __A, __B); +} + +extern __inline __m256h +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_maskz_fcmul_pch (__mmask8 __A, __m256h __B, __m256h __C) +{ + return (__m256h)__builtin_ia32_vfcmulcph_v16hf_mask((__v16hf) __B, + (__v16hf) __C, + _mm256_setzero_ph (), + __A); +} + #ifdef __DISABLE_AVX512FP16VL__ #undef __DISABLE_AVX512FP16VL__ #pragma GCC pop_options diff --git a/gcc/config/i386/i386-builtin-types.def b/gcc/config/i386/i386-builtin-types.def index 22b924bf98d..35bcafd14e3 100644 --- a/gcc/config/i386/i386-builtin-types.def +++ b/gcc/config/i386/i386-builtin-types.def @@ -1348,6 +1348,7 @@ DEF_FUNCTION_TYPE (V8DI, V8HF, V8DI, UQI, INT) DEF_FUNCTION_TYPE (V8DF, V8HF, V8DF, UQI, INT) DEF_FUNCTION_TYPE (V8HF, V8DI, V8HF, UQI, INT) DEF_FUNCTION_TYPE (V8HF, V8DF, V8HF, UQI, INT) +DEF_FUNCTION_TYPE (V8HF, V8HF, V8HF, V8HF) DEF_FUNCTION_TYPE (V8HF, V8HF, V8HF, V8HF, UQI, INT) DEF_FUNCTION_TYPE (V8HF, V2DF, V8HF, V8HF, UQI, INT) DEF_FUNCTION_TYPE (V8HF, V4SF, V8HF, V8HF, UQI, INT) @@ -1358,12 +1359,14 @@ DEF_FUNCTION_TYPE (V16HF, V16HF, V16HF) DEF_FUNCTION_TYPE (V16HI, V16HF, V16HI, UHI) DEF_FUNCTION_TYPE (V16HF, V16HI, V16HF, UHI) DEF_FUNCTION_TYPE (V16HF, V16HF, V16HF, UHI) +DEF_FUNCTION_TYPE (V16HF, V16HF, V16HF, V16HF) DEF_FUNCTION_TYPE (V16SI, V16HF, V16SI, UHI, INT) DEF_FUNCTION_TYPE (V16SF, V16HF, V16SF, UHI, INT) DEF_FUNCTION_TYPE (V16HF, V16HF, INT, V16HF, UHI) DEF_FUNCTION_TYPE (UHI, V16HF, V16HF, INT, UHI) DEF_FUNCTION_TYPE (V16HF, V16SI, V16HF, UHI, INT) DEF_FUNCTION_TYPE (V16HF, V16SF, V16HF, UHI, INT) +DEF_FUNCTION_TYPE (V16HF, V16HF, V16HF, V16HF, UQI) DEF_FUNCTION_TYPE (V16HF, V16HF, V16HF, V16HF, UHI) DEF_FUNCTION_TYPE (V32HF, V32HF, V32HF, USI) DEF_FUNCTION_TYPE (V32HF, V32HF, V32HF, INT) @@ -1371,7 +1374,9 @@ DEF_FUNCTION_TYPE (V32HI, V32HF, V32HI, USI, INT) DEF_FUNCTION_TYPE (V32HF, V32HI, V32HF, USI, INT) DEF_FUNCTION_TYPE (USI, V32HF, V32HF, INT, USI) DEF_FUNCTION_TYPE (V32HF, V32HF, V32HF, USI, INT) +DEF_FUNCTION_TYPE (V32HF, V32HF, V32HF, V32HF, INT) DEF_FUNCTION_TYPE (V32HF, V32HF, V32HF, V32HF, USI) DEF_FUNCTION_TYPE (USI, V32HF, V32HF, INT, USI, INT) +DEF_FUNCTION_TYPE (V32HF, V32HF, V32HF, V32HF, UHI, INT) DEF_FUNCTION_TYPE (V32HF, V32HF, V32HF, V32HF, USI, INT) DEF_FUNCTION_TYPE (V32HF, V32HF, INT, V32HF, USI, INT) diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def index f446a6ce5d3..448f9f75fa4 100644 --- a/gcc/config/i386/i386-builtin.def +++ b/gcc/config/i386/i386-builtin.def @@ -2911,6 +2911,26 @@ BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512vl_ BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512fp16_fnmsub_v8hf_mask, "__builtin_ia32_vfnmsubph128_mask", IX86_BUILTIN_VFNMSUBPH128_MASK, UNKNOWN, (int) V8HF_FTYPE_V8HF_V8HF_V8HF_UQI) BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512fp16_fnmsub_v8hf_mask3, "__builtin_ia32_vfnmsubph128_mask3", IX86_BUILTIN_VFNMSUBPH128_MASK3, UNKNOWN, (int) V8HF_FTYPE_V8HF_V8HF_V8HF_UQI) BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512fp16_fnmsub_v8hf_maskz, "__builtin_ia32_vfnmsubph128_maskz", IX86_BUILTIN_VFNMSUBPH128_MASKZ, UNKNOWN, (int) V8HF_FTYPE_V8HF_V8HF_V8HF_UQI) +BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_fma_fmaddc_v8hf, "__builtin_ia32_vfmaddcph_v8hf", IX86_BUILTIN_VFMADDCPH_V8HF, UNKNOWN, (int) V8HF_FTYPE_V8HF_V8HF_V8HF) +BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512fp16_fmaddc_v8hf_mask, "__builtin_ia32_vfmaddcph_v8hf_mask", IX86_BUILTIN_VFMADDCPH_V8HF_MASK, UNKNOWN, (int) V8HF_FTYPE_V8HF_V8HF_V8HF_UQI) +BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512fp16_fmaddc_v8hf_maskz, "__builtin_ia32_vfmaddcph_v8hf_maskz", IX86_BUILTIN_VFMADDCPH_V8HF_MASKZ, UNKNOWN, (int) V8HF_FTYPE_V8HF_V8HF_V8HF_UQI) +BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_fma_fmaddc_v16hf, "__builtin_ia32_vfmaddcph_v16hf", IX86_BUILTIN_VFMADDCPH_V16HF, UNKNOWN, (int) V16HF_FTYPE_V16HF_V16HF_V16HF) +BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512vl_fmaddc_v16hf_mask, "__builtin_ia32_vfmaddcph_v16hf_mask", IX86_BUILTIN_VFMADDCPH_V16HF_MASK, UNKNOWN, (int) V16HF_FTYPE_V16HF_V16HF_V16HF_UQI) +BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512vl_fmaddc_v16hf_maskz, "__builtin_ia32_vfmaddcph_v16hf_maskz", IX86_BUILTIN_VFMADDCPH_V16HF_MASKZ, UNKNOWN, (int) V16HF_FTYPE_V16HF_V16HF_V16HF_UQI) +BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_fma_fcmaddc_v8hf, "__builtin_ia32_vfcmaddcph_v8hf", IX86_BUILTIN_VFCMADDCPH_V8HF, UNKNOWN, (int) V8HF_FTYPE_V8HF_V8HF_V8HF) +BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512fp16_fcmaddc_v8hf_mask, "__builtin_ia32_vfcmaddcph_v8hf_mask", IX86_BUILTIN_VFCMADDCPH_V8HF_MASK, UNKNOWN, (int) V8HF_FTYPE_V8HF_V8HF_V8HF_UQI) +BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512fp16_fcmaddc_v8hf_maskz, "__builtin_ia32_vfcmaddcph_v8hf_maskz", IX86_BUILTIN_VFCMADDCPH_V8HF_MASKZ, UNKNOWN, (int) V8HF_FTYPE_V8HF_V8HF_V8HF_UQI) +BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_fma_fcmaddc_v16hf, "__builtin_ia32_vfcmaddcph_v16hf", IX86_BUILTIN_VFCMADDCPH_V16HF, UNKNOWN, (int) V16HF_FTYPE_V16HF_V16HF_V16HF) +BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512vl_fcmaddc_v16hf_mask, "__builtin_ia32_vfcmaddcph_v16hf_mask", IX86_BUILTIN_VFCMADDCPH_V16HF_MASK, UNKNOWN, (int) V16HF_FTYPE_V16HF_V16HF_V16HF_UQI) +BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512vl_fcmaddc_v16hf_maskz, "__builtin_ia32_vfcmaddcph_v16hf_maskz", IX86_BUILTIN_VFCMADDCPH_V16HF_MASKZ, UNKNOWN, (int) V16HF_FTYPE_V16HF_V16HF_V16HF_UQI) +BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512fp16_fcmulc_v8hf, "__builtin_ia32_vfcmulcph_v8hf", IX86_BUILTIN_VFCMULCPH_V8HF, UNKNOWN, (int) V8HF_FTYPE_V8HF_V8HF) +BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512fp16_fcmulc_v8hf_mask, "__builtin_ia32_vfcmulcph_v8hf_mask", IX86_BUILTIN_VFCMULCPH_V8HF_MASK, UNKNOWN, (int) V8HF_FTYPE_V8HF_V8HF_V8HF_UQI) +BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512vl_fcmulc_v16hf, "__builtin_ia32_vfcmulcph_v16hf", IX86_BUILTIN_VFCMULCPH_V16HF, UNKNOWN, (int) V16HF_FTYPE_V16HF_V16HF) +BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512vl_fcmulc_v16hf_mask, "__builtin_ia32_vfcmulcph_v16hf_mask", IX86_BUILTIN_VFCMULCPH_V16HF_MASK, UNKNOWN, (int) V16HF_FTYPE_V16HF_V16HF_V16HF_UQI) +BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512fp16_fmulc_v8hf, "__builtin_ia32_vfmulcph_v8hf", IX86_BUILTIN_VFMULCPH_V8HF, UNKNOWN, (int) V8HF_FTYPE_V8HF_V8HF) +BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512fp16_fmulc_v8hf_mask, "__builtin_ia32_vfmulcph_v8hf_mask", IX86_BUILTIN_VFMULCPH_V8HF_MASK, UNKNOWN, (int) V8HF_FTYPE_V8HF_V8HF_V8HF_UQI) +BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512vl_fmulc_v16hf, "__builtin_ia32_vfmulcph_v16hf", IX86_BUILTIN_VFMULCPH_V16HF, UNKNOWN, (int) V16HF_FTYPE_V16HF_V16HF) +BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512vl_fmulc_v16hf_mask, "__builtin_ia32_vfmulcph_v16hf_mask", IX86_BUILTIN_VFMULCPH_V16HF_MASK, UNKNOWN, (int) V16HF_FTYPE_V16HF_V16HF_V16HF_UQI) /* Builtins with rounding support. */ BDESC_END (ARGS, ROUND_ARGS) @@ -3201,6 +3221,16 @@ BDESC (0, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512f_vmfnmadd_v8hf_mask_round BDESC (0, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512f_vmfnmadd_v8hf_mask3_round, "__builtin_ia32_vfnmaddsh3_mask3", IX86_BUILTIN_VFNMADDSH3_MASK3, UNKNOWN, (int) V8HF_FTYPE_V8HF_V8HF_V8HF_UQI_INT) BDESC (0, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512f_vmfnmadd_v8hf_maskz_round, "__builtin_ia32_vfnmaddsh3_maskz", IX86_BUILTIN_VFNMADDSH3_MASKZ, UNKNOWN, (int) V8HF_FTYPE_V8HF_V8HF_V8HF_UQI_INT) BDESC (0, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512f_vmfmsub_v8hf_mask3_round, "__builtin_ia32_vfmsubsh3_mask3", IX86_BUILTIN_VFMSUBSH3_MASK3, UNKNOWN, (int) V8HF_FTYPE_V8HF_V8HF_V8HF_UQI_INT) +BDESC (0, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_fma_fmaddc_v32hf_round, "__builtin_ia32_vfmaddcph_v32hf_round", IX86_BUILTIN_VFMADDCPH_V32HF_ROUND, UNKNOWN, (int) V32HF_FTYPE_V32HF_V32HF_V32HF_INT) +BDESC (0, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512bw_fmaddc_v32hf_mask_round, "__builtin_ia32_vfmaddcph_v32hf_mask_round", IX86_BUILTIN_VFMADDCPH_V32HF_MASK_ROUND, UNKNOWN, (int) V32HF_FTYPE_V32HF_V32HF_V32HF_UHI_INT) +BDESC (0, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512bw_fmaddc_v32hf_maskz_round, "__builtin_ia32_vfmaddcph_v32hf_maskz_round", IX86_BUILTIN_VFMADDCPH_V32HF_MASKZ_ROUND, UNKNOWN, (int) V32HF_FTYPE_V32HF_V32HF_V32HF_UHI_INT) +BDESC (0, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_fma_fcmaddc_v32hf_round, "__builtin_ia32_vfcmaddcph_v32hf_round", IX86_BUILTIN_VFCMADDCPH_V32HF_ROUND, UNKNOWN, (int) V32HF_FTYPE_V32HF_V32HF_V32HF_INT) +BDESC (0, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512bw_fcmaddc_v32hf_mask_round, "__builtin_ia32_vfcmaddcph_v32hf_mask_round", IX86_BUILTIN_VFCMADDCPH_V32HF_MASK_ROUND, UNKNOWN, (int) V32HF_FTYPE_V32HF_V32HF_V32HF_UHI_INT) +BDESC (0, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512bw_fcmaddc_v32hf_maskz_round, "__builtin_ia32_vfcmaddcph_v32hf_maskz_round", IX86_BUILTIN_VFCMADDCPH_V32HF_MASKZ_ROUND, UNKNOWN, (int) V32HF_FTYPE_V32HF_V32HF_V32HF_UHI_INT) +BDESC (0, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512bw_fcmulc_v32hf_round, "__builtin_ia32_vfcmulcph_v32hf_round", IX86_BUILTIN_VFCMULCPH_V32HF_ROUND, UNKNOWN, (int) V32HF_FTYPE_V32HF_V32HF_INT) +BDESC (0, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512bw_fcmulc_v32hf_mask_round, "__builtin_ia32_vfcmulcph_v32hf_mask_round", IX86_BUILTIN_VFCMULCPH_V32HF_MASK_ROUND, UNKNOWN, (int) V32HF_FTYPE_V32HF_V32HF_V32HF_UHI_INT) +BDESC (0, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512bw_fmulc_v32hf_round, "__builtin_ia32_vfmulcph_v32hf_round", IX86_BUILTIN_VFMULCPH_V32HF_ROUND, UNKNOWN, (int) V32HF_FTYPE_V32HF_V32HF_INT) +BDESC (0, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512bw_fmulc_v32hf_mask_round, "__builtin_ia32_vfmulcph_v32hf_mask_round", IX86_BUILTIN_VFMULCPH_V32HF_MASK_ROUND, UNKNOWN, (int) V32HF_FTYPE_V32HF_V32HF_V32HF_UHI_INT) BDESC_END (ROUND_ARGS, MULTI_ARG) diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c index f6de05c769a..f6d74549dc2 100644 --- a/gcc/config/i386/i386-expand.c +++ b/gcc/config/i386/i386-expand.c @@ -9582,6 +9582,7 @@ ix86_expand_args_builtin (const struct builtin_description *d, case V2DI_FTYPE_V8HF_V2DI_UQI: case V2DI_FTYPE_V4SF_V2DI_UQI: case V8HF_FTYPE_V8HF_V8HF_UQI: + case V8HF_FTYPE_V8HF_V8HF_V8HF: case V8HF_FTYPE_V8HI_V8HF_UQI: case V8HF_FTYPE_V8SI_V8HF_UQI: case V8HF_FTYPE_V8SF_V8HF_UQI: @@ -9660,6 +9661,7 @@ ix86_expand_args_builtin (const struct builtin_description *d, case V16SF_FTYPE_V8SF_V16SF_UHI: case V16SI_FTYPE_V8SI_V16SI_UHI: case V16HF_FTYPE_V16HI_V16HF_UHI: + case V16HF_FTYPE_V16HF_V16HF_V16HF: case V16HI_FTYPE_V16HF_V16HI_UHI: case V16HI_FTYPE_V16HI_V16HI_UHI: case V8HI_FTYPE_V16QI_V8HI_UQI: @@ -9816,6 +9818,7 @@ ix86_expand_args_builtin (const struct builtin_description *d, case V8HI_FTYPE_V8HI_V8HI_V8HI_UQI: case V8SI_FTYPE_V8SI_V8SI_V8SI_UQI: case V4SI_FTYPE_V4SI_V4SI_V4SI_UQI: + case V16HF_FTYPE_V16HF_V16HF_V16HF_UQI: case V16HF_FTYPE_V16HF_V16HF_V16HF_UHI: case V8SF_FTYPE_V8SF_V8SF_V8SF_UQI: case V16QI_FTYPE_V16QI_V16QI_V16QI_UHI: @@ -10545,6 +10548,7 @@ ix86_expand_round_builtin (const struct builtin_description *d, case V16SF_FTYPE_V16HF_V16SF_UHI_INT: case V32HF_FTYPE_V32HI_V32HF_USI_INT: case V32HF_FTYPE_V32HF_V32HF_USI_INT: + case V32HF_FTYPE_V32HF_V32HF_V32HF_INT: case V16SF_FTYPE_V16SF_V16SF_HI_INT: case V8DI_FTYPE_V8SF_V8DI_QI_INT: case V16SF_FTYPE_V16SI_V16SF_HI_INT: @@ -10574,6 +10578,7 @@ ix86_expand_round_builtin (const struct builtin_description *d, case V4SF_FTYPE_V4SF_V4SF_V4SF_UQI_INT: case V4SF_FTYPE_V8HF_V4SF_V4SF_UQI_INT: case V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT: + case V32HF_FTYPE_V32HF_V32HF_V32HF_UHI_INT: case V32HF_FTYPE_V32HF_V32HF_V32HF_USI_INT: case V2DF_FTYPE_V8HF_V2DF_V2DF_UQI_INT: case V2DF_FTYPE_V2DF_V2DF_V2DF_QI_INT: diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 31f8fc68c65..ddd93f739e3 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -194,6 +194,14 @@ (define_c_enum "unspec" [ UNSPEC_VCVTNE2PS2BF16 UNSPEC_VCVTNEPS2BF16 UNSPEC_VDPBF16PS + + ;; For AVX512FP16 suppport + UNSPEC_COMPLEX_FMA + UNSPEC_COMPLEX_FCMA + UNSPEC_COMPLEX_FMUL + UNSPEC_COMPLEX_FCMUL + UNSPEC_COMPLEX_MASK + ]) (define_c_enum "unspecv" [ @@ -909,6 +917,10 @@ (define_mode_attr avx512fmaskmode (V16SF "HI") (V8SF "QI") (V4SF "QI") (V8DF "QI") (V4DF "QI") (V2DF "QI")]) +;; Mapping of vector modes to corresponding complex mask size +(define_mode_attr avx512fmaskcmode + [(V32HF "HI") (V16HF "QI") (V8HF "QI")]) + ;; Mapping of vector modes to corresponding mask size (define_mode_attr avx512fmaskmodelower [(V64QI "di") (V32QI "si") (V16QI "hi") @@ -5499,6 +5511,92 @@ (define_insn "*fma4i_vmfnmsub_<mode>" [(set_attr "type" "ssemuladd") (set_attr "mode" "<MODE>")]) +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Complex type operations +;; +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +(define_int_iterator UNSPEC_COMPLEX_F_C_MA + [UNSPEC_COMPLEX_FMA UNSPEC_COMPLEX_FCMA]) + +(define_int_iterator UNSPEC_COMPLEX_F_C_MUL + [UNSPEC_COMPLEX_FMUL UNSPEC_COMPLEX_FCMUL]) + +(define_int_attr complexopname + [(UNSPEC_COMPLEX_FMA "fmaddc") + (UNSPEC_COMPLEX_FCMA "fcmaddc") + (UNSPEC_COMPLEX_FMUL "fmulc") + (UNSPEC_COMPLEX_FCMUL "fcmulc")]) + +(define_expand "<avx512>_fmaddc_<mode>_maskz<round_expand_name>" + [(match_operand:VF_AVX512FP16VL 0 "register_operand") + (match_operand:VF_AVX512FP16VL 1 "<round_expand_nimm_predicate>") + (match_operand:VF_AVX512FP16VL 2 "<round_expand_nimm_predicate>") + (match_operand:VF_AVX512FP16VL 3 "<round_expand_nimm_predicate>") + (match_operand:<avx512fmaskcmode> 4 "register_operand")] + "TARGET_AVX512FP16 && <round_mode512bit_condition>" +{ + emit_insn (gen_fma_fmaddc_<mode>_maskz_1<round_expand_name> ( + operands[0], operands[1], operands[2], operands[3], + CONST0_RTX (<MODE>mode), operands[4]<round_expand_operand>)); + DONE; +}) + +(define_expand "<avx512>_fcmaddc_<mode>_maskz<round_expand_name>" + [(match_operand:VF_AVX512FP16VL 0 "register_operand") + (match_operand:VF_AVX512FP16VL 1 "<round_expand_nimm_predicate>") + (match_operand:VF_AVX512FP16VL 2 "<round_expand_nimm_predicate>") + (match_operand:VF_AVX512FP16VL 3 "<round_expand_nimm_predicate>") + (match_operand:<avx512fmaskcmode> 4 "register_operand")] + "TARGET_AVX512FP16 && <round_mode512bit_condition>" +{ + emit_insn (gen_fma_fcmaddc_<mode>_maskz_1<round_expand_name> ( + operands[0], operands[1], operands[2], operands[3], + CONST0_RTX (<MODE>mode), operands[4]<round_expand_operand>)); + DONE; +}) + +(define_insn "fma_<complexopname>_<mode><sdc_maskz_name><round_name>" + [(set (match_operand:VF_AVX512FP16VL 0 "register_operand" "=v") + (unspec:VF_AVX512FP16VL + [(match_operand:VF_AVX512FP16VL 1 "<round_nimm_predicate>" "0") + (match_operand:VF_AVX512FP16VL 2 "<round_nimm_predicate>" "%v") + (match_operand:VF_AVX512FP16VL 3 "<round_nimm_predicate>" "<round_constraint>")] + UNSPEC_COMPLEX_F_C_MA))] + "TARGET_AVX512FP16 && <sdc_mask_mode512bit_condition> && <round_mode512bit_condition>" + "v<complexopname><ssemodesuffix>\t{<round_sdc_mask_op4>%3, %2, %0<sdc_mask_op4>|%0<sdc_mask_op4>, %2, %3<round_sdc_mask_op4>}" + [(set_attr "type" "ssemuladd") + (set_attr "mode" "<MODE>")]) + +(define_insn "<avx512>_<complexopname>_<mode>_mask<round_name>" + [(set (match_operand:VF_AVX512FP16VL 0 "register_operand" "=v") + (vec_merge:VF_AVX512FP16VL + (unspec:VF_AVX512FP16VL + [(match_operand:VF_AVX512FP16VL 1 "register_operand" "0") + (match_operand:VF_AVX512FP16VL 2 "nonimmediate_operand" "%v") + (match_operand:VF_AVX512FP16VL 3 "nonimmediate_operand" "<round_constraint>")] + UNSPEC_COMPLEX_F_C_MA) + (match_dup 1) + (unspec:<avx512fmaskmode> + [(match_operand:<avx512fmaskcmode> 4 "register_operand" "Yk")] + UNSPEC_COMPLEX_MASK)))] + "TARGET_AVX512FP16 && <round_mode512bit_condition>" + "v<complexopname><ssemodesuffix>\t{<round_op5>%3, %2, %0%{%4%}|%0%{%4%}, %2, %3<round_op5>}" + [(set_attr "type" "ssemuladd") + (set_attr "mode" "<MODE>")]) + +(define_insn "<avx512>_<complexopname>_<mode><maskc_name><round_name>" + [(set (match_operand:VF_AVX512FP16VL 0 "register_operand" "=v") + (unspec:VF_AVX512FP16VL + [(match_operand:VF_AVX512FP16VL 1 "nonimmediate_operand" "%v") + (match_operand:VF_AVX512FP16VL 2 "nonimmediate_operand" "<round_constraint>")] + UNSPEC_COMPLEX_F_C_MUL))] + "TARGET_AVX512FP16 && <round_mode512bit_condition>" + "v<complexopname><ssemodesuffix>\t{<round_maskc_op3>%2, %1, %0<maskc_operand3>|%0<maskc_operand3>, %1, %2<round_maskc_op3>}" + [(set_attr "type" "ssemul") + (set_attr "mode" "<MODE>")]) + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; Parallel half-precision floating point conversion operations diff --git a/gcc/config/i386/subst.md b/gcc/config/i386/subst.md index 2e9c2b38e25..3a1f554e9b9 100644 --- a/gcc/config/i386/subst.md +++ b/gcc/config/i386/subst.md @@ -28,6 +28,9 @@ (define_mode_iterator SUBST_V V16SF V8SF V4SF V8DF V4DF V2DF]) +(define_mode_iterator SUBST_CV + [V32HF V16HF V8HF]) + (define_mode_iterator SUBST_S [QI HI SI DI]) @@ -42,9 +45,11 @@ (define_mode_iterator SUBST_A QI HI SI DI SF DF]) (define_subst_attr "mask_name" "mask" "" "_mask") +(define_subst_attr "maskc_name" "maskc" "" "_mask") (define_subst_attr "mask_applied" "mask" "false" "true") (define_subst_attr "mask_operand2" "mask" "" "%{%3%}%N2") (define_subst_attr "mask_operand3" "mask" "" "%{%4%}%N3") +(define_subst_attr "maskc_operand3" "maskc" "" "%{%4%}%N3") (define_subst_attr "mask_operand3_1" "mask" "" "%%{%%4%%}%%N3") ;; for sprintf (define_subst_attr "mask_operand4" "mask" "" "%{%5%}%N4") (define_subst_attr "mask_operand6" "mask" "" "%{%7%}%N6") @@ -89,6 +94,18 @@ (define_subst "merge_mask" (match_dup 0) (match_operand:<avx512fmaskmode> 2 "register_operand" "Yk")))]) +(define_subst "maskc" + [(set (match_operand:SUBST_CV 0) + (match_operand:SUBST_CV 1))] + "TARGET_AVX512F" + [(set (match_dup 0) + (vec_merge:SUBST_CV + (match_dup 1) + (match_operand:SUBST_CV 2 "nonimm_or_0_operand" "0C") + (unspec:<avx512fmaskmode> + [(match_operand:<avx512fmaskcmode> 3 "register_operand" "Yk")] + UNSPEC_COMPLEX_MASK)))]) + (define_subst_attr "mask_scalar_merge_name" "mask_scalar_merge" "" "_mask") (define_subst_attr "mask_scalar_merge_operand3" "mask_scalar_merge" "" "%{%3%}") (define_subst_attr "mask_scalar_merge_operand4" "mask_scalar_merge" "" "%{%4%}") @@ -119,11 +136,31 @@ (define_subst "sd" (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk"))) ]) +(define_subst_attr "sdc_maskz_name" "sdc" "" "_maskz_1") +(define_subst_attr "sdc_mask_op4" "sdc" "" "%{%5%}%N4") +(define_subst_attr "sdc_mask_op5" "sdc" "" "%{%6%}%N5") +(define_subst_attr "sdc_mask_mode512bit_condition" "sdc" "1" "(<MODE_SIZE> == 64 || TARGET_AVX512VL)") + +(define_subst "sdc" + [(set (match_operand:SUBST_CV 0) + (match_operand:SUBST_CV 1))] + "" + [(set (match_dup 0) + (vec_merge:SUBST_CV + (match_dup 1) + (match_operand:SUBST_CV 2 "const0_operand" "C") + (unspec:<avx512fmaskmode> + [(match_operand:<avx512fmaskcmode> 3 "register_operand" "Yk")] + UNSPEC_COMPLEX_MASK))) +]) + (define_subst_attr "round_name" "round" "" "_round") (define_subst_attr "round_mask_operand2" "mask" "%R2" "%R4") (define_subst_attr "round_mask_operand3" "mask" "%R3" "%R5") +(define_subst_attr "round_maskc_operand3" "maskc" "%R3" "%R5") (define_subst_attr "round_mask_operand4" "mask" "%R4" "%R6") (define_subst_attr "round_sd_mask_operand4" "sd" "%R4" "%R6") +(define_subst_attr "round_sdc_mask_operand4" "sdc" "%R4" "%R6") (define_subst_attr "round_op2" "round" "" "%R2") (define_subst_attr "round_op3" "round" "" "%R3") (define_subst_attr "round_op4" "round" "" "%R4") @@ -131,8 +168,10 @@ (define_subst_attr "round_op5" "round" "" "%R5") (define_subst_attr "round_op6" "round" "" "%R6") (define_subst_attr "round_mask_op2" "round" "" "<round_mask_operand2>") (define_subst_attr "round_mask_op3" "round" "" "<round_mask_operand3>") +(define_subst_attr "round_maskc_op3" "round" "" "<round_maskc_operand3>") (define_subst_attr "round_mask_op4" "round" "" "<round_mask_operand4>") (define_subst_attr "round_sd_mask_op4" "round" "" "<round_sd_mask_operand4>") +(define_subst_attr "round_sdc_mask_op4" "round" "" "<round_sdc_mask_operand4>") (define_subst_attr "round_constraint" "round" "vm" "v") (define_subst_attr "round_qq2phsuff" "round" "<qq2phsuff>" "") (define_subst_attr "bcst_round_constraint" "round" "vmBr" "v") @@ -169,6 +208,7 @@ (define_subst_attr "round_saeonly_mask_operand3" "mask" "%r3" "%r5") (define_subst_attr "round_saeonly_mask_operand4" "mask" "%r4" "%r6") (define_subst_attr "round_saeonly_mask_scalar_merge_operand4" "mask_scalar_merge" "%r4" "%r5") (define_subst_attr "round_saeonly_sd_mask_operand5" "sd" "%r5" "%r7") +(define_subst_attr "round_saeonly_sdc_mask_operand5" "sdc" "%r5" "%r7") (define_subst_attr "round_saeonly_op2" "round_saeonly" "" "%r2") (define_subst_attr "round_saeonly_op3" "round_saeonly" "" "%r3") (define_subst_attr "round_saeonly_op4" "round_saeonly" "" "%r4") diff --git a/gcc/testsuite/gcc.target/i386/avx-1.c b/gcc/testsuite/gcc.target/i386/avx-1.c index 6c2d1dc3df4..56e90d9f9a5 100644 --- a/gcc/testsuite/gcc.target/i386/avx-1.c +++ b/gcc/testsuite/gcc.target/i386/avx-1.c @@ -787,6 +787,16 @@ #define __builtin_ia32_vfnmsubsh3_mask(A, B, C, D, E) __builtin_ia32_vfnmsubsh3_mask(A, B, C, D, 8) #define __builtin_ia32_vfnmsubsh3_mask3(A, B, C, D, E) __builtin_ia32_vfnmsubsh3_mask3(A, B, C, D, 8) #define __builtin_ia32_vfnmsubsh3_maskz(A, B, C, D, E) __builtin_ia32_vfnmsubsh3_maskz(A, B, C, D, 8) +#define __builtin_ia32_vfcmaddcph_v32hf_round(A, B, C, D) __builtin_ia32_vfcmaddcph_v32hf_round(A, B, C, 8) +#define __builtin_ia32_vfcmaddcph_v32hf_mask_round(A, C, D, B, E) __builtin_ia32_vfcmaddcph_v32hf_mask_round(A, C, D, B, 8) +#define __builtin_ia32_vfcmaddcph_v32hf_maskz_round(B, C, D, A, E) __builtin_ia32_vfcmaddcph_v32hf_maskz_round(B, C, D, A, 8) +#define __builtin_ia32_vfmaddcph_v32hf_round(A, B, C, D) __builtin_ia32_vfmaddcph_v32hf_round(A, B, C, 8) +#define __builtin_ia32_vfmaddcph_v32hf_mask_round(A, C, D, B, E) __builtin_ia32_vfmaddcph_v32hf_mask_round(A, C, D, B, 8) +#define __builtin_ia32_vfmaddcph_v32hf_maskz_round(B, C, D, A, E) __builtin_ia32_vfmaddcph_v32hf_maskz_round(B, C, D, A, 8) +#define __builtin_ia32_vfmulcph_v32hf_round(A, B, C) __builtin_ia32_vfmulcph_v32hf_round(A, B, 8) +#define __builtin_ia32_vfmulcph_v32hf_mask_round(A, C, D, B, E) __builtin_ia32_vfmulcph_v32hf_mask_round(A, C, D, B, 8) +#define __builtin_ia32_vfcmulcph_v32hf_round(A, B, C) __builtin_ia32_vfcmulcph_v32hf_round(A, B, 8) +#define __builtin_ia32_vfcmulcph_v32hf_mask_round(A, C, D, B, E) __builtin_ia32_vfcmulcph_v32hf_mask_round(A, C, D, B, 8) /* avx512fp16vlintrin.h */ #define __builtin_ia32_vcmpph_v8hf_mask(A, B, C, D) __builtin_ia32_vcmpph_v8hf_mask(A, B, 1, D) diff --git a/gcc/testsuite/gcc.target/i386/sse-13.c b/gcc/testsuite/gcc.target/i386/sse-13.c index f16be008909..ef9f8aad853 100644 --- a/gcc/testsuite/gcc.target/i386/sse-13.c +++ b/gcc/testsuite/gcc.target/i386/sse-13.c @@ -804,6 +804,16 @@ #define __builtin_ia32_vfnmsubsh3_mask(A, B, C, D, E) __builtin_ia32_vfnmsubsh3_mask(A, B, C, D, 8) #define __builtin_ia32_vfnmsubsh3_mask3(A, B, C, D, E) __builtin_ia32_vfnmsubsh3_mask3(A, B, C, D, 8) #define __builtin_ia32_vfnmsubsh3_maskz(A, B, C, D, E) __builtin_ia32_vfnmsubsh3_maskz(A, B, C, D, 8) +#define __builtin_ia32_vfcmaddcph_v32hf_round(A, B, C, D) __builtin_ia32_vfcmaddcph_v32hf_round(A, B, C, 8) +#define __builtin_ia32_vfcmaddcph_v32hf_mask_round(A, C, D, B, E) __builtin_ia32_vfcmaddcph_v32hf_mask_round(A, C, D, B, 8) +#define __builtin_ia32_vfcmaddcph_v32hf_maskz_round(B, C, D, A, E) __builtin_ia32_vfcmaddcph_v32hf_maskz_round(B, C, D, A, 8) +#define __builtin_ia32_vfmaddcph_v32hf_round(A, B, C, D) __builtin_ia32_vfmaddcph_v32hf_round(A, B, C, 8) +#define __builtin_ia32_vfmaddcph_v32hf_mask_round(A, C, D, B, E) __builtin_ia32_vfmaddcph_v32hf_mask_round(A, C, D, B, 8) +#define __builtin_ia32_vfmaddcph_v32hf_maskz_round(B, C, D, A, E) __builtin_ia32_vfmaddcph_v32hf_maskz_round(B, C, D, A, 8) +#define __builtin_ia32_vfmulcph_v32hf_round(A, B, C) __builtin_ia32_vfmulcph_v32hf_round(A, B, 8) +#define __builtin_ia32_vfmulcph_v32hf_mask_round(A, C, D, B, E) __builtin_ia32_vfmulcph_v32hf_mask_round(A, C, D, B, 8) +#define __builtin_ia32_vfcmulcph_v32hf_round(A, B, C) __builtin_ia32_vfcmulcph_v32hf_round(A, B, 8) +#define __builtin_ia32_vfcmulcph_v32hf_mask_round(A, C, D, B, E) __builtin_ia32_vfcmulcph_v32hf_mask_round(A, C, D, B, 8) /* avx512fp16vlintrin.h */ #define __builtin_ia32_vcmpph_v8hf_mask(A, B, C, D) __builtin_ia32_vcmpph_v8hf_mask(A, B, 1, D) diff --git a/gcc/testsuite/gcc.target/i386/sse-14.c b/gcc/testsuite/gcc.target/i386/sse-14.c index 01ac4e04173..f27c73fd4cc 100644 --- a/gcc/testsuite/gcc.target/i386/sse-14.c +++ b/gcc/testsuite/gcc.target/i386/sse-14.c @@ -772,6 +772,8 @@ test_2 (_mm_cvt_roundss_sh, __m128h, __m128h, __m128, 8) test_2 (_mm_cvt_roundsd_sh, __m128h, __m128h, __m128d, 8) test_2 (_mm_cvt_roundi32_sh, __m128h, __m128h, int, 8) test_2 (_mm_cvt_roundu32_sh, __m128h, __m128h, unsigned, 8) +test_2 (_mm512_fmul_round_pch, __m512h, __m512h, __m512h, 8) +test_2 (_mm512_fcmul_round_pch, __m512h, __m512h, __m512h, 8) test_2x (_mm512_cmp_round_ph_mask, __mmask32, __m512h, __m512h, 1, 8) test_2x (_mm_cmp_round_sh_mask, __mmask8, __m128h, __m128h, 1, 8) test_2x (_mm_comi_round_sh, int, __m128h, __m128h, 1, 8) @@ -846,6 +848,10 @@ test_3 (_mm_fmadd_round_sh, __m128h, __m128h, __m128h, __m128h, 9) test_3 (_mm_fnmadd_round_sh, __m128h, __m128h, __m128h, __m128h, 9) test_3 (_mm_fmsub_round_sh, __m128h, __m128h, __m128h, __m128h, 9) test_3 (_mm_fnmsub_round_sh, __m128h, __m128h, __m128h, __m128h, 9) +test_3 (_mm512_fmadd_round_pch, __m512h, __m512h, __m512h, __m512h, 8) +test_3 (_mm512_fcmadd_round_pch, __m512h, __m512h, __m512h, __m512h, 8) +test_3 (_mm512_maskz_fmul_round_pch, __m512h, __mmask16, __m512h, __m512h, 8) +test_3 (_mm512_maskz_fcmul_round_pch, __m512h, __mmask16, __m512h, __m512h, 8) test_3x (_mm512_mask_cmp_round_ph_mask, __mmask32, __mmask32, __m512h, __m512h, 1, 8) test_3x (_mm_mask_cmp_round_sh_mask, __mmask8, __mmask8, __m128h, __m128h, 1, 8) test_3x (_mm512_mask_reduce_round_ph, __m512h, __m512h, __mmask32, __m512h, 123, 8) @@ -908,6 +914,14 @@ test_4 (_mm_maskz_fmsub_round_sh, __m128h, __mmask8, __m128h, __m128h, __m128h, test_4 (_mm_mask_fnmsub_round_sh, __m128h, __m128h, __mmask8, __m128h, __m128h, 9) test_4 (_mm_mask3_fnmsub_round_sh, __m128h, __m128h, __m128h, __m128h, __mmask8, 9) test_4 (_mm_maskz_fnmsub_round_sh, __m128h, __mmask8, __m128h, __m128h, __m128h, 9) +test_4 (_mm512_mask_fmadd_round_pch, __m512h, __m512h, __mmask16, __m512h, __m512h, 8) +test_4 (_mm512_mask_fcmadd_round_pch, __m512h, __m512h, __mmask16, __m512h, __m512h, 8) +test_4 (_mm512_mask3_fmadd_round_pch, __m512h, __m512h, __m512h, __m512h, __mmask16, 8) +test_4 (_mm512_mask3_fcmadd_round_pch, __m512h, __m512h, __m512h, __m512h, __mmask16, 8) +test_4 (_mm512_maskz_fmadd_round_pch, __m512h, __mmask16, __m512h, __m512h, __m512h, 8) +test_4 (_mm512_maskz_fcmadd_round_pch, __m512h, __mmask16, __m512h, __m512h, __m512h, 8) +test_4 (_mm512_mask_fmul_round_pch, __m512h, __m512h, __mmask16, __m512h, __m512h, 8) +test_4 (_mm512_mask_fcmul_round_pch, __m512h, __m512h, __mmask16, __m512h, __m512h, 8) test_4x (_mm_mask_reduce_round_sh, __m128h, __m128h, __mmask8, __m128h, __m128h, 123, 8) test_4x (_mm_mask_roundscale_round_sh, __m128h, __m128h, __mmask8, __m128h, __m128h, 123, 8) test_4x (_mm_mask_getmant_sh, __m128h, __m128h, __mmask8, __m128h, __m128h, 1, 1) diff --git a/gcc/testsuite/gcc.target/i386/sse-22.c b/gcc/testsuite/gcc.target/i386/sse-22.c index 79e3f35ab86..ccf8c3a6c03 100644 --- a/gcc/testsuite/gcc.target/i386/sse-22.c +++ b/gcc/testsuite/gcc.target/i386/sse-22.c @@ -876,6 +876,8 @@ test_2 (_mm_cvt_roundsh_ss, __m128, __m128, __m128h, 8) test_2 (_mm_cvt_roundsh_sd, __m128d, __m128d, __m128h, 8) test_2 (_mm_cvt_roundss_sh, __m128h, __m128h, __m128, 8) test_2 (_mm_cvt_roundsd_sh, __m128h, __m128h, __m128d, 8) +test_2 (_mm512_fmul_round_pch, __m512h, __m512h, __m512h, 8) +test_2 (_mm512_fcmul_round_pch, __m512h, __m512h, __m512h, 8) test_2x (_mm512_cmp_round_ph_mask, __mmask32, __m512h, __m512h, 1, 8) test_2x (_mm_cmp_round_sh_mask, __mmask8, __m128h, __m128h, 1, 8) test_2x (_mm_comi_round_sh, int, __m128h, __m128h, 1, 8) @@ -949,6 +951,10 @@ test_3 (_mm_fmadd_round_sh, __m128h, __m128h, __m128h, __m128h, 9) test_3 (_mm_fnmadd_round_sh, __m128h, __m128h, __m128h, __m128h, 9) test_3 (_mm_fmsub_round_sh, __m128h, __m128h, __m128h, __m128h, 9) test_3 (_mm_fnmsub_round_sh, __m128h, __m128h, __m128h, __m128h, 9) +test_3 (_mm512_fmadd_round_pch, __m512h, __m512h, __m512h, __m512h, 8) +test_3 (_mm512_fcmadd_round_pch, __m512h, __m512h, __m512h, __m512h, 8) +test_3 (_mm512_maskz_fmul_round_pch, __m512h, __mmask16, __m512h, __m512h, 8) +test_3 (_mm512_maskz_fcmul_round_pch, __m512h, __mmask16, __m512h, __m512h, 8) test_3x (_mm512_mask_cmp_round_ph_mask, __mmask32, __mmask32, __m512h, __m512h, 1, 8) test_3x (_mm_mask_cmp_round_sh_mask, __mmask8, __mmask8, __m128h, __m128h, 1, 8) test_3x (_mm512_mask_reduce_round_ph, __m512h, __m512h, __mmask32, __m512h, 123, 8) @@ -1010,6 +1016,14 @@ test_4 (_mm_maskz_fmsub_round_sh, __m128h, __mmask8, __m128h, __m128h, __m128h, test_4 (_mm_mask_fnmsub_round_sh, __m128h, __m128h, __mmask8, __m128h, __m128h, 9) test_4 (_mm_mask3_fnmsub_round_sh, __m128h, __m128h, __m128h, __m128h, __mmask8, 9) test_4 (_mm_maskz_fnmsub_round_sh, __m128h, __mmask8, __m128h, __m128h, __m128h, 9) +test_4 (_mm512_mask_fmadd_round_pch, __m512h, __m512h, __mmask16, __m512h, __m512h, 8) +test_4 (_mm512_mask_fcmadd_round_pch, __m512h, __m512h, __mmask16, __m512h, __m512h, 8) +test_4 (_mm512_mask3_fmadd_round_pch, __m512h, __m512h, __m512h, __m512h, __mmask16, 8) +test_4 (_mm512_mask3_fcmadd_round_pch, __m512h, __m512h, __m512h, __m512h, __mmask16, 8) +test_4 (_mm512_maskz_fmadd_round_pch, __m512h, __mmask16, __m512h, __m512h, __m512h, 8) +test_4 (_mm512_maskz_fcmadd_round_pch, __m512h, __mmask16, __m512h, __m512h, __m512h, 8) +test_4 (_mm512_mask_fmul_round_pch, __m512h, __m512h, __mmask16, __m512h, __m512h, 8) +test_4 (_mm512_mask_fcmul_round_pch, __m512h, __m512h, __mmask16, __m512h, __m512h, 8) test_4x (_mm_mask_reduce_round_sh, __m128h, __m128h, __mmask8, __m128h, __m128h, 123, 8) test_4x (_mm_mask_roundscale_round_sh, __m128h, __m128h, __mmask8, __m128h, __m128h, 123, 8) test_4x (_mm_mask_getmant_sh, __m128h, __m128h, __mmask8, __m128h, __m128h, 1, 1) diff --git a/gcc/testsuite/gcc.target/i386/sse-23.c b/gcc/testsuite/gcc.target/i386/sse-23.c index caf14408b91..dc39d7e2012 100644 --- a/gcc/testsuite/gcc.target/i386/sse-23.c +++ b/gcc/testsuite/gcc.target/i386/sse-23.c @@ -805,6 +805,16 @@ #define __builtin_ia32_vfnmsubsh3_mask(A, B, C, D, E) __builtin_ia32_vfnmsubsh3_mask(A, B, C, D, 8) #define __builtin_ia32_vfnmsubsh3_mask3(A, B, C, D, E) __builtin_ia32_vfnmsubsh3_mask3(A, B, C, D, 8) #define __builtin_ia32_vfnmsubsh3_maskz(A, B, C, D, E) __builtin_ia32_vfnmsubsh3_maskz(A, B, C, D, 8) +#define __builtin_ia32_vfcmaddcph_v32hf_round(A, B, C, D) __builtin_ia32_vfcmaddcph_v32hf_round(A, B, C, 8) +#define __builtin_ia32_vfcmaddcph_v32hf_mask_round(A, C, D, B, E) __builtin_ia32_vfcmaddcph_v32hf_mask_round(A, C, D, B, 8) +#define __builtin_ia32_vfcmaddcph_v32hf_maskz_round(B, C, D, A, E) __builtin_ia32_vfcmaddcph_v32hf_maskz_round(B, C, D, A, 8) +#define __builtin_ia32_vfmaddcph_v32hf_round(A, B, C, D) __builtin_ia32_vfmaddcph_v32hf_round(A, B, C, 8) +#define __builtin_ia32_vfmaddcph_v32hf_mask_round(A, C, D, B, E) __builtin_ia32_vfmaddcph_v32hf_mask_round(A, C, D, B, 8) +#define __builtin_ia32_vfmaddcph_v32hf_maskz_round(B, C, D, A, E) __builtin_ia32_vfmaddcph_v32hf_maskz_round(B, C, D, A, 8) +#define __builtin_ia32_vfmulcph_v32hf_round(A, B, C) __builtin_ia32_vfmulcph_v32hf_round(A, B, 8) +#define __builtin_ia32_vfmulcph_v32hf_mask_round(A, C, D, B, E) __builtin_ia32_vfmulcph_v32hf_mask_round(A, C, D, B, 8) +#define __builtin_ia32_vfcmulcph_v32hf_round(A, B, C) __builtin_ia32_vfcmulcph_v32hf_round(A, B, 8) +#define __builtin_ia32_vfcmulcph_v32hf_mask_round(A, C, D, B, E) __builtin_ia32_vfcmulcph_v32hf_mask_round(A, C, D, B, 8) /* avx512fp16vlintrin.h */ #define __builtin_ia32_vcmpph_v8hf_mask(A, B, C, D) __builtin_ia32_vcmpph_v8hf_mask(A, B, 1, D)