diff --git a/gcc/config/arc/simdext.md b/gcc/config/arc/simdext.md
index d142aacd7dc..41c42690633 100644
--- a/gcc/config/arc/simdext.md
+++ b/gcc/config/arc/simdext.md
@@ -174,7 +174,7 @@ (define_insn "vld128_insn"
 							  (parallel [(match_operand:SI 2 "immediate_operand" "L")])))
 			   (match_operand:SI 3 "immediate_operand" "P"))))]
  "TARGET_SIMD_SET"
- "vld128 %0, [i%2, %3]"
+ "vld128\\t%0,[i%2,%3]"
  [(set_attr "type" "simd_vload128")
   (set_attr "length" "4")
   (set_attr "cond" "nocond")]
@@ -186,7 +186,7 @@ (define_insn "vst128_insn"
 			   (match_operand:SI 2 "immediate_operand" "P")))
 	(match_operand:V8HI 3 "vector_register_operand" "=v"))]
  "TARGET_SIMD_SET"
- "vst128 %3, [i%1, %2]"
+ "vst128\\t%3,[i%1,%2]"
  [(set_attr "type" "simd_vstore")
   (set_attr "length" "4")
   (set_attr "cond" "nocond")]
@@ -204,7 +204,7 @@ (define_insn "vst64_insn"
 	 (match_operand:V8HI 3 "vector_register_operand" "=v")
 	 (parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3)])))]
  "TARGET_SIMD_SET"
- "vst64 %3, [i%1, %2]"
+ "vst64\\t%3,[i%1,%2]"
  [(set_attr "type" "simd_vstore")
   (set_attr "length" "4")
   (set_attr "cond" "nocond")]
@@ -215,9 +215,9 @@ (define_insn "movv8hi_insn"
 	(match_operand:V8HI 1 "vector_register_or_memory_operand" "m,v,v"))]
   "TARGET_SIMD_SET && !(GET_CODE (operands[0]) == MEM && GET_CODE(operands[1]) == MEM)"
   "@
-    vld128r %0, %1
-    vst128r %1, %0
-    vmvzw %0,%1,0xffff"
+    vld128r\\t%0,%1
+    vst128r\\t%1,%0
+    vmvzw\\t%0,%1,0xffff"
   [(set_attr "type" "simd_vload128,simd_vstore,simd_vmove_else_zero")
    (set_attr "length" "8,8,4")
    (set_attr "cond" "nocond, nocond, nocond")])
@@ -227,55 +227,21 @@ (define_insn "movti_insn"
 	(match_operand:TI 1 "vector_register_or_memory_operand" "m,v,v"))]
   ""
   "@
-    vld128r %0, %1
-    vst128r %1, %0
-    vmvzw %0,%1,0xffff"
+    vld128r\\t%0,%1
+    vst128r\\t%1,%0
+    vmvzw\\t%0,%1,0xffff"
   [(set_attr "type" "simd_vload128,simd_vstore,simd_vmove_else_zero")
    (set_attr "length" "8,8,4")
    (set_attr "cond" "nocond, nocond, nocond")])
 
-;; (define_insn "*movv8hi_insn_rr"
-;;   [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
-;; 	(match_operand:V8HI 1 "vector_register_operand" "v"))]
-;;   ""
-;;   "mov reg,reg"
-;;   [(set_attr "length" "8")
-;;   (set_attr "type" "move")])
-
-;; (define_insn "*movv8_out"
-;;   [(set (match_operand:V8HI 0 "memory_operand" "=m")
-;; 	(match_operand:V8HI 1 "vector_register_operand" "v"))]
-;;   ""
-;;   "mov out"
-;;   [(set_attr "length" "8")
-;;   (set_attr "type" "move")])
-
-
-;; (define_insn "addv8hi3"
-;;   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
-;; 	(plus:V8HI (match_operand:V8HI 1 "vector_register_operand"  "v")
-;; 		   (match_operand:V8HI 2 "vector_register_operand" "v")))]
-;;   "TARGET_SIMD_SET"
-;;   "vaddw %0, %1, %2"
-;;   [(set_attr "length" "8")
-;;    (set_attr "cond" "nocond")])
-
-;; (define_insn "vaddw_insn"
-;;   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
-;; 	(unspec [(match_operand:V8HI 1 "vector_register_operand"  "v")
-;; 			 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VADDW))]
-;;   "TARGET_SIMD_SET"
-;;   "vaddw %0, %1, %2"
-;;   [(set_attr "length" "8")
-;;    (set_attr "cond" "nocond")])
-
 ;; V V V Insns
 (define_insn "vaddaw_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-			 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VADDAW))]
+		      (match_operand:V8HI 2 "vector_register_operand" "v")]
+		     UNSPEC_ARC_SIMD_VADDAW))]
   "TARGET_SIMD_SET"
-  "vaddaw %0, %1, %2"
+  "vaddaw\\t%0,%1,%2"
   [(set_attr "type" "simd_varith_with_acc")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -283,9 +249,10 @@ (define_insn "vaddaw_insn"
 (define_insn "vaddw_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-			 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VADDW))]
+		      (match_operand:V8HI 2 "vector_register_operand" "v")]
+		     UNSPEC_ARC_SIMD_VADDW))]
   "TARGET_SIMD_SET"
-  "vaddw %0, %1, %2"
+  "vaddw\\t%0,%1,2"
   [(set_attr "type" "simd_varith_1cycle")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -293,9 +260,10 @@ (define_insn "vaddw_insn"
 (define_insn "vavb_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-			 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VAVB))]
+		      (match_operand:V8HI 2 "vector_register_operand" "v")]
+		     UNSPEC_ARC_SIMD_VAVB))]
   "TARGET_SIMD_SET"
-  "vavb %0, %1, %2"
+  "vavb\\t%0,%1,%2"
   [(set_attr "type" "simd_varith_1cycle")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -303,9 +271,10 @@ (define_insn "vavb_insn"
 (define_insn "vavrb_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-			 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VAVRB))]
+		      (match_operand:V8HI 2 "vector_register_operand" "v")]
+		     UNSPEC_ARC_SIMD_VAVRB))]
   "TARGET_SIMD_SET"
-  "vavrb %0, %1, %2"
+  "vavrb\\t%0,%1,%2"
   [(set_attr "type" "simd_varith_1cycle")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -313,9 +282,10 @@ (define_insn "vavrb_insn"
 (define_insn "vdifaw_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-			 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VDIFAW))]
+		      (match_operand:V8HI 2 "vector_register_operand" "v")]
+		     UNSPEC_ARC_SIMD_VDIFAW))]
   "TARGET_SIMD_SET"
-  "vdifaw %0, %1, %2"
+  "vdifaw\\t%0,%1,%2"
   [(set_attr "type" "simd_varith_with_acc")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -323,9 +293,10 @@ (define_insn "vdifaw_insn"
 (define_insn "vdifw_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-			 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VDIFW))]
+		      (match_operand:V8HI 2 "vector_register_operand" "v")]
+		     UNSPEC_ARC_SIMD_VDIFW))]
   "TARGET_SIMD_SET"
-  "vdifw %0, %1, %2"
+  "vdifw\\t%0,%1,%2"
   [(set_attr "type" "simd_varith_1cycle")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -333,9 +304,10 @@ (define_insn "vdifw_insn"
 (define_insn "vmaxaw_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-			 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMAXAW))]
+		      (match_operand:V8HI 2 "vector_register_operand" "v")]
+		     UNSPEC_ARC_SIMD_VMAXAW))]
   "TARGET_SIMD_SET"
-  "vmaxaw %0, %1, %2"
+  "vmaxaw\\t%0,%1,2"
   [(set_attr "type" "simd_varith_with_acc")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -343,9 +315,10 @@ (define_insn "vmaxaw_insn"
 (define_insn "vmaxw_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-			 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMAXW))]
+		      (match_operand:V8HI 2 "vector_register_operand" "v")]
+		     UNSPEC_ARC_SIMD_VMAXW))]
   "TARGET_SIMD_SET"
-  "vmaxw %0, %1, %2"
+  "vmaxw\\t%0,%1,%2"
   [(set_attr "type" "simd_varith_1cycle")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -353,9 +326,10 @@ (define_insn "vmaxw_insn"
 (define_insn "vminaw_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-			 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMINAW))]
+		      (match_operand:V8HI 2 "vector_register_operand" "v")]
+		     UNSPEC_ARC_SIMD_VMINAW))]
   "TARGET_SIMD_SET"
-  "vminaw %0, %1, %2"
+  "vminaw\\t%0,%1,%2"
   [(set_attr "type" "simd_varith_with_acc")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -363,9 +337,10 @@ (define_insn "vminaw_insn"
 (define_insn "vminw_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-			 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMINW))]
+		      (match_operand:V8HI 2 "vector_register_operand" "v")]
+		     UNSPEC_ARC_SIMD_VMINW))]
   "TARGET_SIMD_SET"
-  "vminw %0, %1, %2"
+  "vminw\\t%0,%1,%2"
   [(set_attr "type" "simd_varith_1cycle")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -373,9 +348,10 @@ (define_insn "vminw_insn"
 (define_insn "vmulaw_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-			 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMULAW))]
+		      (match_operand:V8HI 2 "vector_register_operand" "v")]
+		     UNSPEC_ARC_SIMD_VMULAW))]
   "TARGET_SIMD_SET"
-  "vmulaw %0, %1, %2"
+  "vmulaw\\t%0,%1,%2"
   [(set_attr "type" "simd_varith_with_acc")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -383,9 +359,10 @@ (define_insn "vmulaw_insn"
 (define_insn "vmulfaw_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-			 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMULFAW))]
+		      (match_operand:V8HI 2 "vector_register_operand" "v")]
+		     UNSPEC_ARC_SIMD_VMULFAW))]
   "TARGET_SIMD_SET"
-  "vmulfaw %0, %1, %2"
+  "vmulfaw\\t%0,%1,%2"
   [(set_attr "type" "simd_varith_with_acc")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -393,9 +370,10 @@ (define_insn "vmulfaw_insn"
 (define_insn "vmulfw_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-			 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMULFW))]
+		      (match_operand:V8HI 2 "vector_register_operand" "v")]
+		     UNSPEC_ARC_SIMD_VMULFW))]
   "TARGET_SIMD_SET"
-  "vmulfw %0, %1, %2"
+  "vmulfw\\t%0,%1,%2"
   [(set_attr "type" "simd_varith_2cycle")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -403,9 +381,10 @@ (define_insn "vmulfw_insn"
 (define_insn "vmulw_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-			 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMULW))]
+		      (match_operand:V8HI 2 "vector_register_operand" "v")]
+		     UNSPEC_ARC_SIMD_VMULW))]
   "TARGET_SIMD_SET"
-  "vmulw %0, %1, %2"
+  "vmulw\\t%0,%1,%2"
   [(set_attr "type" "simd_varith_2cycle")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -413,9 +392,10 @@ (define_insn "vmulw_insn"
 (define_insn "vsubaw_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-			 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VSUBAW))]
+		      (match_operand:V8HI 2 "vector_register_operand" "v")]
+		     UNSPEC_ARC_SIMD_VSUBAW))]
   "TARGET_SIMD_SET"
-  "vsubaw %0, %1, %2"
+  "vsubaw\\t%0,%1,%2"
   [(set_attr "type" "simd_varith_with_acc")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -423,9 +403,10 @@ (define_insn "vsubaw_insn"
 (define_insn "vsubw_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-			 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VSUBW))]
+		      (match_operand:V8HI 2 "vector_register_operand" "v")]
+		     UNSPEC_ARC_SIMD_VSUBW))]
   "TARGET_SIMD_SET"
-  "vsubw %0, %1, %2"
+  "vsubw\\t%0,%1,%2"
   [(set_attr "type" "simd_varith_1cycle")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -433,9 +414,10 @@ (define_insn "vsubw_insn"
 (define_insn "vsummw_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-			 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VSUMMW))]
+		      (match_operand:V8HI 2 "vector_register_operand" "v")]
+		     UNSPEC_ARC_SIMD_VSUMMW))]
   "TARGET_SIMD_SET"
-  "vsummw %0, %1, %2"
+  "vsummw\\t%0,%1,%2"
   [(set_attr "type" "simd_varith_2cycle")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -443,9 +425,10 @@ (define_insn "vsummw_insn"
 (define_insn "vand_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-			 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VAND))]
+		      (match_operand:V8HI 2 "vector_register_operand" "v")]
+		     UNSPEC_ARC_SIMD_VAND))]
   "TARGET_SIMD_SET"
-  "vand %0, %1, %2"
+  "vand\\t%0,%1,%2"
   [(set_attr "type" "simd_vlogic")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -453,9 +436,10 @@ (define_insn "vand_insn"
 (define_insn "vandaw_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-			 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VANDAW))]
+		      (match_operand:V8HI 2 "vector_register_operand" "v")]
+		     UNSPEC_ARC_SIMD_VANDAW))]
   "TARGET_SIMD_SET"
-  "vandaw %0, %1, %2"
+  "vandaw\\t%0,%1,%2"
   [(set_attr "type" "simd_vlogic_with_acc")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -463,9 +447,10 @@ (define_insn "vandaw_insn"
 (define_insn "vbic_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-			 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VBIC))]
+		      (match_operand:V8HI 2 "vector_register_operand" "v")]
+		     UNSPEC_ARC_SIMD_VBIC))]
   "TARGET_SIMD_SET"
-  "vbic %0, %1, %2"
+  "vbic\\t%0,%1,%2"
   [(set_attr "type" "simd_vlogic")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -473,9 +458,10 @@ (define_insn "vbic_insn"
 (define_insn "vbicaw_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-			 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VBICAW))]
+		      (match_operand:V8HI 2 "vector_register_operand" "v")]
+		     UNSPEC_ARC_SIMD_VBICAW))]
   "TARGET_SIMD_SET"
-  "vbicaw %0, %1, %2"
+  "vbicaw\\t%0,%1,%2"
   [(set_attr "type" "simd_vlogic_with_acc")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -483,9 +469,10 @@ (define_insn "vbicaw_insn"
 (define_insn "vor_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-			 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VOR))]
+		      (match_operand:V8HI 2 "vector_register_operand" "v")]
+		     UNSPEC_ARC_SIMD_VOR))]
   "TARGET_SIMD_SET"
-  "vor %0, %1, %2"
+  "vor\\t%0,%1,%2"
   [(set_attr "type" "simd_vlogic")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -493,9 +480,10 @@ (define_insn "vor_insn"
 (define_insn "vxor_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-			 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VXOR))]
+		      (match_operand:V8HI 2 "vector_register_operand" "v")]
+		     UNSPEC_ARC_SIMD_VXOR))]
   "TARGET_SIMD_SET"
-  "vxor %0, %1, %2"
+  "vxor\\t%0,%1,%2"
   [(set_attr "type" "simd_vlogic")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -503,9 +491,10 @@ (define_insn "vxor_insn"
 (define_insn "vxoraw_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-			 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VXORAW))]
+		      (match_operand:V8HI 2 "vector_register_operand" "v")]
+		     UNSPEC_ARC_SIMD_VXORAW))]
   "TARGET_SIMD_SET"
-  "vxoraw %0, %1, %2"
+  "vxoraw\\t%0,%1,%2"
   [(set_attr "type" "simd_vlogic_with_acc")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -513,9 +502,10 @@ (define_insn "vxoraw_insn"
 (define_insn "veqw_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-			 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VEQW))]
+		      (match_operand:V8HI 2 "vector_register_operand" "v")]
+		     UNSPEC_ARC_SIMD_VEQW))]
   "TARGET_SIMD_SET"
-  "veqw %0, %1, %2"
+  "veqw\\t%0,%1,%2"
   [(set_attr "type" "simd_vcompare")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -523,9 +513,10 @@ (define_insn "veqw_insn"
 (define_insn "vlew_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-			 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VLEW))]
+		      (match_operand:V8HI 2 "vector_register_operand" "v")]
+		     UNSPEC_ARC_SIMD_VLEW))]
   "TARGET_SIMD_SET"
-  "vlew %0, %1, %2"
+  "vlew\\t%0,%1,%2"
   [(set_attr "type" "simd_vcompare")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -533,9 +524,10 @@ (define_insn "vlew_insn"
 (define_insn "vltw_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-			 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VLTW))]
+		      (match_operand:V8HI 2 "vector_register_operand" "v")]
+		     UNSPEC_ARC_SIMD_VLTW))]
   "TARGET_SIMD_SET"
-  "vltw %0, %1, %2"
+  "vltw\\t%0,%1,%2"
   [(set_attr "type" "simd_vcompare")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -543,9 +535,10 @@ (define_insn "vltw_insn"
 (define_insn "vnew_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-			 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VNEW))]
+		      (match_operand:V8HI 2 "vector_register_operand" "v")]
+		     UNSPEC_ARC_SIMD_VNEW))]
   "TARGET_SIMD_SET"
-  "vnew %0, %1, %2"
+  "vnew\\t%0,%1,%2"
   [(set_attr "type" "simd_vcompare")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -553,9 +546,10 @@ (define_insn "vnew_insn"
 (define_insn "vmr1aw_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-			 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR1AW))]
+		      (match_operand:V8HI 2 "vector_register_operand" "v")]
+		     UNSPEC_ARC_SIMD_VMR1AW))]
   "TARGET_SIMD_SET"
-  "vmr1aw %0, %1, %2"
+  "vmr1aw\\t%0,%1,%2"
   [(set_attr "type" "simd_valign_with_acc")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -563,9 +557,10 @@ (define_insn "vmr1aw_insn"
 (define_insn "vmr1w_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-			 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR1W))]
+		      (match_operand:V8HI 2 "vector_register_operand" "v")]
+		     UNSPEC_ARC_SIMD_VMR1W))]
   "TARGET_SIMD_SET"
-  "vmr1w %0, %1, %2"
+  "vmr1w\\t%0,%1,%2"
   [(set_attr "type" "simd_valign")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -573,9 +568,10 @@ (define_insn "vmr1w_insn"
 (define_insn "vmr2aw_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-			 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR2AW))]
+		      (match_operand:V8HI 2 "vector_register_operand" "v")]
+		     UNSPEC_ARC_SIMD_VMR2AW))]
   "TARGET_SIMD_SET"
-  "vmr2aw %0, %1, %2"
+  "vmr2aw\\t%0,%1,%2"
   [(set_attr "type" "simd_valign_with_acc")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -583,9 +579,10 @@ (define_insn "vmr2aw_insn"
 (define_insn "vmr2w_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-			 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR2W))]
+		      (match_operand:V8HI 2 "vector_register_operand" "v")]
+		     UNSPEC_ARC_SIMD_VMR2W))]
   "TARGET_SIMD_SET"
-  "vmr2w %0, %1, %2"
+  "vmr2w\\t%0,%1,%2"
   [(set_attr "type" "simd_valign")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -593,9 +590,10 @@ (define_insn "vmr2w_insn"
 (define_insn "vmr3aw_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-			 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR3AW))]
+		      (match_operand:V8HI 2 "vector_register_operand" "v")]
+		     UNSPEC_ARC_SIMD_VMR3AW))]
   "TARGET_SIMD_SET"
-  "vmr3aw %0, %1, %2"
+  "vmr3aw\\t%0,%1,%2"
   [(set_attr "type" "simd_valign_with_acc")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -603,9 +601,10 @@ (define_insn "vmr3aw_insn"
 (define_insn "vmr3w_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-			 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR3W))]
+		      (match_operand:V8HI 2 "vector_register_operand" "v")]
+		     UNSPEC_ARC_SIMD_VMR3W))]
   "TARGET_SIMD_SET"
-  "vmr3w %0, %1, %2"
+  "vmr3w\\t%0,%1,%2"
   [(set_attr "type" "simd_valign")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -613,9 +612,10 @@ (define_insn "vmr3w_insn"
 (define_insn "vmr4aw_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-			 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR4AW))]
+		      (match_operand:V8HI 2 "vector_register_operand" "v")]
+		     UNSPEC_ARC_SIMD_VMR4AW))]
   "TARGET_SIMD_SET"
-  "vmr4aw %0, %1, %2"
+  "vmr4aw\\t%0,%1,%2"
   [(set_attr "type" "simd_valign_with_acc")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -623,9 +623,10 @@ (define_insn "vmr4aw_insn"
 (define_insn "vmr4w_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-			 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR4W))]
+		      (match_operand:V8HI 2 "vector_register_operand" "v")]
+		     UNSPEC_ARC_SIMD_VMR4W))]
   "TARGET_SIMD_SET"
-  "vmr4w %0, %1, %2"
+  "vmr4w\\t%0,%1,%2"
   [(set_attr "type" "simd_valign")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -633,9 +634,10 @@ (define_insn "vmr4w_insn"
 (define_insn "vmr5aw_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-			 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR5AW))]
+		      (match_operand:V8HI 2 "vector_register_operand" "v")]
+		     UNSPEC_ARC_SIMD_VMR5AW))]
   "TARGET_SIMD_SET"
-  "vmr5aw %0, %1, %2"
+  "vmr5aw\\t%0,%1,%2"
   [(set_attr "type" "simd_valign_with_acc")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -643,9 +645,10 @@ (define_insn "vmr5aw_insn"
 (define_insn "vmr5w_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-			 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR5W))]
+		      (match_operand:V8HI 2 "vector_register_operand" "v")]
+		     UNSPEC_ARC_SIMD_VMR5W))]
   "TARGET_SIMD_SET"
-  "vmr5w %0, %1, %2"
+  "vmr5w\\t%0,%1,%2"
   [(set_attr "type" "simd_valign")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -653,9 +656,10 @@ (define_insn "vmr5w_insn"
 (define_insn "vmr6aw_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-			 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR6AW))]
+		      (match_operand:V8HI 2 "vector_register_operand" "v")]
+		     UNSPEC_ARC_SIMD_VMR6AW))]
   "TARGET_SIMD_SET"
-  "vmr6aw %0, %1, %2"
+  "vmr6aw\\t%0,%1,%2"
   [(set_attr "type" "simd_valign_with_acc")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -663,9 +667,10 @@ (define_insn "vmr6aw_insn"
 (define_insn "vmr6w_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-			 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR6W))]
+		      (match_operand:V8HI 2 "vector_register_operand" "v")]
+		     UNSPEC_ARC_SIMD_VMR6W))]
   "TARGET_SIMD_SET"
-  "vmr6w %0, %1, %2"
+  "vmr6w\\t%0,%1,%2"
   [(set_attr "type" "simd_valign")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -673,9 +678,10 @@ (define_insn "vmr6w_insn"
 (define_insn "vmr7aw_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-			 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR7AW))]
+		      (match_operand:V8HI 2 "vector_register_operand" "v")]
+		     UNSPEC_ARC_SIMD_VMR7AW))]
   "TARGET_SIMD_SET"
-  "vmr7aw %0, %1, %2"
+  "vmr7aw\\t%0,%1,%2"
   [(set_attr "type" "simd_valign_with_acc")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -683,9 +689,10 @@ (define_insn "vmr7aw_insn"
 (define_insn "vmr7w_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-			 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR7W))]
+		      (match_operand:V8HI 2 "vector_register_operand" "v")]
+		     UNSPEC_ARC_SIMD_VMR7W))]
   "TARGET_SIMD_SET"
-  "vmr7w %0, %1, %2"
+  "vmr7w\\t%0,%1,%2"
   [(set_attr "type" "simd_valign")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -693,9 +700,10 @@ (define_insn "vmr7w_insn"
 (define_insn "vmrb_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-			 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMRB))]
+		      (match_operand:V8HI 2 "vector_register_operand" "v")]
+		     UNSPEC_ARC_SIMD_VMRB))]
   "TARGET_SIMD_SET"
-  "vmrb %0, %1, %2"
+  "vmrb\\t%0,%1,%2"
   [(set_attr "type" "simd_valign")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -703,9 +711,10 @@ (define_insn "vmrb_insn"
 (define_insn "vh264f_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-			 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VH264F))]
+		      (match_operand:V8HI 2 "vector_register_operand" "v")]
+		     UNSPEC_ARC_SIMD_VH264F))]
   "TARGET_SIMD_SET"
-  "vh264f %0, %1, %2"
+  "vh264f\\t%0,%1,%2"
   [(set_attr "type" "simd_vspecial_3cycle")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -713,9 +722,10 @@ (define_insn "vh264f_insn"
 (define_insn "vh264ft_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-			 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VH264FT))]
+		      (match_operand:V8HI 2 "vector_register_operand" "v")]
+		     UNSPEC_ARC_SIMD_VH264FT))]
   "TARGET_SIMD_SET"
-  "vh264ft %0, %1, %2"
+  "vh264ft\\t%0,%1,%2"
   [(set_attr "type" "simd_vspecial_3cycle")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -723,9 +733,10 @@ (define_insn "vh264ft_insn"
 (define_insn "vh264fw_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-			 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VH264FW))]
+		      (match_operand:V8HI 2 "vector_register_operand" "v")]
+		     UNSPEC_ARC_SIMD_VH264FW))]
   "TARGET_SIMD_SET"
-  "vh264fw %0, %1, %2"
+  "vh264fw\\t%0,%1,%2"
   [(set_attr "type" "simd_vspecial_3cycle")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -733,9 +744,10 @@ (define_insn "vh264fw_insn"
 (define_insn "vvc1f_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-			 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VVC1F))]
+		      (match_operand:V8HI 2 "vector_register_operand" "v")]
+		     UNSPEC_ARC_SIMD_VVC1F))]
   "TARGET_SIMD_SET"
-  "vvc1f %0, %1, %2"
+  "vvc1f\\t%0,%1,%2"
   [(set_attr "type" "simd_vspecial_3cycle")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -743,9 +755,10 @@ (define_insn "vvc1f_insn"
 (define_insn "vvc1ft_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-			 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VVC1FT))]
+		      (match_operand:V8HI 2 "vector_register_operand" "v")]
+		     UNSPEC_ARC_SIMD_VVC1FT))]
   "TARGET_SIMD_SET"
-  "vvc1ft %0, %1, %2"
+  "vvc1ft\\t%0,%1,%2"
   [(set_attr "type" "simd_vspecial_3cycle")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -754,22 +767,13 @@ (define_insn "vvc1ft_insn"
 
 ;;---
 ;; V V r/limm Insns
-
-;; (define_insn "vbaddw_insn"
-;;   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
-;; 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-;; 			      (match_operand:SI 2 "nonmemory_operand" "rCal")] UNSPEC_ARC_SIMD_VBADDW))]
-;;   "TARGET_SIMD_SET"
-;;   "vbaddw %0, %1, %2"
-;;   [(set_attr "length" "4")
-;;    (set_attr "cond" "nocond")])
-
 (define_insn "vbaddw_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-		      (match_operand:SI 2 "nonmemory_operand" "r")] UNSPEC_ARC_SIMD_VBADDW))]
+		      (match_operand:SI 2 "nonmemory_operand" "r")]
+		     UNSPEC_ARC_SIMD_VBADDW))]
   "TARGET_SIMD_SET"
-  "vbaddw %0, %1, %2"
+  "vbaddw\\t%0,%1,%2"
   [(set_attr "type" "simd_varith_1cycle")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -777,9 +781,10 @@ (define_insn "vbaddw_insn"
 (define_insn "vbmaxw_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-		      (match_operand:SI 2 "nonmemory_operand" "r")] UNSPEC_ARC_SIMD_VBMAXW))]
+		      (match_operand:SI 2 "nonmemory_operand" "r")]
+		     UNSPEC_ARC_SIMD_VBMAXW))]
   "TARGET_SIMD_SET"
-  "vbmaxw %0, %1, %2"
+  "vbmaxw\\t%0,%1,%2"
   [(set_attr "type" "simd_varith_1cycle")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -787,9 +792,10 @@ (define_insn "vbmaxw_insn"
 (define_insn "vbminw_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-		      (match_operand:SI 2 "nonmemory_operand" "r")] UNSPEC_ARC_SIMD_VBMINW))]
+		      (match_operand:SI 2 "nonmemory_operand" "r")]
+		     UNSPEC_ARC_SIMD_VBMINW))]
   "TARGET_SIMD_SET"
-  "vbminw %0, %1, %2"
+  "vbminw\\t%0,%1,%2"
   [(set_attr "type" "simd_varith_1cycle")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -797,9 +803,10 @@ (define_insn "vbminw_insn"
 (define_insn "vbmulaw_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-		      (match_operand:SI 2 "nonmemory_operand" "r")] UNSPEC_ARC_SIMD_VBMULAW))]
+		      (match_operand:SI 2 "nonmemory_operand" "r")]
+		     UNSPEC_ARC_SIMD_VBMULAW))]
   "TARGET_SIMD_SET"
-  "vbmulaw %0, %1, %2"
+  "vbmulaw\\t%0,%1,%2"
   [(set_attr "type" "simd_varith_with_acc")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -807,9 +814,10 @@ (define_insn "vbmulaw_insn"
 (define_insn "vbmulfw_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-		      (match_operand:SI 2 "nonmemory_operand" "r")] UNSPEC_ARC_SIMD_VBMULFW))]
+		      (match_operand:SI 2 "nonmemory_operand" "r")]
+		     UNSPEC_ARC_SIMD_VBMULFW))]
   "TARGET_SIMD_SET"
-  "vbmulfw %0, %1, %2"
+  "vbmulfw\\t%0,%1,%2"
   [(set_attr "type" "simd_varith_2cycle")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -817,9 +825,10 @@ (define_insn "vbmulfw_insn"
 (define_insn "vbmulw_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-		      (match_operand:SI 2 "nonmemory_operand" "r")] UNSPEC_ARC_SIMD_VBMULW))]
+		      (match_operand:SI 2 "nonmemory_operand" "r")]
+		     UNSPEC_ARC_SIMD_VBMULW))]
   "TARGET_SIMD_SET"
-  "vbmulw %0, %1, %2"
+  "vbmulw\\t%0,%1,%2"
   [(set_attr "type" "simd_varith_2cycle")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -827,9 +836,10 @@ (define_insn "vbmulw_insn"
 (define_insn "vbrsubw_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-		     (match_operand:SI 2 "nonmemory_operand" "r")] UNSPEC_ARC_SIMD_VBRSUBW))]
+		      (match_operand:SI 2 "nonmemory_operand" "r")]
+		     UNSPEC_ARC_SIMD_VBRSUBW))]
   "TARGET_SIMD_SET"
-  "vbrsubw %0, %1, %2"
+  "vbrsubw\\t%0,%1,%2"
   [(set_attr "type" "simd_varith_1cycle")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -837,9 +847,10 @@ (define_insn "vbrsubw_insn"
 (define_insn "vbsubw_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-		      (match_operand:SI 2 "nonmemory_operand" "r")] UNSPEC_ARC_SIMD_VBSUBW))]
+		      (match_operand:SI 2 "nonmemory_operand" "r")]
+		     UNSPEC_ARC_SIMD_VBSUBW))]
   "TARGET_SIMD_SET"
-  "vbsubw %0, %1, %2"
+  "vbsubw\\t%0,%1,%2"
   [(set_attr "type" "simd_varith_1cycle")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -849,9 +860,10 @@ (define_insn "vbsubw_insn"
 (define_insn "vasrrwi_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-		      (match_operand:SI 2 "immediate_operand" "L")] UNSPEC_ARC_SIMD_VASRRWi))]
+		      (match_operand:SI 2 "immediate_operand" "L")]
+		     UNSPEC_ARC_SIMD_VASRRWi))]
   "TARGET_SIMD_SET"
-  "vasrrwi %0, %1, %2"
+  "vasrrwi\\t%0,%1,%2"
   [(set_attr "type" "simd_varith_2cycle")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -859,9 +871,10 @@ (define_insn "vasrrwi_insn"
 (define_insn "vasrsrwi_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-		     (match_operand:SI 2 "immediate_operand" "L")] UNSPEC_ARC_SIMD_VASRSRWi))]
+		      (match_operand:SI 2 "immediate_operand" "L")]
+		     UNSPEC_ARC_SIMD_VASRSRWi))]
   "TARGET_SIMD_SET"
-  "vasrsrwi %0, %1, %2"
+  "vasrsrwi\\t%0,%1,%2"
   [(set_attr "type" "simd_varith_2cycle")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -869,9 +882,10 @@ (define_insn "vasrsrwi_insn"
 (define_insn "vasrwi_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-		      (match_operand:SI 2 "immediate_operand" "L")] UNSPEC_ARC_SIMD_VASRWi))]
+		      (match_operand:SI 2 "immediate_operand" "L")]
+		     UNSPEC_ARC_SIMD_VASRWi))]
   "TARGET_SIMD_SET"
-  "vasrwi %0, %1, %2"
+  "vasrwi\\t%0,%1,%2"
   [(set_attr "type" "simd_varith_1cycle")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -879,9 +893,10 @@ (define_insn "vasrwi_insn"
 (define_insn "vasrpwbi_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-		      (match_operand:SI 2 "immediate_operand" "L")] UNSPEC_ARC_SIMD_VASRPWBi))]
+		      (match_operand:SI 2 "immediate_operand" "L")]
+		     UNSPEC_ARC_SIMD_VASRPWBi))]
   "TARGET_SIMD_SET"
-  "vasrpwbi %0, %1, %2"
+  "vasrpwbi\\t%0,%1,%2"
   [(set_attr "type" "simd_vpack")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -889,9 +904,10 @@ (define_insn "vasrpwbi_insn"
 (define_insn "vasrrpwbi_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-		      (match_operand:SI 2 "immediate_operand" "L")] UNSPEC_ARC_SIMD_VASRRPWBi))]
+		      (match_operand:SI 2 "immediate_operand" "L")]
+		     UNSPEC_ARC_SIMD_VASRRPWBi))]
   "TARGET_SIMD_SET"
-  "vasrrpwbi %0, %1, %2"
+  "vasrrpwbi\\t%0,%1,%2"
   [(set_attr "type" "simd_vpack")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -899,9 +915,10 @@ (define_insn "vasrrpwbi_insn"
 (define_insn "vsr8awi_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-		      (match_operand:SI 2 "immediate_operand" "L")] UNSPEC_ARC_SIMD_VSR8AWi))]
+		      (match_operand:SI 2 "immediate_operand" "L")]
+		     UNSPEC_ARC_SIMD_VSR8AWi))]
   "TARGET_SIMD_SET"
-  "vsr8awi %0, %1, %2"
+  "vsr8awi\\t%0,%1,%2"
   [(set_attr "type" "simd_valign_with_acc")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -909,9 +926,10 @@ (define_insn "vsr8awi_insn"
 (define_insn "vsr8i_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-		      (match_operand:SI 2 "immediate_operand" "L")] UNSPEC_ARC_SIMD_VSR8i))]
+		      (match_operand:SI 2 "immediate_operand" "L")]
+		     UNSPEC_ARC_SIMD_VSR8i))]
   "TARGET_SIMD_SET"
-  "vsr8i %0, %1, %2"
+  "vsr8i\\t%0,%1,%2"
   [(set_attr "type" "simd_valign")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -921,9 +939,10 @@ (define_insn "vsr8i_insn"
 (define_insn "vmvaw_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-		      (match_operand:SI 2 "immediate_operand" "P")] UNSPEC_ARC_SIMD_VMVAW))]
+		      (match_operand:SI 2 "immediate_operand" "P")]
+		     UNSPEC_ARC_SIMD_VMVAW))]
   "TARGET_SIMD_SET"
-  "vmvaw %0, %1, %2"
+  "vmvaw\\t%0,%1,%2"
   [(set_attr "type" "simd_vmove_with_acc")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -931,9 +950,10 @@ (define_insn "vmvaw_insn"
 (define_insn "vmvw_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-		      (match_operand:SI 2 "immediate_operand" "P")] UNSPEC_ARC_SIMD_VMVW))]
+		      (match_operand:SI 2 "immediate_operand" "P")]
+		     UNSPEC_ARC_SIMD_VMVW))]
   "TARGET_SIMD_SET"
-  "vmvw %0, %1, %2"
+  "vmvw\\t%0,%1,%2"
   [(set_attr "type" "simd_vmove")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -941,9 +961,10 @@ (define_insn "vmvw_insn"
 (define_insn "vmvzw_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-		      (match_operand:SI 2 "immediate_operand" "P")] UNSPEC_ARC_SIMD_VMVZW))]
+		      (match_operand:SI 2 "immediate_operand" "P")]
+		     UNSPEC_ARC_SIMD_VMVZW))]
   "TARGET_SIMD_SET"
-  "vmvzw %0, %1, %2"
+  "vmvzw\\t%0,%1,%2"
   [(set_attr "type" "simd_vmove_else_zero")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -951,9 +972,10 @@ (define_insn "vmvzw_insn"
 (define_insn "vd6tapf_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
-		      (match_operand:SI 2 "immediate_operand" "P")] UNSPEC_ARC_SIMD_VD6TAPF))]
+		      (match_operand:SI 2 "immediate_operand" "P")]
+		     UNSPEC_ARC_SIMD_VD6TAPF))]
   "TARGET_SIMD_SET"
-  "vd6tapf %0, %1, %2"
+  "vd6tapf\\t%0,%1,%2"
   [(set_attr "type" "simd_vspecial_4cycle")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -962,9 +984,10 @@ (define_insn "vd6tapf_insn"
 (define_insn "vmovaw_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:SI 1 "nonmemory_operand"  "r")
-		      (match_operand:SI 2 "immediate_operand" "P")] UNSPEC_ARC_SIMD_VMOVAW))]
+		      (match_operand:SI 2 "immediate_operand" "P")]
+		     UNSPEC_ARC_SIMD_VMOVAW))]
   "TARGET_SIMD_SET"
-  "vmovaw %0, %1, %2"
+  "vmovaw\\t%0,%1,%2"
   [(set_attr "type" "simd_vmove_with_acc")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -972,9 +995,10 @@ (define_insn "vmovaw_insn"
 (define_insn "vmovw_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:SI 1 "nonmemory_operand"  "r")
-		      (match_operand:SI 2 "immediate_operand" "P")] UNSPEC_ARC_SIMD_VMOVW))]
+		      (match_operand:SI 2 "immediate_operand" "P")]
+		     UNSPEC_ARC_SIMD_VMOVW))]
   "TARGET_SIMD_SET"
-  "vmovw %0, %1, %2"
+  "vmovw\\t%0,%1,%2"
   [(set_attr "type" "simd_vmove")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -982,9 +1006,10 @@ (define_insn "vmovw_insn"
 (define_insn "vmovzw_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:SI 1 "nonmemory_operand"  "r")
-		      (match_operand:SI 2 "immediate_operand" "P")] UNSPEC_ARC_SIMD_VMOVZW))]
+		      (match_operand:SI 2 "immediate_operand" "P")]
+		     UNSPEC_ARC_SIMD_VMOVZW))]
   "TARGET_SIMD_SET"
-  "vmovzw %0, %1, %2"
+  "vmovzw\\t%0,%1,%2"
   [(set_attr "type" "simd_vmove_else_zero")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -994,9 +1019,10 @@ (define_insn "vsr8_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 		      (match_operand:SI 2 "immediate_operand" "K")
-		      (match_operand:V8HI 3 "vector_register_operand"  "v")] UNSPEC_ARC_SIMD_VSR8))]
+		      (match_operand:V8HI 3 "vector_register_operand"  "v")]
+		     UNSPEC_ARC_SIMD_VSR8))]
   "TARGET_SIMD_SET"
-  "vsr8 %0, %1, i%2"
+  "vsr8\\t%0,%1,i%2"
   [(set_attr "type" "simd_valign")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -1005,9 +1031,10 @@ (define_insn "vasrw_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 		      (match_operand:SI 2 "immediate_operand" "K")
-		      (match_operand:V8HI 3 "vector_register_operand"  "v")] UNSPEC_ARC_SIMD_VASRW))]
+		      (match_operand:V8HI 3 "vector_register_operand"  "v")]
+		     UNSPEC_ARC_SIMD_VASRW))]
   "TARGET_SIMD_SET"
-  "vasrw %0, %1, i%2"
+  "vasrw\\t%0,%1,i%2"
   [(set_attr "type" "simd_varith_1cycle")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -1016,9 +1043,10 @@ (define_insn "vsr8aw_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"           "=v")
 	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")
 		      (match_operand:SI 2 "immediate_operand" "K")
-		      (match_operand:V8HI 3 "vector_register_operand"  "v")] UNSPEC_ARC_SIMD_VSR8AW))]
+		      (match_operand:V8HI 3 "vector_register_operand"  "v")]
+		     UNSPEC_ARC_SIMD_VSR8AW))]
   "TARGET_SIMD_SET"
-  "vsr8aw %0, %1, i%2"
+  "vsr8aw\\t%0,%1,i%2"
   [(set_attr "type" "simd_valign_with_acc")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -1026,99 +1054,110 @@ (define_insn "vsr8aw_insn"
 ;; Va, Vb insns
 (define_insn "vabsaw_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"  "=v")
-	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")] UNSPEC_ARC_SIMD_VABSAW))]
+	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")]
+		     UNSPEC_ARC_SIMD_VABSAW))]
   "TARGET_SIMD_SET"
-  "vabsaw %0, %1"
+  "vabsaw\\t%0,%1"
   [(set_attr "type" "simd_varith_with_acc")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
 
 (define_insn "vabsw_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"  "=v")
-	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")] UNSPEC_ARC_SIMD_VABSW))]
+	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")]
+		     UNSPEC_ARC_SIMD_VABSW))]
   "TARGET_SIMD_SET"
-  "vabsw %0, %1"
+  "vabsw\\t%0,%1"
   [(set_attr "type" "simd_varith_1cycle")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
 
 (define_insn "vaddsuw_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"  "=v")
-	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")] UNSPEC_ARC_SIMD_VADDSUW))]
+	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")]
+		     UNSPEC_ARC_SIMD_VADDSUW))]
   "TARGET_SIMD_SET"
-  "vaddsuw %0, %1"
+  "vaddsuw\\t%0,%1"
   [(set_attr "type" "simd_varith_1cycle")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
 
 (define_insn "vsignw_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"  "=v")
-	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")] UNSPEC_ARC_SIMD_VSIGNW))]
+	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")]
+		     UNSPEC_ARC_SIMD_VSIGNW))]
   "TARGET_SIMD_SET"
-  "vsignw %0, %1"
+  "vsignw\\t%0,%1"
   [(set_attr "type" "simd_varith_1cycle")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
 
 (define_insn "vexch1_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"  "=v")
-	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")] UNSPEC_ARC_SIMD_VEXCH1))]
+	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")]
+		     UNSPEC_ARC_SIMD_VEXCH1))]
   "TARGET_SIMD_SET"
-  "vexch1 %0, %1"
+  "vexch1\\t%0,%1"
   [(set_attr "type" "simd_vpermute")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
 
 (define_insn "vexch2_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"  "=v")
-	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")] UNSPEC_ARC_SIMD_VEXCH2))]
+	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")]
+		     UNSPEC_ARC_SIMD_VEXCH2))]
   "TARGET_SIMD_SET"
-  "vexch2 %0, %1"
+  "vexch2\\t%0,%1"
   [(set_attr "type" "simd_vpermute")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
 
 (define_insn "vexch4_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"  "=v")
-	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")] UNSPEC_ARC_SIMD_VEXCH4))]
+	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")]
+		     UNSPEC_ARC_SIMD_VEXCH4))]
   "TARGET_SIMD_SET"
-  "vexch4 %0, %1"
+  "vexch4\\t%0,%1"
   [(set_attr "type" "simd_vpermute")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
 
 (define_insn "vupbaw_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"  "=v")
-	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")] UNSPEC_ARC_SIMD_VUPBAW))]
+	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")]
+		     UNSPEC_ARC_SIMD_VUPBAW))]
   "TARGET_SIMD_SET"
-  "vupbaw %0, %1"
+  "vupbaw\\t%0,%1"
   [(set_attr "type" "simd_vpack_with_acc")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
 
 (define_insn "vupbw_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"  "=v")
-	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")] UNSPEC_ARC_SIMD_VUPBW))]
+	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")]
+		     UNSPEC_ARC_SIMD_VUPBW))]
   "TARGET_SIMD_SET"
-  "vupbw %0, %1"
+  "vupbw\\t%0,%1"
   [(set_attr "type" "simd_vpack")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
 
 (define_insn "vupsbaw_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"  "=v")
-	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")] UNSPEC_ARC_SIMD_VUPSBAW))]
+	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")]
+		     UNSPEC_ARC_SIMD_VUPSBAW))]
   "TARGET_SIMD_SET"
-  "vupsbaw %0, %1"
+  "vupsbaw\\t%0,%1"
   [(set_attr "type" "simd_vpack_with_acc")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
 
 (define_insn "vupsbw_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand"  "=v")
-	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")] UNSPEC_ARC_SIMD_VUPSBW))]
+	(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand"  "v")]
+		     UNSPEC_ARC_SIMD_VUPSBW))]
   "TARGET_SIMD_SET"
-  "vupsbw %0, %1"
+  "vupsbw\\t%0,%1"
   [(set_attr "type" "simd_vpack")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -1127,9 +1166,10 @@ (define_insn "vupsbw_insn"
 (define_insn "vdirun_insn"
   [(set (match_operand:SI 0 "arc_simd_dma_register_operand"           "=d")
 	(unspec_volatile:SI [(match_operand:SI 1 "nonmemory_operand"  "r")
-			     (match_operand:SI 2 "nonmemory_operand" "r")] UNSPEC_ARC_SIMD_VDIRUN))]
+			     (match_operand:SI 2 "nonmemory_operand" "r")]
+			    UNSPEC_ARC_SIMD_VDIRUN))]
   "TARGET_SIMD_SET"
-  "vdirun %1, %2"
+  "vdirun\\t%1,%2"
   [(set_attr "type" "simd_dma")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -1137,60 +1177,67 @@ (define_insn "vdirun_insn"
 (define_insn "vdorun_insn"
   [(set (match_operand:SI 0 "arc_simd_dma_register_operand"              "=d")
 	(unspec_volatile:SI [(match_operand:SI 1 "nonmemory_operand"     "r")
-			     (match_operand:SI 2 "nonmemory_operand"     "r")] UNSPEC_ARC_SIMD_VDORUN))]
+			     (match_operand:SI 2 "nonmemory_operand"     "r")]
+			    UNSPEC_ARC_SIMD_VDORUN))]
   "TARGET_SIMD_SET"
-  "vdorun %1, %2"
+  "vdorun\\t%1,%2"
   [(set_attr "type" "simd_dma")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
 
 (define_insn "vdiwr_insn"
   [(set (match_operand:SI 0 "arc_simd_dma_register_operand"           "=d,d")
-	(unspec_volatile:SI [(match_operand:SI 1 "nonmemory_operand"  "r,Cal")] UNSPEC_ARC_SIMD_VDIWR))]
+	(unspec_volatile:SI [(match_operand:SI 1 "nonmemory_operand"  "r,Cal")]
+			    UNSPEC_ARC_SIMD_VDIWR))]
   "TARGET_SIMD_SET"
-  "vdiwr %0, %1"
+  "vdiwr\\t%0,%1"
   [(set_attr "type" "simd_dma")
    (set_attr "length" "4,8")
    (set_attr "cond" "nocond,nocond")])
 
 (define_insn "vdowr_insn"
   [(set (match_operand:SI 0 "arc_simd_dma_register_operand"           "=d,d")
-	(unspec_volatile:SI [(match_operand:SI 1 "nonmemory_operand"  "r,Cal")] UNSPEC_ARC_SIMD_VDOWR))]
+	(unspec_volatile:SI [(match_operand:SI 1 "nonmemory_operand"  "r,Cal")]
+			    UNSPEC_ARC_SIMD_VDOWR))]
   "TARGET_SIMD_SET"
-  "vdowr %0, %1"
+  "vdowr\\t%0,%1"
   [(set_attr "type" "simd_dma")
    (set_attr "length" "4,8")
    (set_attr "cond" "nocond,nocond")])
 
 ;; vector record and run instructions
 (define_insn "vrec_insn"
-  [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand"  "r")] UNSPEC_ARC_SIMD_VREC)]
+  [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand"  "r")]
+		    UNSPEC_ARC_SIMD_VREC)]
   "TARGET_SIMD_SET"
-  "vrec %0"
+  "vrec\\t%0"
   [(set_attr "type" "simd_vcontrol")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
 
 (define_insn "vrun_insn"
-  [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand"  "r")] UNSPEC_ARC_SIMD_VRUN)]
+  [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand"  "r")]
+		    UNSPEC_ARC_SIMD_VRUN)]
   "TARGET_SIMD_SET"
-  "vrun %0"
+  "vrun\\t%0"
   [(set_attr "type" "simd_vcontrol")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
 
 (define_insn "vrecrun_insn"
-  [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand"  "r")] UNSPEC_ARC_SIMD_VRECRUN)]
+  [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand"  "r")]
+		    UNSPEC_ARC_SIMD_VRECRUN)]
   "TARGET_SIMD_SET"
-  "vrecrun %0"
+  "vrecrun\\t%0"
   [(set_attr "type" "simd_vcontrol")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
 
 (define_insn "vendrec_insn"
-  [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand"  "r")] UNSPEC_ARC_SIMD_VENDREC)]
+  [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand"  "r")]
+		    UNSPEC_ARC_SIMD_VENDREC)]
   "TARGET_SIMD_SET"
-  "vendrec %0"
+  "vendrec\\t%0"
   [(set_attr "type" "simd_vcontrol")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -1211,7 +1258,7 @@ (define_insn "vld32wh_insn"
 	  (parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3)])
 	  )))]
   "TARGET_SIMD_SET"
-  "vld32wh %0, [i%3,%1]"
+  "vld32wh\\t%0,[i%3,%1]"
   [(set_attr "type" "simd_vload")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -1232,18 +1279,22 @@ (define_insn "vld32wl_insn"
 			     [(match_operand:SI 3 "immediate_operand" "L")]))
 	     ))))))]
   "TARGET_SIMD_SET"
-  "vld32wl %0, [i%3,%1]"
+  "vld32wl\\t%0,[i%3,%1]"
   [(set_attr "type" "simd_vload")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
 
 (define_insn "vld64w_insn"
   [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
-	(zero_extend:V8HI (mem:V4HI (plus:SI (zero_extend:SI (vec_select:HI (match_operand:V8HI 1 "vector_register_operand"  "v")
-									    (parallel [(match_operand:SI 2 "immediate_operand" "L")])))
-					     (match_operand:SI 3 "immediate_operand" "P")))))]
+	(zero_extend:V8HI
+	 (mem:V4HI
+	  (plus:SI
+	   (zero_extend:SI
+	    (vec_select:HI (match_operand:V8HI 1 "vector_register_operand"  "v")
+			   (parallel [(match_operand:SI 2 "immediate_operand" "L")])))
+	   (match_operand:SI 3 "immediate_operand" "P")))))]
  "TARGET_SIMD_SET"
- "vld64w %0, [i%2, %3]"
+ "vld64w\\t%0,[i%2,%3]"
  [(set_attr "type" "simd_vload")
   (set_attr "length" "4")
   (set_attr "cond" "nocond")]
@@ -1264,7 +1315,7 @@ (define_insn "vld64_insn"
 	     (parallel [(match_operand:SI 3 "immediate_operand" "L")]))
 	    )))))]
   "TARGET_SIMD_SET"
-  "vld64 %0, [i%3,%1]"
+  "vld64\\t%0,[i%3,%1]"
   [(set_attr "type" "simd_vload")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -1287,40 +1338,48 @@ (define_insn "vld32_insn"
 	      (match_operand:V8HI 2 "vector_register_operand"  "v")
 	      (parallel [(match_operand:SI 3 "immediate_operand" "L")]))))))))]
   "TARGET_SIMD_SET"
-  "vld32 %0, [i%3,%1]"
+  "vld32\\t%0,[i%3,%1]"
   [(set_attr "type" "simd_vload")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
 
 (define_insn "vst16_n_insn"
-  [(set  (mem:HI (plus:SI (match_operand:SI 0 "immediate_operand" "P")
-			  (zero_extend: SI (vec_select:HI (match_operand:V8HI 1 "vector_register_operand"  "v")
-							  (parallel [(match_operand:SI 2 "immediate_operand" "L")])))))
+  [(set (mem:HI
+	 (plus:SI
+	  (match_operand:SI 0 "immediate_operand" "P")
+	  (zero_extend:SI
+	   (vec_select:HI (match_operand:V8HI 1 "vector_register_operand"  "v")
+			  (parallel [(match_operand:SI 2 "immediate_operand" "L")])))))
 	 (vec_select:HI (match_operand:V8HI 3 "vector_register_operand" "v")
 			(parallel [(match_operand:SI 4 "immediate_operand" "L")])))]
  "TARGET_SIMD_SET"
- "vst16_%4 %3,[i%2, %0]"
+ "vst16_%4\\t%3,[i%2,%0]"
  [(set_attr "type" "simd_vstore")
   (set_attr "length" "4")
   (set_attr "cond" "nocond")])
 
 (define_insn "vst32_n_insn"
-  [(set  (mem:SI (plus:SI (match_operand:SI 0 "immediate_operand" "P")
-			  (zero_extend: SI (vec_select:HI (match_operand:V8HI 1 "vector_register_operand"  "v")
-							  (parallel [(match_operand:SI 2 "immediate_operand" "L")])))))
-	 (vec_select:SI (unspec:V4SI [(match_operand:V8HI 3 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VCAST)
-			(parallel [(match_operand:SI 4 "immediate_operand" "L")])))]
+  [(set (mem:SI
+	 (plus:SI
+	  (match_operand:SI 0 "immediate_operand" "P")
+	  (zero_extend:SI
+	   (vec_select:HI (match_operand:V8HI 1 "vector_register_operand"  "v")
+			  (parallel [(match_operand:SI 2 "immediate_operand" "L")])))))
+	(vec_select:SI (unspec:V4SI [(match_operand:V8HI 3 "vector_register_operand" "v")]
+				    UNSPEC_ARC_SIMD_VCAST)
+		       (parallel [(match_operand:SI 4 "immediate_operand" "L")])))]
  "TARGET_SIMD_SET"
- "vst32_%4 %3,[i%2, %0]"
+ "vst32_%4\\t%3,[i%2,%0]"
  [(set_attr "type" "simd_vstore")
   (set_attr "length" "4")
   (set_attr "cond" "nocond")])
 
 ;; SIMD unit interrupt
 (define_insn "vinti_insn"
-  [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand"  "L")] UNSPEC_ARC_SIMD_VINTI)]
+  [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand"  "L")]
+		    UNSPEC_ARC_SIMD_VINTI)]
   "TARGET_SIMD_SET"
-  "vinti %0"
+  "vinti\\t%0"
   [(set_attr "type" "simd_vcontrol")
    (set_attr "length" "4")
    (set_attr "cond" "nocond")])
@@ -1357,14 +1416,14 @@ (define_expand "movv2hi"
 
 (define_insn_and_split "*movv2hi_insn"
   [(set (match_operand:V2HI 0 "move_dest_operand" "=r,r,r,m")
-	(match_operand:V2HI 1 "general_operand"       "i,r,m,r"))]
+	(match_operand:V2HI 1 "general_operand"    "i,r,m,r"))]
   "(register_operand (operands[0], V2HImode)
     || register_operand (operands[1], V2HImode))"
   "@
    #
-   mov%? %0, %1
-   ld%U1%V1 %0,%1
-   st%U0%V0 %1,%0"
+   mov%?\\t%0,%1
+   ld%U1%V1\\t%0,%1
+   st%U0%V0\\t%1,%0"
   "reload_completed && GET_CODE (operands[1]) == CONST_VECTOR"
   [(set (match_dup 0) (match_dup 2))]
   {
@@ -1380,8 +1439,8 @@ (define_insn_and_split "*movv2hi_insn"
    ])
 
 (define_expand "movmisalignv2hi"
- [(set (match_operand:V2HI 0 "general_operand" "")
-       (match_operand:V2HI 1 "general_operand" ""))]
+  [(set (match_operand:V2HI 0 "general_operand" "")
+	(match_operand:V2HI 1 "general_operand" ""))]
  "unaligned_access"
  "{
    if (prepare_move_operands (operands, V2HImode))
@@ -1411,19 +1470,19 @@ (define_insn_and_split "*mov<mode>_insn"
 
      case 1:
        if (TARGET_PLUS_QMACW
-           && even_register_operand (operands[0], <MODE>mode)
+	   && even_register_operand (operands[0], <MODE>mode)
 	   && even_register_operand (operands[1], <MODE>mode))
-         return \"vadd2%?\\t%0,%1,0\";
+	 return \"vadd2%?\\t%0,%1,0\";
        return \"#\";
 
      case 2:
        if (TARGET_LL64)
-         return \"ldd%U1%V1 %0,%1\";
+	 return \"ldd%U1%V1\\t%0,%1\";
        return \"#\";
 
      case 3:
        if (TARGET_LL64)
-	   return \"std%U0%V0 %1,%0\";
+	   return \"std%U0%V0\\t%1,%0\";
 	 return \"#\";
     }
 }"
@@ -1439,8 +1498,8 @@ (define_insn_and_split "*mov<mode>_insn"
    ])
 
 (define_expand "movmisalign<mode>"
- [(set (match_operand:VWH 0 "general_operand" "")
-       (match_operand:VWH 1 "general_operand" ""))]
+  [(set (match_operand:VWH 0 "general_operand" "")
+	(match_operand:VWH 1 "general_operand" ""))]
  "unaligned_access"
  "{
    if (prepare_move_operands (operands, <MODE>mode))
@@ -1449,9 +1508,9 @@ (define_expand "movmisalign<mode>"
 
 (define_insn "bswapv2hi2"
   [(set (match_operand:V2HI 0 "register_operand" "=r,r")
-        (bswap:V2HI (match_operand:V2HI 1 "nonmemory_operand" "r,i")))]
+	(bswap:V2HI (match_operand:V2HI 1 "nonmemory_operand" "r,i")))]
   "TARGET_V2 && TARGET_SWAP"
-  "swape %0, %1"
+  "swape\\t%0,%1"
   [(set_attr "length" "4,8")
    (set_attr "type" "two_cycle_core")])
 
@@ -1461,7 +1520,7 @@ (define_insn "add<mode>3"
 	(plus:VCT (match_operand:VCT 1 "register_operand" "0,r")
 		  (match_operand:VCT 2 "register_operand" "r,r")))]
   "TARGET_PLUS_DMPY"
-  "vadd<V_suffix>%? %0, %1, %2"
+  "vadd<V_suffix>%?\\t%0,%1,%2"
   [(set_attr "length" "4")
    (set_attr "type" "multi")
    (set_attr "predicable" "yes,no")
@@ -1472,7 +1531,7 @@ (define_insn "sub<mode>3"
 	(minus:VCT (match_operand:VCT 1 "register_operand" "0,r")
 		   (match_operand:VCT 2 "register_operand" "r,r")))]
   "TARGET_PLUS_DMPY"
-  "vsub<V_suffix>%? %0, %1, %2"
+  "vsub<V_suffix>%?\\t%0,%1,%2"
   [(set_attr "length" "4")
    (set_attr "type" "multi")
    (set_attr "predicable" "yes,no")
@@ -1482,14 +1541,16 @@ (define_insn "sub<mode>3"
 (define_insn "addsub<mode>3"
   [(set (match_operand:VDV 0 "register_operand" "=r,r")
 	(vec_concat:VDV
-	 (plus:<V_addsub> (vec_select:<V_addsub> (match_operand:VDV 1 "register_operand" "0,r")
-						 (parallel [(const_int 0)]))
-			  (vec_select:<V_addsub> (match_operand:VDV 2 "register_operand" "r,r")
-						 (parallel [(const_int 0)])))
-	 (minus:<V_addsub> (vec_select:<V_addsub> (match_dup 1) (parallel [(const_int 1)]))
-			   (vec_select:<V_addsub> (match_dup 2) (parallel [(const_int 1)])))))]
+	 (plus:<V_addsub>
+	  (vec_select:<V_addsub> (match_operand:VDV 1 "register_operand" "0,r")
+				 (parallel [(const_int 0)]))
+	  (vec_select:<V_addsub> (match_operand:VDV 2 "register_operand" "r,r")
+				 (parallel [(const_int 0)])))
+	 (minus:<V_addsub>
+	  (vec_select:<V_addsub> (match_dup 1) (parallel [(const_int 1)]))
+	  (vec_select:<V_addsub> (match_dup 2) (parallel [(const_int 1)])))))]
   "TARGET_PLUS_DMPY"
-  "vaddsub<V_addsub_suffix>%? %0, %1, %2"
+  "vaddsub<V_addsub_suffix>%?\\t%0,%1,%2"
   [(set_attr "length" "4")
    (set_attr "type" "multi")
    (set_attr "predicable" "yes,no")
@@ -1498,14 +1559,16 @@ (define_insn "addsub<mode>3"
 (define_insn "subadd<mode>3"
   [(set (match_operand:VDV 0 "register_operand" "=r,r")
 	(vec_concat:VDV
-	 (minus:<V_addsub> (vec_select:<V_addsub> (match_operand:VDV 1 "register_operand" "0,r")
-						  (parallel [(const_int 0)]))
-			   (vec_select:<V_addsub> (match_operand:VDV 2 "register_operand" "r,r")
-						  (parallel [(const_int 0)])))
-	 (plus:<V_addsub> (vec_select:<V_addsub> (match_dup 1) (parallel [(const_int 1)]))
-			  (vec_select:<V_addsub> (match_dup 2) (parallel [(const_int 1)])))))]
+	 (minus:<V_addsub>
+	  (vec_select:<V_addsub> (match_operand:VDV 1 "register_operand" "0,r")
+				 (parallel [(const_int 0)]))
+	  (vec_select:<V_addsub> (match_operand:VDV 2 "register_operand" "r,r")
+				 (parallel [(const_int 0)])))
+	 (plus:<V_addsub>
+	  (vec_select:<V_addsub> (match_dup 1) (parallel [(const_int 1)]))
+	  (vec_select:<V_addsub> (match_dup 2) (parallel [(const_int 1)])))))]
   "TARGET_PLUS_DMPY"
-  "vsubadd<V_addsub_suffix>%? %0, %1, %2"
+  "vsubadd<V_addsub_suffix>%?\\t%0,%1,%2"
   [(set_attr "length" "4")
    (set_attr "type" "multi")
    (set_attr "predicable" "yes,no")
@@ -1515,10 +1578,11 @@ (define_insn "addsubv4hi3"
   [(set (match_operand:V4HI 0 "even_register_operand" "=r,r")
 	(vec_concat:V4HI
 	 (vec_concat:V2HI
-	  (plus:HI (vec_select:HI (match_operand:V4HI 1 "even_register_operand" "0,r")
-				  (parallel [(const_int 0)]))
-		   (vec_select:HI (match_operand:V4HI 2 "even_register_operand" "r,r")
-				  (parallel [(const_int 0)])))
+	  (plus:HI
+	   (vec_select:HI (match_operand:V4HI 1 "even_register_operand" "0,r")
+			  (parallel [(const_int 0)]))
+	   (vec_select:HI (match_operand:V4HI 2 "even_register_operand" "r,r")
+			  (parallel [(const_int 0)])))
 	  (minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
 		    (vec_select:HI (match_dup 2) (parallel [(const_int 1)]))))
 	 (vec_concat:V2HI
@@ -1528,7 +1592,7 @@ (define_insn "addsubv4hi3"
 		    (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
 	 ))]
   "TARGET_PLUS_QMACW"
-  "vaddsub4h%? %0, %1, %2"
+  "vaddsub4h%?\\t%0,%1,%2"
   [(set_attr "length" "4")
    (set_attr "type" "multi")
    (set_attr "predicable" "yes,no")
@@ -1538,10 +1602,11 @@ (define_insn "subaddv4hi3"
   [(set (match_operand:V4HI 0 "even_register_operand" "=r,r")
 	(vec_concat:V4HI
 	 (vec_concat:V2HI
-	  (minus:HI (vec_select:HI (match_operand:V4HI 1 "even_register_operand" "0,r")
-				   (parallel [(const_int 0)]))
-		    (vec_select:HI (match_operand:V4HI 2 "even_register_operand" "r,r")
-				  (parallel [(const_int 0)])))
+	  (minus:HI
+	   (vec_select:HI (match_operand:V4HI 1 "even_register_operand" "0,r")
+			  (parallel [(const_int 0)]))
+	   (vec_select:HI (match_operand:V4HI 2 "even_register_operand" "r,r")
+			  (parallel [(const_int 0)])))
 	  (plus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
 		   (vec_select:HI (match_dup 2) (parallel [(const_int 1)]))))
 	 (vec_concat:V2HI
@@ -1551,7 +1616,7 @@ (define_insn "subaddv4hi3"
 		   (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
 	 ))]
   "TARGET_PLUS_QMACW"
-  "vsubadd4h%? %0, %1, %2"
+  "vsubadd4h%?\\t%0,%1,%2"
   [(set_attr "length" "4")
    (set_attr "type" "multi")
    (set_attr "predicable" "yes,no")
@@ -1581,7 +1646,7 @@ (define_insn "dmpyh<V_US_suffix>"
 	   (SE:SI (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
 	   (SE:SI (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))))]
   "TARGET_PLUS_DMPY"
-  "dmpyh<V_US_suffix>%? %0, %1, %2"
+  "dmpyh<V_US_suffix>%?\\t%0,%1,%2"
   [(set_attr "length" "4")
    (set_attr "type" "multi")
    (set_attr "predicable" "yes,no")
@@ -1662,13 +1727,15 @@ (define_insn "arc_vec_<V_US>mult_lo_v4hi"
 			    (match_operand:V4HI 2 "even_register_operand" "r,r")
 			    (parallel [(const_int 0) (const_int 1)])))))
   (set (reg:V2SI ARCV2_ACC)
-       (mult:V2SI (SE:V2SI (vec_select:V2HI (match_dup 1)
-					    (parallel [(const_int 0) (const_int 1)])))
-		  (SE:V2SI (vec_select:V2HI (match_dup 2)
-					    (parallel [(const_int 0) (const_int 1)])))))
+       (mult:V2SI (SE:V2SI
+		   (vec_select:V2HI (match_dup 1)
+				    (parallel [(const_int 0) (const_int 1)])))
+		  (SE:V2SI
+		   (vec_select:V2HI (match_dup 2)
+				    (parallel [(const_int 0) (const_int 1)])))))
   ]
   "TARGET_PLUS_MACD"
-  "vmpy2h<V_US_suffix>%? %0, %1, %2"
+  "vmpy2h<V_US_suffix>%?\\t%0,%1,%2"
   [(set_attr "length" "4")
    (set_attr "type" "multi")
    (set_attr "predicable" "yes,no")
@@ -1684,7 +1751,7 @@ (define_insn "arc_vec_<V_US>multacc_lo_v4hi"
 			     (parallel [(const_int 0) (const_int 1)])))))
   ]
   "TARGET_PLUS_MACD"
-  "vmpy2h<V_US_suffix>%? 0, %0, %1"
+  "vmpy2h<V_US_suffix>%?\\t0,%0,%1"
   [(set_attr "length" "4")
    (set_attr "type" "multi")
    (set_attr "predicable" "no")
@@ -1716,26 +1783,28 @@ (define_insn "arc_vec_<V_US>mult_hi_v4hi"
 			    (match_operand:V4HI 2 "even_register_operand" "r,r")
 			    (parallel [(const_int 2) (const_int 3)])))))
   (set (reg:V2SI ARCV2_ACC)
-       (mult:V2SI (SE:V2SI (vec_select:V2HI (match_dup 1)
-					    (parallel [(const_int 2) (const_int 3)])))
-		  (SE:V2SI (vec_select:V2HI (match_dup 2)
-					    (parallel [(const_int 2) (const_int 3)])))))
+       (mult:V2SI (SE:V2SI
+		   (vec_select:V2HI (match_dup 1)
+				    (parallel [(const_int 2) (const_int 3)])))
+		  (SE:V2SI
+		   (vec_select:V2HI (match_dup 2)
+				    (parallel [(const_int 2) (const_int 3)])))))
   ]
   "TARGET_PLUS_QMACW"
-  "vmpy2h<V_US_suffix>%? %0, %R1, %R2"
+  "vmpy2h<V_US_suffix>%?\\t%0,%R1,%R2"
   [(set_attr "length" "4")
    (set_attr "type" "multi")
    (set_attr "predicable" "yes,no")
    (set_attr "cond" "canuse,nocond")])
 
 (define_expand "vec_widen_<V_US>mult_hi_v4hi"
- [(set (match_operand:V2SI 0 "even_register_operand"                               "")
+ [(set (match_operand:V2SI 0 "even_register_operand")
        (mult:V2SI (SE:V2SI (vec_select:V2HI
-				     (match_operand:V4HI 1 "even_register_operand" "")
-				     (parallel [(const_int 2) (const_int 3)])))
+			    (match_operand:V4HI 1 "even_register_operand")
+			    (parallel [(const_int 2) (const_int 3)])))
 		  (SE:V2SI (vec_select:V2HI
-				     (match_operand:V4HI 2 "even_register_operand" "")
-				     (parallel [(const_int 2) (const_int 3)])))))]
+			    (match_operand:V4HI 2 "even_register_operand")
+			    (parallel [(const_int 2) (const_int 3)])))))]
   "TARGET_PLUS_MACD"
   {
      emit_insn (gen_arc_vec_<V_US>mult_hi_v4hi (operands[0],
@@ -1746,10 +1815,11 @@ (define_expand "vec_widen_<V_US>mult_hi_v4hi"
 )
 
 (define_insn "arc_vec_<V_US>mac_v2hiv2si"
- [(set (match_operand:V2SI 0 "even_register_operand"                "=r,Ral,r")
+ [(set (match_operand:V2SI 0 "even_register_operand"     "=r,Ral,r")
        (plus:V2SI
-	(mult:V2SI (SE:V2SI (match_operand:V2HI 1 "register_operand" "0,  r,r"))
-		   (SE:V2SI (match_operand:V2HI 2 "register_operand" "r,  r,r")))
+	(mult:V2SI
+	 (SE:V2SI (match_operand:V2HI 1 "register_operand" "0,  r,r"))
+	 (SE:V2SI (match_operand:V2HI 2 "register_operand" "r,  r,r")))
 	(reg:V2SI ARCV2_ACC)))
   (set (reg:V2SI ARCV2_ACC)
        (plus:V2SI
@@ -1786,7 +1856,7 @@ (define_insn "dmach"
 		   UNSPEC_ARC_DMACH))
    (clobber (reg:DI ARCV2_ACC))]
   "TARGET_PLUS_DMPY"
-  "dmach%? %0, %1, %2"
+  "dmach%?\\t%0,%1,%2"
   [(set_attr "length" "4")
    (set_attr "type" "multi")
    (set_attr "predicable" "yes,no")
@@ -1800,7 +1870,7 @@ (define_insn "dmachu"
 		   UNSPEC_ARC_DMACHU))
    (clobber (reg:DI ARCV2_ACC))]
   "TARGET_PLUS_DMPY"
-  "dmachu%? %0, %1, %2"
+  "dmachu%?\\t%0,%1,%2"
   [(set_attr "length" "4")
    (set_attr "type" "multi")
    (set_attr "predicable" "yes,no")
@@ -1814,7 +1884,7 @@ (define_insn "dmacwh"
 		   UNSPEC_ARC_DMACWH))
    (clobber (reg:DI ARCV2_ACC))]
   "TARGET_PLUS_QMACW"
-  "dmacwh%? %0, %1, %2"
+  "dmacwh%?\\t%0,%1,%2"
   [(set_attr "length" "4")
    (set_attr "type" "multi")
    (set_attr "predicable" "yes,no")
@@ -1828,7 +1898,7 @@ (define_insn "dmacwhu"
 		   UNSPEC_ARC_DMACWHU))
    (clobber (reg:DI ARCV2_ACC))]
   "TARGET_PLUS_QMACW"
-  "dmacwhu%? %0, %1, %2"
+  "dmacwhu%?\\t%0,%1,%2"
   [(set_attr "length" "4")
    (set_attr "type" "multi")
    (set_attr "predicable" "yes,no")
@@ -1842,7 +1912,7 @@ (define_insn "vmac2h"
 		     UNSPEC_ARC_VMAC2H))
    (clobber (reg:DI ARCV2_ACC))]
   "TARGET_PLUS_MACD"
-  "vmac2h%? %0, %1, %2"
+  "vmac2h%?\\t%0,%1,%2"
   [(set_attr "length" "4")
    (set_attr "type" "multi")
    (set_attr "predicable" "yes,no")
@@ -1856,7 +1926,7 @@ (define_insn "vmac2hu"
 		   UNSPEC_ARC_VMAC2HU))
    (clobber (reg:DI ARCV2_ACC))]
   "TARGET_PLUS_MACD"
-  "vmac2hu%? %0, %1, %2"
+  "vmac2hu%?\\t%0,%1,%2"
   [(set_attr "length" "4")
    (set_attr "type" "multi")
    (set_attr "predicable" "yes,no")
@@ -1869,7 +1939,7 @@ (define_insn "vmpy2h"
 		     UNSPEC_ARC_VMPY2H))
    (clobber (reg:DI ARCV2_ACC))]
   "TARGET_PLUS_MACD"
-  "vmpy2h%? %0, %1, %2"
+  "vmpy2h%?\\t%0,%1,%2"
   [(set_attr "length" "4")
    (set_attr "type" "multi")
    (set_attr "predicable" "yes,no")
@@ -1882,7 +1952,7 @@ (define_insn "vmpy2hu"
 		     UNSPEC_ARC_VMPY2HU))
    (clobber (reg:DI ARCV2_ACC))]
   "TARGET_PLUS_MACD"
-  "vmpy2hu%? %0, %1, %2"
+  "vmpy2hu%?\\t%0,%1,%2"
   [(set_attr "length" "4")
    (set_attr "type" "multi")
    (set_attr "predicable" "yes,no")
@@ -1896,7 +1966,7 @@ (define_insn "qmach"
 		     UNSPEC_ARC_QMACH))
    (clobber (reg:DI ARCV2_ACC))]
   "TARGET_PLUS_QMACW"
-  "qmach%? %0, %1, %2"
+  "qmach%?\\t%0,%1,%2"
   [(set_attr "length" "4")
    (set_attr "type" "multi")
    (set_attr "predicable" "yes,no")
@@ -1910,7 +1980,7 @@ (define_insn "qmachu"
 		   UNSPEC_ARC_QMACHU))
    (clobber (reg:DI ARCV2_ACC))]
   "TARGET_PLUS_QMACW"
-  "qmachu%? %0, %1, %2"
+  "qmachu%?\\t%0,%1,%2"
   [(set_attr "length" "4")
    (set_attr "type" "multi")
    (set_attr "predicable" "yes,no")
@@ -1923,7 +1993,7 @@ (define_insn "qmpyh"
 		     UNSPEC_ARC_QMPYH))
    (clobber (reg:DI ARCV2_ACC))]
   "TARGET_PLUS_QMACW"
-  "qmpyh%? %0, %1, %2"
+  "qmpyh%?\\t%0,%1,%2"
   [(set_attr "length" "4")
    (set_attr "type" "multi")
    (set_attr "predicable" "yes,no")
@@ -1936,7 +2006,7 @@ (define_insn "qmpyhu"
 		   UNSPEC_ARC_QMPYHU))
    (clobber (reg:DI ARCV2_ACC))]
   "TARGET_PLUS_QMACW"
-  "qmpyhu%? %0, %1, %2"
+  "qmpyhu%?\\t%0,%1,%2"
   [(set_attr "length" "4")
    (set_attr "type" "multi")
    (set_attr "predicable" "yes,no")
