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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id t7sm60531eds.26.2021.05.05.12.37.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 May 2021 12:37:06 -0700 (PDT) To: gcc-patches@gcc.gnu.org Subject: [PATCH v2 08/10] RISC-V: Add s.ext-consuming INSNs for LR and SC [PR 100266] Date: Wed, 5 May 2021 21:36:49 +0200 Message-Id: <20210505193651.2075405-9-cmuellner@gcc.gnu.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210505193651.2075405-1-cmuellner@gcc.gnu.org> References: <20210505193651.2075405-1-cmuellner@gcc.gnu.org> MIME-Version: 1.0 X-Spam-Status: No, score=-11.7 required=5.0 tests=BAYES_00, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Christoph Muellner via Gcc-patches From: =?utf-8?q?Christoph_M=C3=BCllner?= Reply-To: Christoph Muellner Cc: Kito Cheng Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" The current model of the LR and SC INSNs requires a sign-extension to use the generated SImode value for conditional branches, which only operate on XLEN registers. However, the sign-extension is actually not required in both cases, therefore this patch introduces additional INSNs that consume the sign-extension. Rationale: The sign-extension of the loaded value of a LR.W is specified as sign-extended. Therefore, a sign-extension is not required. The sign-extension of the success value a SC.W is specified as non-zero. As sign-extended non-zero value remains non-zero, therefore the sign-extension is not required. gcc/ PR 100266 * config/riscv/sync.md (riscv_load_reserved): New. * config/riscv/sync.md (riscv_store_conditional): New. --- gcc/config/riscv/sync.md | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index edff6520b87e..49b860da8ef0 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -125,6 +125,21 @@ "lr.%A2 %0, %1" ) +;; This pattern allows to consume a sign-extension of the loaded value. +;; This is legal, because the specification of LR.W defines the loaded +;; value to be sign-extended. + +(define_insn "riscv_load_reserved" + [(set (match_operand:DI 0 "register_operand" "=r") + (sign_extend:DI + (unspec_volatile:SI + [(match_operand:SI 1 "memory_operand" "A") + (match_operand:SI 2 "const_int_operand")] ;; model + UNSPEC_LOAD_RESERVED)))] + "TARGET_ATOMIC && TARGET_64BIT" + "lr.w%A2 %0, %1" +) + (define_insn "@riscv_store_conditional" [(set (match_operand:GPR 0 "register_operand" "=&r") (unspec_volatile:GPR [(const_int 0)] UNSPEC_STORE_CONDITIONAL)) @@ -137,6 +152,25 @@ "sc.%A3 %0, %z2, %1" ) +;; This pattern allows to consume a sign-extension of the success +;; value of SC.W, which can then be used for instructions which +;; require values of XLEN-size (e.g. conditional branches). +;; This is legal, because any non-zero value remains non-zero +;; after sign-extension. + +(define_insn "riscv_store_conditional" + [(set (match_operand:DI 0 "register_operand" "=&r") + (sign_extend:DI + (unspec_volatile:SI [(const_int 0)] UNSPEC_STORE_CONDITIONAL))) + (set (match_operand:SI 1 "memory_operand" "=A") + (unspec_volatile:SI + [(match_operand:SI 2 "reg_or_0_operand" "rJ") + (match_operand:SI 3 "const_int_operand")] ;; model + UNSPEC_STORE_CONDITIONAL))] + "TARGET_ATOMIC && TARGET_64BIT" + "sc.w%A3 %0, %z2, %1" +) + (define_insn "atomic_" [(set (match_operand:GPR 0 "memory_operand" "+A") (unspec_volatile:GPR