[v2,07/10] RISC-V: Model INSNs for LR and SC [PR 100266]

Message ID	20210505193651.2075405-8-cmuellner@gcc.gnu.org
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Headers	show Return-Path: <gcc-patches-bounces@gcc.gnu.org> DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 16FEA3A4E874 To: gcc-patches@gcc.gnu.org Subject: [PATCH v2 07/10] RISC-V: Model INSNs for LR and SC [PR 100266] Date: Wed, 5 May 2021 21:36:48 +0200 Message-Id: <20210505193651.2075405-8-cmuellner@gcc.gnu.org> In-Reply-To: <20210505193651.2075405-1-cmuellner@gcc.gnu.org> References: <20210505193651.2075405-1-cmuellner@gcc.gnu.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: list From: Christoph Muellner via Gcc-patches <gcc-patches@gcc.gnu.org> Reply-To: Christoph Muellner <cmuellner@gcc.gnu.org> Cc: Kito Cheng <kito.cheng@sifive.com> Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" <gcc-patches-bounces@gcc.gnu.org>
Series	Atomics improvements [PR100265/PR100266] \| expand [v2,00/10,RISC-V] Atomics improvements [PR100265/PR100266] [v2,01/10] RISC-V: Simplify memory model code [PR 100265] [v2,02/10] RISC-V: Emit proper memory ordering suffixes for AMOs [PR 100265] [v2,03/10] RISC-V: Eliminate %F specifier from riscv_print_operand() [PR 100265] [v2,04/10] RISC-V: Use STORE instead of AMOSWAP for atomic stores [PR 100265] [v2,05/10] RISC-V: Emit fences according to chosen memory model [PR 100265] [v2,06/10] RISC-V: Implement atomic_{load,store} [PR 100265] [v2,07/10] RISC-V: Model INSNs for LR and SC [PR 100266] [v2,08/10] RISC-V: Add s.ext-consuming INSNs for LR and SC [PR 100266] [v2,09/10] RISC-V: Provide programmatic implementation of CAS [PR 100266] [v2,10/10] RISC-V: Introduce predicate "riscv_sync_memory_operand" [PR 100266]

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20210505193651.2075405-8-cmuellner@gcc.gnu.org

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DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 16FEA3A4E874
To: gcc-patches@gcc.gnu.org
Subject: [PATCH v2 07/10] RISC-V: Model INSNs for LR and SC [PR 100266]
Date: Wed,  5 May 2021 21:36:48 +0200
Message-Id: <20210505193651.2075405-8-cmuellner@gcc.gnu.org>
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From: Christoph Muellner via Gcc-patches <gcc-patches@gcc.gnu.org>
Reply-To: Christoph Muellner <cmuellner@gcc.gnu.org>
Cc: Kito Cheng <kito.cheng@sifive.com>
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Series

Atomics improvements [PR100265/PR100266] | expand

Commit Message

Christoph Müllner May 5, 2021, 7:36 p.m. UTC

In order to emit LR/SC sequences, let's provide INSNs, which
take care of memory ordering constraints.

    gcc/
        PR 100266
        * config/rsicv/sync.md (UNSPEC_LOAD_RESERVED): New.
        * config/rsicv/sync.md (UNSPEC_STORE_CONDITIONAL): New.
        * config/riscv/sync.md (riscv_load_reserved): New.
        * config/riscv/sync.md (riscv_store_conditional): New.
---
 gcc/config/riscv/sync.md | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md
index ceec324dfa30..edff6520b87e 100644
--- a/gcc/config/riscv/sync.md
+++ b/gcc/config/riscv/sync.md
@@ -26,6 +26,8 @@ 
   UNSPEC_ATOMIC_LOAD
   UNSPEC_ATOMIC_STORE
   UNSPEC_MEMORY_BARRIER
+  UNSPEC_LOAD_RESERVED
+  UNSPEC_STORE_CONDITIONAL
 ])
 
 (define_code_iterator any_atomic [plus ior xor and])
@@ -113,6 +115,28 @@ 
     DONE;
 })
 
+(define_insn "@riscv_load_reserved<mode>"
+  [(set (match_operand:GPR 0 "register_operand" "=r")
+    (unspec_volatile:GPR
+      [(match_operand:GPR 1 "memory_operand" "A")
+       (match_operand:SI 2 "const_int_operand")]      ;; model
+      UNSPEC_LOAD_RESERVED))]
+  "TARGET_ATOMIC"
+  "lr.<amo>%A2 %0, %1"
+)
+
+(define_insn "@riscv_store_conditional<mode>"
+  [(set (match_operand:GPR 0 "register_operand" "=&r")
+    (unspec_volatile:GPR [(const_int 0)] UNSPEC_STORE_CONDITIONAL))
+   (set (match_operand:GPR 1 "memory_operand" "=A")
+    (unspec_volatile:GPR
+      [(match_operand:GPR 2 "reg_or_0_operand" "rJ")
+       (match_operand:SI 3 "const_int_operand")]      ;; model
+      UNSPEC_STORE_CONDITIONAL))]
+  "TARGET_ATOMIC"
+  "sc.<amo>%A3 %0, %z2, %1"
+)
+
 (define_insn "atomic_<atomic_optab><mode>"
   [(set (match_operand:GPR 0 "memory_operand" "+A")
 	(unspec_volatile:GPR

[v2,07/10] RISC-V: Model INSNs for LR and SC [PR 100266]

Commit Message

Patch