diff mbox series

aarch64: Fix up *add<mode>3_poly_1 [PR99813]

Message ID 20210330201934.GN1179226@tucnak
State New
Headers show
Series aarch64: Fix up *add<mode>3_poly_1 [PR99813] | expand

Commit Message

Jakub Jelinek March 30, 2021, 8:19 p.m. UTC
Hi!

As mentioned in the PR, Uai constraint stands for
aarch64_sve_scalar_inc_dec_immediate
while Uav for
aarch64_sve_addvl_addpl_immediate.
Both *add<mode>3_aarch64 and *add<mode>3_poly_1 patterns use
  * return aarch64_output_sve_scalar_inc_dec (operands[2]);
  * return aarch64_output_sve_addvl_addpl (operands[2]);
in that order, but the former with Uai,Uav order, while the
latter with Uav,Uai instead.  This patch swaps the constraints
so that they match the output.

Bootstrapped/regtested on aarch64-linux, ok for trunk?

2021-03-30  Jakub Jelinek  <jakub@redhat.com>
	    Richard Sandiford  <richard.sandiford@arm.com>

	PR target/99813
	* config/aarch64/aarch64.md (*add<mode>3_poly_1): Swap Uai and Uav
	constraints on operands[2] and similarly 0 and rk constraints
	on operands[1] corresponding to that.

	* g++.target/aarch64/sve/pr99813.C: New test.


	Jakub

Comments

Richard Sandiford March 31, 2021, 8:42 a.m. UTC | #1
Jakub Jelinek <jakub@redhat.com> writes:
> Hi!
>
> As mentioned in the PR, Uai constraint stands for
> aarch64_sve_scalar_inc_dec_immediate
> while Uav for
> aarch64_sve_addvl_addpl_immediate.
> Both *add<mode>3_aarch64 and *add<mode>3_poly_1 patterns use
>   * return aarch64_output_sve_scalar_inc_dec (operands[2]);
>   * return aarch64_output_sve_addvl_addpl (operands[2]);
> in that order, but the former with Uai,Uav order, while the
> latter with Uav,Uai instead.  This patch swaps the constraints
> so that they match the output.
>
> Bootstrapped/regtested on aarch64-linux, ok for trunk?

OK, thanks.

Richard

> 2021-03-30  Jakub Jelinek  <jakub@redhat.com>
> 	    Richard Sandiford  <richard.sandiford@arm.com>
>
> 	PR target/99813
> 	* config/aarch64/aarch64.md (*add<mode>3_poly_1): Swap Uai and Uav
> 	constraints on operands[2] and similarly 0 and rk constraints
> 	on operands[1] corresponding to that.
>
> 	* g++.target/aarch64/sve/pr99813.C: New test.
>
> --- gcc/config/aarch64/aarch64.md.jj	2021-02-25 23:07:07.851319165 +0100
> +++ gcc/config/aarch64/aarch64.md	2021-03-30 11:13:35.994077470 +0200
> @@ -2050,8 +2050,8 @@
>    [(set
>      (match_operand:GPI 0 "register_operand" "=r,r,r,r,r,r,&r")
>      (plus:GPI
> -     (match_operand:GPI 1 "register_operand" "%rk,rk,rk,rk,rk,0,rk")
> -     (match_operand:GPI 2 "aarch64_pluslong_or_poly_operand" "I,r,J,Uaa,Uav,Uai,Uat")))]
> +     (match_operand:GPI 1 "register_operand" "%rk,rk,rk,rk,0,rk,rk")
> +     (match_operand:GPI 2 "aarch64_pluslong_or_poly_operand" "I,r,J,Uaa,Uai,Uav,Uat")))]
>    "TARGET_SVE && operands[0] != stack_pointer_rtx"
>    "@
>    add\\t%<w>0, %<w>1, %2
> --- gcc/testsuite/g++.target/aarch64/sve/pr99813.C.jj	2021-03-30 11:22:13.430290522 +0200
> +++ gcc/testsuite/g++.target/aarch64/sve/pr99813.C	2021-03-30 11:22:55.526819721 +0200
> @@ -0,0 +1,27 @@
> +// PR target/99813
> +/* { dg-do assemble { target aarch64_asm_sve_ok } } */
> +/* { dg-options "-O3 -march=armv8.2-a+sve -fvect-cost-model=unlimited -fno-tree-dominator-opts -mtune=cortex-a72" } */
> +
> +long a, b;
> +bool c[2][14][2][16], f[2][14][2][16];
> +bool d;
> +char e[2][4][2][6];
> +void g() {
> +  a = 0;
> +  for (int h = 0; h < 2; ++h)
> +    for (int i = 0; i < 14; ++i)
> +      for (int j = 0; j < 2; ++j)
> +        for (int k = 0; k < 16; ++k)
> +          c[h][i][j][k] = 0;
> +  d = 0;
> +  for (int h; h < 2; ++h)
> +    for (int i = 0; i < 4; ++i)
> +      for (int j = 0; j < 2; ++j)
> +        for (int k = 0; k < 6; ++k)
> +          e[h][i][j][k] = 6;
> +  for (int h = 0; h < 2; ++h)
> +    for (int i = 0; i < 14; ++i)
> +      for (int j = 0; j < 2; ++j)
> +        for (int k = 0; k < 16; ++k)
> +          f[h][i][j][k] = b = 9;
> +}
>
> 	Jakub
diff mbox series

Patch

--- gcc/config/aarch64/aarch64.md.jj	2021-02-25 23:07:07.851319165 +0100
+++ gcc/config/aarch64/aarch64.md	2021-03-30 11:13:35.994077470 +0200
@@ -2050,8 +2050,8 @@ 
   [(set
     (match_operand:GPI 0 "register_operand" "=r,r,r,r,r,r,&r")
     (plus:GPI
-     (match_operand:GPI 1 "register_operand" "%rk,rk,rk,rk,rk,0,rk")
-     (match_operand:GPI 2 "aarch64_pluslong_or_poly_operand" "I,r,J,Uaa,Uav,Uai,Uat")))]
+     (match_operand:GPI 1 "register_operand" "%rk,rk,rk,rk,0,rk,rk")
+     (match_operand:GPI 2 "aarch64_pluslong_or_poly_operand" "I,r,J,Uaa,Uai,Uav,Uat")))]
   "TARGET_SVE && operands[0] != stack_pointer_rtx"
   "@
   add\\t%<w>0, %<w>1, %2
--- gcc/testsuite/g++.target/aarch64/sve/pr99813.C.jj	2021-03-30 11:22:13.430290522 +0200
+++ gcc/testsuite/g++.target/aarch64/sve/pr99813.C	2021-03-30 11:22:55.526819721 +0200
@@ -0,0 +1,27 @@ 
+// PR target/99813
+/* { dg-do assemble { target aarch64_asm_sve_ok } } */
+/* { dg-options "-O3 -march=armv8.2-a+sve -fvect-cost-model=unlimited -fno-tree-dominator-opts -mtune=cortex-a72" } */
+
+long a, b;
+bool c[2][14][2][16], f[2][14][2][16];
+bool d;
+char e[2][4][2][6];
+void g() {
+  a = 0;
+  for (int h = 0; h < 2; ++h)
+    for (int i = 0; i < 14; ++i)
+      for (int j = 0; j < 2; ++j)
+        for (int k = 0; k < 16; ++k)
+          c[h][i][j][k] = 0;
+  d = 0;
+  for (int h; h < 2; ++h)
+    for (int i = 0; i < 4; ++i)
+      for (int j = 0; j < 2; ++j)
+        for (int k = 0; k < 6; ++k)
+          e[h][i][j][k] = 6;
+  for (int h = 0; h < 2; ++h)
+    for (int i = 0; i < 14; ++i)
+      for (int j = 0; j < 2; ++j)
+        for (int k = 0; k < 16; ++k)
+          f[h][i][j][k] = b = 9;
+}