| Message ID | 20201025112001.GC15956@bubble.grove.modra.org |
|---|---|
| State | New |
| Headers | show |
| Series | [RS6000] Tests that use int128_t and -m32 | expand |
On Sun, Oct 25, 2020 at 7:20 AM Alan Modra <amodra@gmail.com> wrote: > > All these tests fail with -m32 due to lack of int128 support, in some > cases with what I thought was not the best error message. For example > vsx_mask-move-runnable.c:34:3: error: unknown type name 'vector' > is misleading. The problem isn't "vector" but "vector __uint128_t". > > * gcc.target/powerpc/vsx-load-element-extend-char.c: Require int128. > * gcc.target/powerpc/vsx-load-element-extend-int.c: Likewise. > * gcc.target/powerpc/vsx-load-element-extend-longlong.c: Likewise. > * gcc.target/powerpc/vsx-load-element-extend-short.c: Likewise. > * gcc.target/powerpc/vsx-store-element-truncate-char.c: Likewise. > * gcc.target/powerpc/vsx-store-element-truncate-int.c: Likewise. > * gcc.target/powerpc/vsx-store-element-truncate-longlong.c: Likewise. > * gcc.target/powerpc/vsx-store-element-truncate-short.c: Likewise. > * gcc.target/powerpc/vsx_mask-count-runnable.c: Likewise. > * gcc.target/powerpc/vsx_mask-expand-runnable.c: Likewise. > * gcc.target/powerpc/vsx_mask-extract-runnable.c: Likewise. > * gcc.target/powerpc/vsx_mask-move-runnable.c: Likewise. Good catch. Another problem with all of the vsx_mask test cases is that they use -mcpu=power10 instead of -mdejagnu-cpu=power10. Can you follow up with that fix or do you want me to? Thanks, David > > diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-char.c b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-char.c > index 0b8cfd610f8..7a7cb77c3a0 100644 > --- a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-char.c > +++ b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-char.c > @@ -4,6 +4,7 @@ > > /* { dg-do compile {target power10_ok} } */ > /* { dg-do run {target power10_hw} } */ > +/* { dg-require-effective-target { int128 } } */ > /* { dg-options "-mdejagnu-cpu=power10 -O3" } */ > > /* At the time of writing, the number of lxvrbx instructions is > diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-int.c b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-int.c > index b10d3cb43d2..414678c9461 100644 > --- a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-int.c > +++ b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-int.c > @@ -4,6 +4,7 @@ > > /* { dg-do compile {target power10_ok} } */ > /* { dg-do run {target power10_hw} } */ > +/* { dg-require-effective-target { int128 } } */ > > /* Deliberately set optization to zero for this test to confirm > the lxvr*x instruction is generated. At higher optimization levels > diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-longlong.c b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-longlong.c > index 52fcf2e572f..c1e3ebc25ca 100644 > --- a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-longlong.c > +++ b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-longlong.c > @@ -4,6 +4,7 @@ > > /* { dg-do compile {target power10_ok} } */ > /* { dg-do run {target power10_hw} } */ > +/* { dg-require-effective-target { int128 } } */ > /* { dg-options "-mdejagnu-cpu=power10 -O3" } */ > > /* At time of writing, we also geenerate a .constrprop copy > diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-short.c b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-short.c > index 8fc0cc66eb7..698ba30c6f8 100644 > --- a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-short.c > +++ b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-short.c > @@ -4,6 +4,7 @@ > > /* { dg-do compile {target power10_ok} } */ > /* { dg-do run {target power10_hw} } */ > +/* { dg-require-effective-target { int128 } } */ > > /* Deliberately set optization to zero for this test to confirm > the lxvr*x instruction is generated. At higher optimization levels > diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-char.c b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-char.c > index 99f3904983b..53fc2cc9bae 100644 > --- a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-char.c > +++ b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-char.c > @@ -3,6 +3,7 @@ > > /* { dg-do compile {target power10_ok} } */ > /* { dg-do run {target power10_hw} } */ > +/* { dg-require-effective-target { int128 } } */ > /* Deliberately set optization to zero for this test to confirm > the stxvr*x instruction is generated. At higher optimization levels > the instruction we are looking for is sometimes replaced by other > diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-int.c b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-int.c > index 6e2acf83c38..4c64b413e16 100644 > --- a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-int.c > +++ b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-int.c > @@ -3,6 +3,7 @@ > > /* { dg-do compile {target power10_ok} } */ > /* { dg-do run {target power10_hw} } */ > +/* { dg-require-effective-target { int128 } } */ > /* Deliberately set optization to zero for this test to confirm > the stxvr*x instruction is generated. At higher optimization levels > the instruction we are looking for is sometimes replaced by other > diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-longlong.c b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-longlong.c > index 7fce6a44d4f..465fbeaf6ab 100644 > --- a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-longlong.c > +++ b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-longlong.c > @@ -3,6 +3,7 @@ > > /* { dg-do compile {target power10_ok} } */ > /* { dg-do run {target power10_hw} } */ > +/* { dg-require-effective-target { int128 } } */ > > /* Deliberately set optization to zero for this test to confirm > the stxvr*x instruction is generated. At higher optimization levels > diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-short.c b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-short.c > index 17925c87732..f87256921bf 100644 > --- a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-short.c > +++ b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-short.c > @@ -3,6 +3,7 @@ > > /* { dg-do compile {target power10_ok} } */ > /* { dg-do run {target power10_hw} } */ > +/* { dg-require-effective-target { int128 } } */ > > /* Deliberately set optization to zero for this test to confirm > the stxvr*x instruction is generated. At higher optimization levels > diff --git a/gcc/testsuite/gcc.target/powerpc/vsx_mask-count-runnable.c b/gcc/testsuite/gcc.target/powerpc/vsx_mask-count-runnable.c > index 5862517eae9..6ac4ed2173f 100644 > --- a/gcc/testsuite/gcc.target/powerpc/vsx_mask-count-runnable.c > +++ b/gcc/testsuite/gcc.target/powerpc/vsx_mask-count-runnable.c > @@ -1,7 +1,7 @@ > /* { dg-do run { target { power10_hw } } } */ > /* { dg-do link { target { ! power10_hw } } } */ > /* { dg-options "-mcpu=power10 -O2" } */ > -/* { dg-require-effective-target power10_ok } */ > +/* { dg-require-effective-target { int128 && power10_ok } } */ > > /* Check that the expected 128-bit instructions are generated if the processor > supports the 128-bit integer instructions. */ > diff --git a/gcc/testsuite/gcc.target/powerpc/vsx_mask-expand-runnable.c b/gcc/testsuite/gcc.target/powerpc/vsx_mask-expand-runnable.c > index 13b4c8afd4f..05fedf77eb9 100644 > --- a/gcc/testsuite/gcc.target/powerpc/vsx_mask-expand-runnable.c > +++ b/gcc/testsuite/gcc.target/powerpc/vsx_mask-expand-runnable.c > @@ -1,7 +1,7 @@ > /* { dg-do run { target { power10_hw } } } */ > /* { dg-do link { target { ! power10_hw } } } */ > /* { dg-options "-mcpu=power10 -O2" } */ > -/* { dg-require-effective-target power10_ok } */ > +/* { dg-require-effective-target { int128 && power10_ok } } */ > > /* Check that the expected 128-bit instructions are generated if the processor > supports the 128-bit integer instructions. */ > diff --git a/gcc/testsuite/gcc.target/powerpc/vsx_mask-extract-runnable.c b/gcc/testsuite/gcc.target/powerpc/vsx_mask-extract-runnable.c > index d58a6b0b682..6e952695905 100644 > --- a/gcc/testsuite/gcc.target/powerpc/vsx_mask-extract-runnable.c > +++ b/gcc/testsuite/gcc.target/powerpc/vsx_mask-extract-runnable.c > @@ -1,7 +1,7 @@ > /* { dg-do run { target { power10_hw } } } */ > /* { dg-do link { target { ! power10_hw } } } */ > /* { dg-options "-mcpu=power10 -O2" } */ > -/* { dg-require-effective-target power10_ok } */ > +/* { dg-require-effective-target { int128 && power10_ok } } */ > > /* Check that the expected 128-bit instructions are generated if the processor > supports the 128-bit integer instructions. */ > diff --git a/gcc/testsuite/gcc.target/powerpc/vsx_mask-move-runnable.c b/gcc/testsuite/gcc.target/powerpc/vsx_mask-move-runnable.c > index 9147d67c9d1..c2eb53d3bb2 100644 > --- a/gcc/testsuite/gcc.target/powerpc/vsx_mask-move-runnable.c > +++ b/gcc/testsuite/gcc.target/powerpc/vsx_mask-move-runnable.c > @@ -1,7 +1,7 @@ > /* { dg-do run { target { power10_hw } } } */ > /* { dg-do link { target { ! power10_hw } } } */ > /* { dg-options "-mcpu=power10 -O2" } */ > -/* { dg-require-effective-target power10_ok } */ > +/* { dg-require-effective-target { int128 && power10_ok } } */ > > /* Check that the expected 128-bit instructions are generated if the processor > supports the 128-bit integer instructions. */ > > -- > Alan Modra > Australia Development Lab, IBM
On Sun, Oct 25, 2020 at 10:43:12AM -0400, David Edelsohn wrote: > On Sun, Oct 25, 2020 at 7:20 AM Alan Modra <amodra@gmail.com> wrote: > > > > All these tests fail with -m32 due to lack of int128 support, in some > > cases with what I thought was not the best error message. For example > > vsx_mask-move-runnable.c:34:3: error: unknown type name 'vector' > > is misleading. The problem isn't "vector" but "vector __uint128_t". > > > > * gcc.target/powerpc/vsx-load-element-extend-char.c: Require int128. > > * gcc.target/powerpc/vsx-load-element-extend-int.c: Likewise. > > * gcc.target/powerpc/vsx-load-element-extend-longlong.c: Likewise. > > * gcc.target/powerpc/vsx-load-element-extend-short.c: Likewise. > > * gcc.target/powerpc/vsx-store-element-truncate-char.c: Likewise. > > * gcc.target/powerpc/vsx-store-element-truncate-int.c: Likewise. > > * gcc.target/powerpc/vsx-store-element-truncate-longlong.c: Likewise. > > * gcc.target/powerpc/vsx-store-element-truncate-short.c: Likewise. > > * gcc.target/powerpc/vsx_mask-count-runnable.c: Likewise. > > * gcc.target/powerpc/vsx_mask-expand-runnable.c: Likewise. > > * gcc.target/powerpc/vsx_mask-extract-runnable.c: Likewise. > > * gcc.target/powerpc/vsx_mask-move-runnable.c: Likewise. > > Good catch. > > Another problem with all of the vsx_mask test cases is that they use > -mcpu=power10 instead of -mdejagnu-cpu=power10. Can you follow up > with that fix or do you want me to? Sure, I can do that if you're pre-approving the patch. gcc.target/powerpc/pr93122.c too.
Hi Alan, On Sun, Oct 25, 2020 at 09:50:01PM +1030, Alan Modra wrote: > All these tests fail with -m32 due to lack of int128 support, Is there any good reason __int128 is not enabled for rs6000 -m32, btw? > in some > cases with what I thought was not the best error message. For example > vsx_mask-move-runnable.c:34:3: error: unknown type name 'vector' > is misleading. The problem isn't "vector" but "vector __uint128_t". Ouch, yes. Do you see a simple way to fix that? > diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-char.c b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-char.c > index 0b8cfd610f8..7a7cb77c3a0 100644 > --- a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-char.c > +++ b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-char.c > @@ -4,6 +4,7 @@ > > /* { dg-do compile {target power10_ok} } */ > /* { dg-do run {target power10_hw} } */ > +/* { dg-require-effective-target { int128 } } */ > /* { dg-options "-mdejagnu-cpu=power10 -O3" } */ You might want to write this as {int128}, to keep the same style as the other statements. Or leave off the braces completely, they aren't necessary here, int128 is a single word :-) > diff --git a/gcc/testsuite/gcc.target/powerpc/vsx_mask-count-runnable.c b/gcc/testsuite/gcc.target/powerpc/vsx_mask-count-runnable.c > index 5862517eae9..6ac4ed2173f 100644 > --- a/gcc/testsuite/gcc.target/powerpc/vsx_mask-count-runnable.c > +++ b/gcc/testsuite/gcc.target/powerpc/vsx_mask-count-runnable.c > @@ -1,7 +1,7 @@ > /* { dg-do run { target { power10_hw } } } */ > /* { dg-do link { target { ! power10_hw } } } */ > /* { dg-options "-mcpu=power10 -O2" } */ > -/* { dg-require-effective-target power10_ok } */ > +/* { dg-require-effective-target { int128 && power10_ok } } */ Or write it as two require statements, as we do most of the time? Okay for trunk (with those tweaks if you want). Thanks! Segher
On Mon, Oct 26, 2020 at 10:34:20PM +1030, Alan Modra wrote: > On Sun, Oct 25, 2020 at 10:43:12AM -0400, David Edelsohn wrote: > > Another problem with all of the vsx_mask test cases is that they use > > -mcpu=power10 instead of -mdejagnu-cpu=power10. Can you follow up > > with that fix or do you want me to? > > Sure, I can do that if you're pre-approving the patch. > gcc.target/powerpc/pr93122.c too. This is obvious and trivial, doesn't need approval (just send a mail what you did). Thanks :-) Segher
On Mon, Oct 26, 2020 at 07:33:49AM -0500, Segher Boessenkool wrote: > On Sun, Oct 25, 2020 at 09:50:01PM +1030, Alan Modra wrote: > > All these tests fail with -m32 due to lack of int128 support, > > Is there any good reason __int128 is not enabled for rs6000 -m32, btw? Lack of addti3 and subti3 perhaps? > > in some > > cases with what I thought was not the best error message. For example > > vsx_mask-move-runnable.c:34:3: error: unknown type name 'vector' > > is misleading. The problem isn't "vector" but "vector __uint128_t". > > Ouch, yes. Do you see a simple way to fix that? I haven't looked. The only reason I commented on the error was in the hope that someone who knows gcc intimately enough to fix this without much effort would do so. :-)
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-char.c b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-char.c index 0b8cfd610f8..7a7cb77c3a0 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-char.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-char.c @@ -4,6 +4,7 @@ /* { dg-do compile {target power10_ok} } */ /* { dg-do run {target power10_hw} } */ +/* { dg-require-effective-target { int128 } } */ /* { dg-options "-mdejagnu-cpu=power10 -O3" } */ /* At the time of writing, the number of lxvrbx instructions is diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-int.c b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-int.c index b10d3cb43d2..414678c9461 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-int.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-int.c @@ -4,6 +4,7 @@ /* { dg-do compile {target power10_ok} } */ /* { dg-do run {target power10_hw} } */ +/* { dg-require-effective-target { int128 } } */ /* Deliberately set optization to zero for this test to confirm the lxvr*x instruction is generated. At higher optimization levels diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-longlong.c b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-longlong.c index 52fcf2e572f..c1e3ebc25ca 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-longlong.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-longlong.c @@ -4,6 +4,7 @@ /* { dg-do compile {target power10_ok} } */ /* { dg-do run {target power10_hw} } */ +/* { dg-require-effective-target { int128 } } */ /* { dg-options "-mdejagnu-cpu=power10 -O3" } */ /* At time of writing, we also geenerate a .constrprop copy diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-short.c b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-short.c index 8fc0cc66eb7..698ba30c6f8 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-short.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-short.c @@ -4,6 +4,7 @@ /* { dg-do compile {target power10_ok} } */ /* { dg-do run {target power10_hw} } */ +/* { dg-require-effective-target { int128 } } */ /* Deliberately set optization to zero for this test to confirm the lxvr*x instruction is generated. At higher optimization levels diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-char.c b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-char.c index 99f3904983b..53fc2cc9bae 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-char.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-char.c @@ -3,6 +3,7 @@ /* { dg-do compile {target power10_ok} } */ /* { dg-do run {target power10_hw} } */ +/* { dg-require-effective-target { int128 } } */ /* Deliberately set optization to zero for this test to confirm the stxvr*x instruction is generated. At higher optimization levels the instruction we are looking for is sometimes replaced by other diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-int.c b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-int.c index 6e2acf83c38..4c64b413e16 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-int.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-int.c @@ -3,6 +3,7 @@ /* { dg-do compile {target power10_ok} } */ /* { dg-do run {target power10_hw} } */ +/* { dg-require-effective-target { int128 } } */ /* Deliberately set optization to zero for this test to confirm the stxvr*x instruction is generated. At higher optimization levels the instruction we are looking for is sometimes replaced by other diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-longlong.c b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-longlong.c index 7fce6a44d4f..465fbeaf6ab 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-longlong.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-longlong.c @@ -3,6 +3,7 @@ /* { dg-do compile {target power10_ok} } */ /* { dg-do run {target power10_hw} } */ +/* { dg-require-effective-target { int128 } } */ /* Deliberately set optization to zero for this test to confirm the stxvr*x instruction is generated. At higher optimization levels diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-short.c b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-short.c index 17925c87732..f87256921bf 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-short.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-short.c @@ -3,6 +3,7 @@ /* { dg-do compile {target power10_ok} } */ /* { dg-do run {target power10_hw} } */ +/* { dg-require-effective-target { int128 } } */ /* Deliberately set optization to zero for this test to confirm the stxvr*x instruction is generated. At higher optimization levels diff --git a/gcc/testsuite/gcc.target/powerpc/vsx_mask-count-runnable.c b/gcc/testsuite/gcc.target/powerpc/vsx_mask-count-runnable.c index 5862517eae9..6ac4ed2173f 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx_mask-count-runnable.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx_mask-count-runnable.c @@ -1,7 +1,7 @@ /* { dg-do run { target { power10_hw } } } */ /* { dg-do link { target { ! power10_hw } } } */ /* { dg-options "-mcpu=power10 -O2" } */ -/* { dg-require-effective-target power10_ok } */ +/* { dg-require-effective-target { int128 && power10_ok } } */ /* Check that the expected 128-bit instructions are generated if the processor supports the 128-bit integer instructions. */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx_mask-expand-runnable.c b/gcc/testsuite/gcc.target/powerpc/vsx_mask-expand-runnable.c index 13b4c8afd4f..05fedf77eb9 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx_mask-expand-runnable.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx_mask-expand-runnable.c @@ -1,7 +1,7 @@ /* { dg-do run { target { power10_hw } } } */ /* { dg-do link { target { ! power10_hw } } } */ /* { dg-options "-mcpu=power10 -O2" } */ -/* { dg-require-effective-target power10_ok } */ +/* { dg-require-effective-target { int128 && power10_ok } } */ /* Check that the expected 128-bit instructions are generated if the processor supports the 128-bit integer instructions. */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx_mask-extract-runnable.c b/gcc/testsuite/gcc.target/powerpc/vsx_mask-extract-runnable.c index d58a6b0b682..6e952695905 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx_mask-extract-runnable.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx_mask-extract-runnable.c @@ -1,7 +1,7 @@ /* { dg-do run { target { power10_hw } } } */ /* { dg-do link { target { ! power10_hw } } } */ /* { dg-options "-mcpu=power10 -O2" } */ -/* { dg-require-effective-target power10_ok } */ +/* { dg-require-effective-target { int128 && power10_ok } } */ /* Check that the expected 128-bit instructions are generated if the processor supports the 128-bit integer instructions. */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx_mask-move-runnable.c b/gcc/testsuite/gcc.target/powerpc/vsx_mask-move-runnable.c index 9147d67c9d1..c2eb53d3bb2 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx_mask-move-runnable.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx_mask-move-runnable.c @@ -1,7 +1,7 @@ /* { dg-do run { target { power10_hw } } } */ /* { dg-do link { target { ! power10_hw } } } */ /* { dg-options "-mcpu=power10 -O2" } */ -/* { dg-require-effective-target power10_ok } */ +/* { dg-require-effective-target { int128 && power10_ok } } */ /* Check that the expected 128-bit instructions are generated if the processor supports the 128-bit integer instructions. */