diff mbox series

[committed,nvptx] Split up function ref plus const

Message ID 20200923204633.GA6056@delia
State New
Headers show
Series [committed,nvptx] Split up function ref plus const | expand

Commit Message

Tom de Vries Sept. 23, 2020, 8:46 p.m. UTC
Hi,

With test-case gcc.c-torture/compile/pr92231.c, we run into:
...
nvptx-as: ptxas terminated with signal 11 [Segmentation fault], core dumped^M
compiler exited with status 1
FAIL: gcc.c-torture/compile/pr92231.c   -O0  (test for excess errors)
...
due to using a function reference plus constant as operand:
...
  mov.u64 %r24,bar+4096';
...

Fix this by splitting such an insn into:
...
  mov.u64 %r24,bar';
  add.u64 %r24,%r24,4096';
...

Tested on nvptx.

Committed to trunk.

Thanks,
- Tom

[nvptx] Split up function ref plus const

gcc/ChangeLog:

	* config/nvptx/nvptx.md: Don't allow operand containing sum of
	function ref and const.

---
 gcc/config/nvptx/nvptx.md | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

Comments

Thomas Schwinge Oct. 9, 2020, 9:03 a.m. UTC | #1
Hi Tom!

On 2020-09-23T22:46:34+0200, Tom de Vries <tdevries@suse.de> wrote:
> With test-case gcc.c-torture/compile/pr92231.c, we run into:

"Interesting" testcase...  ;-)

> ...
> nvptx-as: ptxas terminated with signal 11 [Segmentation fault], core dumped^M

Confirmed with:

    $ ptxas --version
    ptxas: NVIDIA (R) Ptx optimizing assembler
    Copyright (c) 2005-2014 NVIDIA Corporation
    Built on Thu_Jul_17_21:41:15_CDT_2014
    Cuda compilation tools, release 6.5, V6.5.12

..., and:

    $ ptxas --version
    ptxas: NVIDIA (R) Ptx optimizing assembler
    Copyright (c) 2005-2017 NVIDIA Corporation
    Built on Fri_Dec__1_00:57:38_CST_2017
    Cuda compilation tools, release 9.1, V9.1.108

Have you reported this to Nvidia?

> compiler exited with status 1
> FAIL: gcc.c-torture/compile/pr92231.c   -O0  (test for excess errors)
> ...
> due to using a function reference plus constant as operand:
> ...
>   mov.u64 %r24,bar+4096';
> ...
>
> Fix this by splitting such an insn into:
> ...
>   mov.u64 %r24,bar';
>   add.u64 %r24,%r24,4096';
> ...

(Spurious single-quote characters in PTX code?)


Grüße
 Thomas


> Tested on nvptx.
>
> Committed to trunk.
>
> Thanks,
> - Tom
>
> [nvptx] Split up function ref plus const
>
> gcc/ChangeLog:
>
>       * config/nvptx/nvptx.md: Don't allow operand containing sum of
>       function ref and const.
>
> ---
>  gcc/config/nvptx/nvptx.md | 18 ++++++++++++++++++
>  1 file changed, 18 insertions(+)
>
> diff --git a/gcc/config/nvptx/nvptx.md b/gcc/config/nvptx/nvptx.md
> index 6178e6a0f77..035f6e0151b 100644
> --- a/gcc/config/nvptx/nvptx.md
> +++ b/gcc/config/nvptx/nvptx.md
> @@ -146,6 +146,13 @@
>    return true;
>  })
>
> +;; Test for a function symbol ref operand
> +(define_predicate "symbol_ref_function_operand"
> +  (match_code "symbol_ref")
> +{
> +  return SYMBOL_REF_FUNCTION_P (op);
> +})
> +
>  (define_attr "predicable" "false,true"
>    (const_string "true"))
>
> @@ -241,6 +248,17 @@
>  }
>    [(set_attr "subregs_ok" "true")])
>
> +;; ptxas segfaults on 'mov.u64 %r24,bar+4096', so break it up.
> +(define_split
> +  [(set (match_operand:DI 0 "nvptx_register_operand")
> +     (const:DI (plus:DI (match_operand:DI 1 "symbol_ref_function_operand")
> +                        (match_operand 2 "const_int_operand"))))]
> +  ""
> +  [(set (match_dup 0) (match_dup 1))
> +   (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
> +  ]
> +  "")
> +
>  (define_insn "*mov<mode>_insn"
>    [(set (match_operand:SDFM 0 "nonimmediate_operand" "=R,R,m")
>       (match_operand:SDFM 1 "general_operand" "RF,m,R"))]
-----------------
Mentor Graphics (Deutschland) GmbH, Arnulfstraße 201, 80634 München / Germany
Registergericht München HRB 106955, Geschäftsführer: Thomas Heurung, Alexander Walter
Tom de Vries Oct. 9, 2020, 9:34 a.m. UTC | #2
On 10/9/20 11:03 AM, Thomas Schwinge wrote:
> Hi Tom!
> 
> On 2020-09-23T22:46:34+0200, Tom de Vries <tdevries@suse.de> wrote:
>> With test-case gcc.c-torture/compile/pr92231.c, we run into:
> 
> "Interesting" testcase...  ;-)
> 
>> ...
>> nvptx-as: ptxas terminated with signal 11 [Segmentation fault], core dumped^M
> 
> Confirmed with:
> 
>     $ ptxas --version
>     ptxas: NVIDIA (R) Ptx optimizing assembler
>     Copyright (c) 2005-2014 NVIDIA Corporation
>     Built on Thu_Jul_17_21:41:15_CDT_2014
>     Cuda compilation tools, release 6.5, V6.5.12
> 
> ..., and:
> 
>     $ ptxas --version
>     ptxas: NVIDIA (R) Ptx optimizing assembler
>     Copyright (c) 2005-2017 NVIDIA Corporation
>     Built on Fri_Dec__1_00:57:38_CST_2017
>     Cuda compilation tools, release 9.1, V9.1.108
> 
> Have you reported this to Nvidia?
> 

No, it's on my list to report, but I'm locked out from my nvidia account
for a while now, and nvidia remains unresponsive.

>> compiler exited with status 1
>> FAIL: gcc.c-torture/compile/pr92231.c   -O0  (test for excess errors)
>> ...
>> due to using a function reference plus constant as operand:
>> ...
>>   mov.u64 %r24,bar+4096';
>> ...
>>
>> Fix this by splitting such an insn into:
>> ...
>>   mov.u64 %r24,bar';
>>   add.u64 %r24,%r24,4096';
>> ...
> 
> (Spurious single-quote characters in PTX code?)
> 

Yeah, I think that was a copy-paste thing, the compiler DDRT.

Thanks,
- Tom
diff mbox series

Patch

diff --git a/gcc/config/nvptx/nvptx.md b/gcc/config/nvptx/nvptx.md
index 6178e6a0f77..035f6e0151b 100644
--- a/gcc/config/nvptx/nvptx.md
+++ b/gcc/config/nvptx/nvptx.md
@@ -146,6 +146,13 @@ 
   return true;
 })
 
+;; Test for a function symbol ref operand
+(define_predicate "symbol_ref_function_operand"
+  (match_code "symbol_ref")
+{
+  return SYMBOL_REF_FUNCTION_P (op);
+})
+
 (define_attr "predicable" "false,true"
   (const_string "true"))
 
@@ -241,6 +248,17 @@ 
 }
   [(set_attr "subregs_ok" "true")])
 
+;; ptxas segfaults on 'mov.u64 %r24,bar+4096', so break it up.
+(define_split
+  [(set (match_operand:DI 0 "nvptx_register_operand")
+	(const:DI (plus:DI (match_operand:DI 1 "symbol_ref_function_operand")
+			   (match_operand 2 "const_int_operand"))))]
+  ""
+  [(set (match_dup 0) (match_dup 1))
+   (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
+  ]
+  "")
+
 (define_insn "*mov<mode>_insn"
   [(set (match_operand:SDFM 0 "nonimmediate_operand" "=R,R,m")
 	(match_operand:SDFM 1 "general_operand" "RF,m,R"))]