| Message ID | 20200709095809.GA18602@arm.com |
|---|---|
| State | New |
| Headers | show |
| Series | [1/6] AArch64: Fix bugs in -mcpu=native detection. | expand |
> -----Original Message----- > From: Tamar Christina <Tamar.Christina@arm.com> > Sent: 09 July 2020 10:58 > To: gcc-patches@gcc.gnu.org > Cc: nd <nd@arm.com>; Richard Earnshaw <Richard.Earnshaw@arm.com>; > Marcus Shawcroft <Marcus.Shawcroft@arm.com>; Kyrylo Tkachov > <Kyrylo.Tkachov@arm.com>; Richard Sandiford > <Richard.Sandiford@arm.com> > Subject: [PATCH 6/6] AArch64: Add test for -mcpu=native > > Hi All, > > This adds some tests to the GCC testsuite for testing the > -mcpu=native code. > > Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. > > Ok for master, GCC 10, 9 and 8? > > Thanks, > Tamar > > gcc/testsuite/ChangeLog: > > * gcc.target/aarch64/cpunative/aarch64-cpunative.exp: New test. > * gcc.target/aarch64/cpunative/info_0: New test. > * gcc.target/aarch64/cpunative/info_1: New test. > * gcc.target/aarch64/cpunative/info_10: New test. > * gcc.target/aarch64/cpunative/info_11: New test. > * gcc.target/aarch64/cpunative/info_12: New test. > * gcc.target/aarch64/cpunative/info_13: New test. > * gcc.target/aarch64/cpunative/info_14: New test. > * gcc.target/aarch64/cpunative/info_15: New test. > * gcc.target/aarch64/cpunative/info_2: New test. > * gcc.target/aarch64/cpunative/info_3: New test. > * gcc.target/aarch64/cpunative/info_4: New test. > * gcc.target/aarch64/cpunative/info_5: New test. > * gcc.target/aarch64/cpunative/info_6: New test. > * gcc.target/aarch64/cpunative/info_7: New test. > * gcc.target/aarch64/cpunative/info_8: New test. > * gcc.target/aarch64/cpunative/info_9: New test. > * gcc.target/aarch64/cpunative/native_cpu_0.c: New test. > * gcc.target/aarch64/cpunative/native_cpu_1.c: New test. > * gcc.target/aarch64/cpunative/native_cpu_10.c: New test. > * gcc.target/aarch64/cpunative/native_cpu_11.c: New test. > * gcc.target/aarch64/cpunative/native_cpu_12.c: New test. > * gcc.target/aarch64/cpunative/native_cpu_13.c: New test. > * gcc.target/aarch64/cpunative/native_cpu_14.c: New test. > * gcc.target/aarch64/cpunative/native_cpu_15.c: New test. > * gcc.target/aarch64/cpunative/native_cpu_2.c: New test. > * gcc.target/aarch64/cpunative/native_cpu_3.c: New test. > * gcc.target/aarch64/cpunative/native_cpu_4.c: New test. > * gcc.target/aarch64/cpunative/native_cpu_5.c: New test. > * gcc.target/aarch64/cpunative/native_cpu_6.c: New test. > * gcc.target/aarch64/cpunative/native_cpu_7.c: New test. > * gcc.target/aarch64/cpunative/native_cpu_8.c: New test. > * gcc.target/aarch64/cpunative/native_cpu_9.c: New test. > > -- diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/aarch64-cpunative.exp b/gcc/testsuite/gcc.target/aarch64/cpunative/aarch64-cpunative.exp new file mode 100644 index 0000000000000000000000000000000000000000..ce80ca04b8d095c96acf0bda4d5b16a6460c4cbd --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/aarch64-cpunative.exp @@ -0,0 +1,35 @@ +# Copyright (C) 2014-2020 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# <http://www.gnu.org/licenses/>. + +# GCC testsuite that uses the `dg.exp' driver. + +# Exit immediately if this isn't an AArch64 target. +if ![istarget aarch64*-*-*] then { May as well add a test for native here to avoid going into the tests themselves? Ok either way with me. Thanks, Kyrill + return +} + +# Load support procs. +load_lib gcc-dg.exp
diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/aarch64-cpunative.exp b/gcc/testsuite/gcc.target/aarch64/cpunative/aarch64-cpunative.exp new file mode 100644 index 0000000000000000000000000000000000000000..ce80ca04b8d095c96acf0bda4d5b16a6460c4cbd --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/aarch64-cpunative.exp @@ -0,0 +1,35 @@ +# Copyright (C) 2014-2020 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# <http://www.gnu.org/licenses/>. + +# GCC testsuite that uses the `dg.exp' driver. + +# Exit immediately if this isn't an AArch64 target. +if ![istarget aarch64*-*-*] then { + return +} + +# Load support procs. +load_lib gcc-dg.exp + +# Initialize `dg'. +dg-init + +# Main loop. +dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \ + "" "" + +# All done. +dg-finish diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_0 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_0 new file mode 100644 index 0000000000000000000000000000000000000000..ef4a3f606fa56bc7ef1e951c1896737f013f78a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_0 @@ -0,0 +1,8 @@ +processor : 0 +BogoMIPS : 100.00 +Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 asimddp +CPU implementer : 0x41 +CPU architecture: 8 +CPU variant : 0x0 +CPU part : 0xd08 +CPU revision : 2 diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_1 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_1 new file mode 100644 index 0000000000000000000000000000000000000000..0f434bca28521f678bcee9f407f34ef813e7f1f1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_1 @@ -0,0 +1,8 @@ +processor : 0 +BogoMIPS : 100.00 +Features : fp +CPU implementer : 0x41 +CPU architecture: 8 +CPU variant : 0x0 +CPU part : 0xd08 +CPU revision : 2 diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_10 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_10 new file mode 100644 index 0000000000000000000000000000000000000000..c6e9d7ca9e274a0be8a75bd7056dad958aa53cb4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_10 @@ -0,0 +1,8 @@ +processor : 0 +BogoMIPS : 100.00 +Features : +CPU implementer : 0x41 +CPU architecture: 8 +CPU variant : 0x0 +CPU part : 0xd08 +CPU revision : 2 diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_11 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_11 new file mode 100644 index 0000000000000000000000000000000000000000..fb76f7d45bcd8238e49d3dedb1dab5265cbae982 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_11 @@ -0,0 +1,8 @@ +processor : 0 +BogoMIPS : 100.00 +Features : asimd fp sb +CPU implementer : 0x41 +CPU architecture: 8 +CPU variant : 0x0 +CPU part : 0xd08 +CPU revision : 2 diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_12 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_12 new file mode 100644 index 0000000000000000000000000000000000000000..9b6aa7bc248530eb794dad5d874a78dc9c06851b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_12 @@ -0,0 +1,8 @@ +processor : 0 +BogoMIPS : 100.00 +Features : asimd fp ssbs +CPU implementer : 0x41 +CPU architecture: 8 +CPU variant : 0x0 +CPU part : 0xd08 +CPU revision : 2 diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_13 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_13 new file mode 100644 index 0000000000000000000000000000000000000000..ef4a3f606fa56bc7ef1e951c1896737f013f78a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_13 @@ -0,0 +1,8 @@ +processor : 0 +BogoMIPS : 100.00 +Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 asimddp +CPU implementer : 0x41 +CPU architecture: 8 +CPU variant : 0x0 +CPU part : 0xd08 +CPU revision : 2 diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_14 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_14 new file mode 100644 index 0000000000000000000000000000000000000000..338975715132ed6e55c2d34514ad20294b7018ee --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_14 @@ -0,0 +1,8 @@ +processor : 0 +BogoMIPS : 100.00 +Features : Lorem ipsum dolor sit ametd rebum expetendis per at Dolor lucilius referrentur ei mei virtute eruditi eum ne Iisque verterem tacimates eu mea ei autem asimd fp asimddp +CPU implementer : 0x41 +CPU architecture: 8 +CPU variant : 0x0 +CPU part : 0xd08 +CPU revision : 2 diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_15 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_15 new file mode 100644 index 0000000000000000000000000000000000000000..bc6453945561044ab09ec2dba851eb88829c483b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_15 @@ -0,0 +1,8 @@ +processor : 0 +BogoMIPS : 100.00 +Features : Lorem ipsum dolor sit ametd rebum expetendis per at Dolor lucilius referrentur ei mei virtute eruditi eum ne Iisque verter svesm4 asimd fp +CPU implementer : 0x41 +CPU architecture: 8 +CPU variant : 0x0 +CPU part : 0xd08 +CPU revision : 2 diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_2 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_2 new file mode 100644 index 0000000000000000000000000000000000000000..965d37760ac34a456a6463c9e1baae152e966040 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_2 @@ -0,0 +1,8 @@ +processor : 0 +BogoMIPS : 100.00 +Features : asimd +CPU implementer : 0x41 +CPU architecture: 8 +CPU variant : 0x0 +CPU part : 0xd08 +CPU revision : 2 diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_3 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_3 new file mode 100644 index 0000000000000000000000000000000000000000..0c276f884a8365b8aa66b7c08f12f3e6cfead497 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_3 @@ -0,0 +1,8 @@ +processor : 0 +BogoMIPS : 100.00 +Features : asimd fp +CPU implementer : 0x41 +CPU architecture: 8 +CPU variant : 0x0 +CPU part : 0xd08 +CPU revision : 2 diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_4 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_4 new file mode 100644 index 0000000000000000000000000000000000000000..716210c14175ef5af956af2e40ecd188451bf54b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_4 @@ -0,0 +1,8 @@ +processor : 0 +BogoMIPS : 100.00 +Features : asimd fp aes pmull sha1 sha2 +CPU implementer : 0x41 +CPU architecture: 8 +CPU variant : 0x0 +CPU part : 0xd08 +CPU revision : 2 diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_5 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_5 new file mode 100644 index 0000000000000000000000000000000000000000..7a002e1c4c8192fcb541de8f90603bd27e793e72 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_5 @@ -0,0 +1,8 @@ +processor : 0 +BogoMIPS : 100.00 +Features : asimd fp fphp asimdhp +CPU implementer : 0x41 +CPU architecture: 8 +CPU variant : 0x0 +CPU part : 0xd08 +CPU revision : 2 diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_6 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_6 new file mode 100644 index 0000000000000000000000000000000000000000..d341dfe86f4c6d68a085389954197d29f32d5992 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_6 @@ -0,0 +1,8 @@ +processor : 0 +BogoMIPS : 100.00 +Features : asimd fp aes pmull sha1 sha2 fphp asimdhp +CPU implementer : 0x41 +CPU architecture: 8 +CPU variant : 0x0 +CPU part : 0xd08 +CPU revision : 2 diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_7 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_7 new file mode 100644 index 0000000000000000000000000000000000000000..ccb784915d517b44cdfba7dec01047ad085e685b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_7 @@ -0,0 +1,8 @@ +processor : 0 +BogoMIPS : 100.00 +Features : asimd pmull sha1 fp aes sha2 fphp asimdhp +CPU implementer : 0x41 +CPU architecture: 8 +CPU variant : 0x0 +CPU part : 0xd08 +CPU revision : 2 diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_8 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_8 new file mode 100644 index 0000000000000000000000000000000000000000..d6d9d03a2a26c2196ddae770411479bf71725d59 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_8 @@ -0,0 +1,8 @@ +processor : 0 +BogoMIPS : 100.00 +Features : asimd sve fp +CPU implementer : 0x41 +CPU architecture: 8 +CPU variant : 0x0 +CPU part : 0xd08 +CPU revision : 2 diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/info_9 b/gcc/testsuite/gcc.target/aarch64/cpunative/info_9 new file mode 100644 index 0000000000000000000000000000000000000000..c9aa4a9a07df4df4a7a4642fed6f664cdf8da4b3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/info_9 @@ -0,0 +1,8 @@ +processor : 0 +BogoMIPS : 100.00 +Features : asimd fp svesm4 +CPU implementer : 0x41 +CPU architecture: 8 +CPU variant : 0x0 +CPU part : 0xd08 +CPU revision : 2 diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_0.c b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_0.c new file mode 100644 index 0000000000000000000000000000000000000000..f155f51bae734a62b39867fc1a0adec65fb552de --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_0.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target { { aarch64*-*-linux*} && native } } } */ +/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_0" } */ +/* { dg-additional-options "-mcpu=native" } */ + +int main() +{ + return 0; +} + +/* { dg-final { scan-assembler {\.arch armv8-a\+crypto\+crc\+dotprod} } } */ + +/* Test a normal looking procinfo. */ diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_1.c b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_1.c new file mode 100644 index 0000000000000000000000000000000000000000..2cf0e89994b1cc0dc9fac67f4dc431c003498048 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_1.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target { { aarch64*-*-linux*} && native } } } */ +/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_1" } */ +/* { dg-additional-options "-mcpu=native" } */ + +int main() +{ + return 0; +} + +/* { dg-final { scan-assembler {\.arch armv8-a\+nosimd} } } */ + +/* Test one where fp is on by default so turn off simd. */ diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_10.c b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_10.c new file mode 100644 index 0000000000000000000000000000000000000000..6a753965c527fd7f27851c5e8e474ec900a1a75a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_10.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target { { aarch64*-*-linux*} && native } } } */ +/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_10" } */ +/* { dg-additional-options "-mcpu=native" } */ + +int main() +{ + return 0; +} + +/* { dg-final { scan-assembler {\.arch armv8-a\+nofp\+nosimd} } } */ + +/* Test one with no entry in feature list. */ diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_11.c b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_11.c new file mode 100644 index 0000000000000000000000000000000000000000..96b9ca434ebbf007ddaa45d55a8c2b8e7a19a715 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_11.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target { { aarch64*-*-linux*} && native } } } */ +/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_11" } */ +/* { dg-additional-options "-mcpu=native" } */ + +int main() +{ + return 0; +} + +/* { dg-final { scan-assembler {\.arch armv8-a\+sb} } } */ + +/* Test one with a feature name that overlaps with another one. */ diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_12.c b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_12.c new file mode 100644 index 0000000000000000000000000000000000000000..c3b44adbf6c8a02c5003049eed2ed453587b8ad4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_12.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target { { aarch64*-*-linux*} && native } } } */ +/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_12" } */ +/* { dg-additional-options "-mcpu=native" } */ + +int main() +{ + return 0; +} + +/* { dg-final { scan-assembler {\.arch armv8-a\+ssbs} } } */ + +/* Test one where the longer feature overlaps with a shorter one. */ diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_13.c b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_13.c new file mode 100644 index 0000000000000000000000000000000000000000..b7b3a8e13dfbda887f80b9e5c8f5416c153e0d65 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_13.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target { { aarch64*-*-linux*} && native } } } */ +/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_13" } */ +/* { dg-additional-options "-mcpu=native" } */ + +int main() +{ + return 0; +} + +/* { dg-final { scan-assembler {\.arch armv8-a\+crypto\+crc\+dotprod} } } */ + +/* Test one with mixed order of feature bits. */ diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_14.c b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_14.c new file mode 100644 index 0000000000000000000000000000000000000000..781ab1ebbfb46901ea38cd0063d984e372839ecd --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_14.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target { { aarch64*-*-linux*} && native } } } */ +/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_14" } */ +/* { dg-additional-options "-mcpu=native" } */ + +int main() +{ + return 0; +} + +/* { dg-final { scan-assembler {\.arch armv8-a\+dotprod} } } */ + +/* Test one where valid feature bits are at a boundary > buffer size. */ diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_15.c b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_15.c new file mode 100644 index 0000000000000000000000000000000000000000..c9205d95b793c27cd61982b9262bbbcc4912ec6d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_15.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { { aarch64*-*-linux*} && native } } } */ +/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_15" } */ +/* { dg-additional-options "-mcpu=native" } */ + +int main() +{ + return 0; +} + +/* { dg-final { scan-assembler {\.arch armv8-a\+sve2-sm4} } } */ + +/* Test one where the bounary of buffer size would cut off and leave + a valid feature in the first full buffer. e.g. this will cut off at + sve leaving 2-sm4 to yet be read. Check that this doesn't enable + +sve by mistake. */ diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_2.c b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_2.c new file mode 100644 index 0000000000000000000000000000000000000000..aad71f4347d2f8e8bb7270db2f8534bf3a198e9e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_2.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target { { aarch64*-*-linux*} && native } } } */ +/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_2" } */ +/* { dg-additional-options "-mcpu=native" } */ + +int main() +{ + return 0; +} + +/* { dg-final { scan-assembler {\.arch armv8-a\+nofp\+nosimd} } } */ + +/* Test one where asimd is provided byt no fp. */ diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_3.c b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_3.c new file mode 100644 index 0000000000000000000000000000000000000000..50685c297dbd7549ee1ea190dbfdb9dd90f3af12 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_3.c @@ -0,0 +1,13 @@ +/* { dg-do compile { target { { aarch64*-*-linux*} && native } } } */ +/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_3" } */ +/* { dg-additional-options "-mcpu=native" } */ + +int main() +{ + return 0; +} + +/* { dg-final { scan-assembler {\.arch armv8-a} } } */ + +/* Test where asimd and fp are the only ones provided, these are default + and so shouldn't emit anything. */ diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_4.c b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_4.c new file mode 100644 index 0000000000000000000000000000000000000000..91ae809757a4e31bf946fc27ec33f51001b0d3e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_4.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target { { aarch64*-*-linux*} && native } } } */ +/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_4" } */ +/* { dg-additional-options "-mcpu=native" } */ + +int main() +{ + return 0; +} + +/* { dg-final { scan-assembler {\.arch armv8-a\+crypto} } } */ + +/* Test one where all crypto bits are given so crypto should be enabled. */ diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_5.c b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_5.c new file mode 100644 index 0000000000000000000000000000000000000000..84139e58ee0000816c4ea24f27bc28f5f6563bac --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_5.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target { { aarch64*-*-linux*} && native } } } */ +/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_5" } */ +/* { dg-additional-options "-mcpu=native" } */ + +int main() +{ + return 0; +} + +/* { dg-final { scan-assembler {\.arch armv8-a\+fp16} } } */ + +/* Test one where fp16 is available and so should be emitted. */ diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_6.c b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_6.c new file mode 100644 index 0000000000000000000000000000000000000000..da72052e62385c9251d25f792b679263a18d9e61 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_6.c @@ -0,0 +1,13 @@ +/* { dg-do compile { target { { aarch64*-*-linux*} && native } } } */ +/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_6" } */ +/* { dg-additional-options "-mcpu=native" } */ + +int main() +{ + return 0; +} + +/* { dg-final { scan-assembler {\.arch armv8-a\+crypto\+fp16} } } */ + +/* Test one where the feature bits for crypto and fp16 are given in + same order as declared in options file. */ diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_7.c b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_7.c new file mode 100644 index 0000000000000000000000000000000000000000..96ad4c14db16468df30cc0a00d709ed5e2f32ed9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_7.c @@ -0,0 +1,13 @@ +/* { dg-do compile { target { { aarch64*-*-linux*} && native } } } */ +/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_7" } */ +/* { dg-additional-options "-mcpu=native" } */ + +int main() +{ + return 0; +} + +/* { dg-final { scan-assembler {\.arch armv8-a\+crypto\+fp16} } } */ + +/* Test one where the crypto and fp16 options are specified in different + order from what is in the options file. */ diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_8.c b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_8.c new file mode 100644 index 0000000000000000000000000000000000000000..7a5a2144a3973406b9ba7d268029a6940fb0be48 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_8.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target { { aarch64*-*-linux*} && native } } } */ +/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_8" } */ +/* { dg-additional-options "-mcpu=native" } */ + +int main() +{ + return 0; +} + +/* { dg-final { scan-assembler {\.arch armv8-a\+sve} } } */ + +/* Test one where sve is enabled. */ diff --git a/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_9.c b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_9.c new file mode 100644 index 0000000000000000000000000000000000000000..528b5d029f1a21c8388a30120590c1b8d5b4a81f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_9.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target { { aarch64*-*-linux*} && native } } } */ +/* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_9" } */ +/* { dg-additional-options "-mcpu=native" } */ + +int main() +{ + return 0; +} + +/* { dg-final { scan-assembler {\.arch armv8-a\+sve2-sm4} } } */ + +/* Test one here a feature that is a prefix of another is enabled. + In this case sve is a prefix to svesm4, but sve2-sm4 should be + enabled. */