diff mbox series

RISC-V: Optimize si to di zero-extend followed by left shift.

Message ID 20200531001048.6756-1-jimw@sifive.com
State New
Headers show
Series RISC-V: Optimize si to di zero-extend followed by left shift. | expand

Commit Message

Jim Wilson May 31, 2020, 12:10 a.m. UTC 
This is potentially a sequence of 3 shifts, we which optimize to a sequence
of 2 shifts.  This can happen when unsigned int is used for array indexing.

Tested with cross toolchain build and check for riscv32-elf and riscv64-linux.
There were no regressions.  The new test fails without the patch and works
with the patch.

Committed.

Jim

	gcc/
	* config/riscv/riscv.md (zero_extendsidi2_shifted): New.

	gcc/testsuite/
	* gcc.target/riscv/zero-extend-5.c: New.
---
 gcc/config/riscv/riscv.md                     | 22 +++++++++++++++++++
 .../gcc.target/riscv/zero-extend-5.c          |  8 +++++++
 2 files changed, 30 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zero-extend-5.c
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 434e064e095..f4bdb7d8cfe 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -1808,6 +1808,28 @@ 
   operands[2] = GEN_INT (ctz_hwi (INTVAL (operands[2])));
 })
 
+;; Handle SImode to DImode zero-extend combined with a left shift.  This can
+;; occur when unsigned int is used for array indexing.  Split this into two
+;; shifts.  Otherwise we can get 3 shifts.
+
+(define_insn_and_split "zero_extendsidi2_shifted"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
+			   (match_operand:QI 2 "immediate_operand" "I"))
+		(match_operand 3 "immediate_operand" "")))
+   (clobber (match_scratch:DI 4 "=&r"))]
+  "TARGET_64BIT
+   && ((INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff)"
+  "#"
+  "&& reload_completed"
+  [(set (match_dup 4)
+	(ashift:DI (match_dup 1) (const_int 32)))
+   (set (match_dup 0)
+	(lshiftrt:DI (match_dup 4) (match_dup 5)))]
+  "operands[5] = GEN_INT (32 - (INTVAL (operands [2])));"
+  [(set_attr "type" "shift")
+   (set_attr "mode" "DI")])
+
 ;;
 ;;  ....................
 ;;
diff --git a/gcc/testsuite/gcc.target/riscv/zero-extend-5.c b/gcc/testsuite/gcc.target/riscv/zero-extend-5.c
new file mode 100644
index 00000000000..1a135b8c097
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zero-extend-5.c
@@ -0,0 +1,8 @@ 
+/* { dg-do compile { target { riscv64*-*-* } } } */
+/* { dg-options "-march=rv64gc -mabi=lp64 -O2" } */
+int
+sub (unsigned int i, unsigned int j, unsigned int k, int *array)
+{
+  return array[i] + array[j] + array[k];
+}
+/* { dg-final { scan-assembler-times "slli" 3 } } */