@@ -1270,6 +1270,36 @@ aarch64_cc;
#define AARCH64_INVERSE_CONDITION_CODE(X) ((aarch64_cc) (((int) X) ^ 1))
+/* N Z C V. */
+#define AARCH64_CC_V 1
+#define AARCH64_CC_C (1 << 1)
+#define AARCH64_CC_Z (1 << 2)
+#define AARCH64_CC_N (1 << 3)
+
+/*
+ * N Z C V flags for ccmp. Indexed by aarch64_cond_code.
+ * These are the flags to make the given code be *true*.
+ */
+static const int aarch64_nzcv_codes[] =
+{
+ AARCH64_CC_Z, /* EQ, Z == 1. */
+ 0, /* NE, Z == 0. */
+ AARCH64_CC_C, /* CS, C == 1. */
+ 0, /* CC, C == 0. */
+ AARCH64_CC_N, /* MI, N == 1. */
+ 0, /* PL, N == 0. */
+ AARCH64_CC_V, /* VS, V == 1. */
+ 0, /* VC, V == 0. */
+ AARCH64_CC_C, /* HI, C == 1 && Z == 0. */
+ 0, /* LS, !(C == 1 && Z == 0). */
+ 0, /* GE, N == V. */
+ AARCH64_CC_V, /* LT, N != V. */
+ 0, /* GT, Z == 0 && N == V. */
+ AARCH64_CC_V, /* LE, !(Z == 0 && N == V). */
+ 0, /* AL, Any. */
+ 0 /* NV, Any. */
+};
+
struct aarch64_branch_protect_type
{
/* The type's name that the user passes to the branch-protection option
@@ -2351,7 +2381,7 @@ aarch64_gen_compare_reg (RTX_CODE code, rtx x, rtx y)
rtx y_hi = operand_subword (y, 1, 0, TImode);
emit_insn (gen_ccmpccdi (cc_reg, x_hi, y_hi,
gen_rtx_EQ (cc_mode, cc_reg, const0_rtx),
- GEN_INT (AARCH64_EQ)));
+ GEN_INT (aarch64_nzcv_codes[AARCH64_NE])));
}
else
{
@@ -9302,33 +9332,6 @@ aarch64_const_vec_all_in_range_p (rtx vec,
return true;
}
-/* N Z C V. */
-#define AARCH64_CC_V 1
-#define AARCH64_CC_C (1 << 1)
-#define AARCH64_CC_Z (1 << 2)
-#define AARCH64_CC_N (1 << 3)
-
-/* N Z C V flags for ccmp. Indexed by AARCH64_COND_CODE. */
-static const int aarch64_nzcv_codes[] =
-{
- 0, /* EQ, Z == 1. */
- AARCH64_CC_Z, /* NE, Z == 0. */
- 0, /* CS, C == 1. */
- AARCH64_CC_C, /* CC, C == 0. */
- 0, /* MI, N == 1. */
- AARCH64_CC_N, /* PL, N == 0. */
- 0, /* VS, V == 1. */
- AARCH64_CC_V, /* VC, V == 0. */
- 0, /* HI, C ==1 && Z == 0. */
- AARCH64_CC_C, /* LS, !(C == 1 && Z == 0). */
- AARCH64_CC_V, /* GE, N == V. */
- 0, /* LT, N != V. */
- AARCH64_CC_Z, /* GT, Z == 0 && N == V. */
- 0, /* LE, !(Z == 0 && N == V). */
- 0, /* AL, Any. */
- 0 /* NV, Any. */
-};
-
/* Print floating-point vector immediate operand X to F, negating it
first if NEGATE is true. Return true on success, false if it isn't
a constant we can handle. */
@@ -9416,7 +9419,6 @@ sizetochar (int size)
(32-bit or 64-bit).
'0': Print a normal operand, if it's a general register,
then we assume DImode.
- 'k': Print NZCV for conditional compare instructions.
'A': Output address constant representing the first
argument of X, specifying a relocation offset
if appropriate.
@@ -9866,22 +9868,6 @@ aarch64_print_operand (FILE *f, rtx x, int code)
output_addr_const (asm_out_file, x);
break;
- case 'k':
- {
- HOST_WIDE_INT cond_code;
-
- if (!CONST_INT_P (x))
- {
- output_operand_lossage ("invalid operand for '%%%c'", code);
- return;
- }
-
- cond_code = INTVAL (x);
- gcc_assert (cond_code >= 0 && cond_code <= AARCH64_NV);
- asm_fprintf (f, "%d", aarch64_nzcv_codes[cond_code]);
- }
- break;
-
case 'y':
case 'z':
{
@@ -20514,14 +20500,15 @@ aarch64_gen_ccmp_next (rtx_insn **prep_seq, rtx_insn **gen_seq, rtx prev,
rtx_code code = reverse_condition (prev_code);
prev = gen_rtx_fmt_ee (code, VOIDmode, XEXP (prev, 0), const0_rtx);
}
- aarch64_cond = AARCH64_INVERSE_CONDITION_CODE (aarch64_cond);
}
+ else
+ aarch64_cond = AARCH64_INVERSE_CONDITION_CODE (aarch64_cond);
create_fixed_operand (&ops[0], target);
create_fixed_operand (&ops[1], op0);
create_fixed_operand (&ops[2], op1);
create_fixed_operand (&ops[3], prev);
- create_fixed_operand (&ops[4], GEN_INT (aarch64_cond));
+ create_fixed_operand (&ops[4], GEN_INT (aarch64_nzcv_codes[aarch64_cond]));
push_to_sequence (*gen_seq);
if (!maybe_expand_insn (icode, 5, ops))
@@ -522,9 +522,9 @@
UNSPEC_NZCV)))]
""
"@
- ccmp\\t%<w>2, %<w>3, %k5, %m4
- ccmp\\t%<w>2, %3, %k5, %m4
- ccmn\\t%<w>2, #%n3, %k5, %m4"
+ ccmp\\t%<w>2, %<w>3, %5, %m4
+ ccmp\\t%<w>2, %3, %5, %m4
+ ccmn\\t%<w>2, #%n3, %5, %m4"
[(set_attr "type" "alus_sreg,alus_imm,alus_imm")]
)
@@ -554,7 +554,7 @@
[(match_operand 5 "immediate_operand")]
UNSPEC_NZCV)))]
"TARGET_FLOAT"
- "fccmp<e>\\t%<s>2, %<s>3, %k5, %m4"
+ "fccmp<e>\\t%<s>2, %<s>3, %5, %m4"
[(set_attr "type" "fccmp<s>")]
)
@@ -585,9 +585,9 @@
(match_operand:GPI 3 "aarch64_ccmp_operand" "r,Uss,Usn"))))]
""
"@
- ccmp\\t%<w>2, %<w>3, %k5, %M4
- ccmp\\t%<w>2, %3, %k5, %M4
- ccmn\\t%<w>2, #%n3, %k5, %M4"
+ ccmp\\t%<w>2, %<w>3, %5, %M4
+ ccmp\\t%<w>2, %3, %5, %M4
+ ccmn\\t%<w>2, #%n3, %5, %M4"
[(set_attr "type" "alus_sreg,alus_imm,alus_imm")]
)
@@ -617,7 +617,7 @@
(match_operand:GPF 2 "register_operand" "w")
(match_operand:GPF 3 "register_operand" "w"))))]
"TARGET_FLOAT"
- "fccmp<e>\\t%<s>2, %<s>3, %k5, %M4"
+ "fccmp<e>\\t%<s>2, %<s>3, %5, %M4"
[(set_attr "type" "fccmp<s>")]
)
Currently we use %k to interpret an aarch64_cond_code value. This interpretation is done via an array, aarch64_nzcv_codes. The rtl is neither hindered nor harmed by using the proper nzcv value itself, so index the array earlier than later. This makes it easier to compare the rtl to the assembly. It is slightly confusing in that aarch64_nzcv_codes has values of nzcv which produce the inverse of the code that is the index. Invert those values. * config/aarch64/aarch64.c (AARCH64_CC_{NZCV}): Move up. (aarch64_nzcv_codes): Move up; reverse values of even/odd entries. (aarch64_gen_compare_reg): Use aarch64_nzcv_codes in gen_ccmpccdi generation. (aarch64_print_operand): Remove case 'k'. (aarch64_gen_ccmp_next): Invert condition for !AND, remove inversion for AND; use aarch64_nzcv_codes. * config/aarch64/aarch64.md (*ccmpcc<GPI>): Remove %k from all alternatives. (*ccmpcc<GPI>_rev, *ccmp<CCFP><GPF>, *ccmp<CCFP><GPF>_rev): Likewise. --- gcc/config/aarch64/aarch64.c | 81 +++++++++++++++-------------------- gcc/config/aarch64/aarch64.md | 16 +++---- 2 files changed, 42 insertions(+), 55 deletions(-)