[30/40] i386: Emulate MMX ssse3_pmulhrswv4hi3 with SSE

Message ID	20190214123031.13301-31-hjl.tools@gmail.com
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Headers	show Return-Path: <gcc-patches-return-496110-incoming=patchwork.ozlabs.org@gcc.gnu.org> DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; q=dns; s=default; b=Ogq 5NDh8H6zVfZ7/Ppk9UzR6sM1mZit2qfX2lA8xeHfv7ZFE4GzDorzEfHMNTB7GWVn W6SnRBfzUNkhY4vvaCZTLHm1bAwVFOLH9CCpYUuA+gUyKsdKTVHNqj79xsBJk9qj AMYxgJo4iCkGtWAiuhfnAU+LuWI09ALh/vYLlx/s= Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk Sender: gcc-patches-owner@gcc.gnu.org From: "H.J. Lu" <hjl.tools@gmail.com> To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak <ubizjak@gmail.com> Subject: [PATCH 30/40] i386: Emulate MMX ssse3_pmulhrswv4hi3 with SSE Date: Thu, 14 Feb 2019 04:30:21 -0800 Message-Id: <20190214123031.13301-31-hjl.tools@gmail.com> In-Reply-To: <20190214123031.13301-1-hjl.tools@gmail.com> References: <20190214123031.13301-1-hjl.tools@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit
Series	V5: Emulate MMX intrinsics with SSE \| expand [00/40] V5: Emulate MMX intrinsics with SSE [01/40] i386: Allow MMX register modes in SSE registers [02/40] i386: Emulate MMX packsswb/packssdw/packuswb with SSE2 [03/40] i386: Emulate MMX punpcklXX/punpckhXX with SSE punpcklXX [04/40] i386: Emulate MMX plusminus/sat_plusminus with SSE [05/40] i386: Emulate MMX mulv4hi3 with SSE [06/40] i386: Emulate MMX smulv4hi3_highpart with SSE [07/40] i386: Emulate MMX mmx_pmaddwd with SSE [08/40] i386: Emulate MMX ashr<mode>3/<shift_insn><mode>3 with SSE [09/40] i386: Emulate MMX <any_logic><mode>3 with SSE [10/40] i386: Emulate MMX mmx_andnot<mode>3 with SSE [11/40] i386: Emulate MMX mmx_eq/mmx_gt<mode>3 with SSE [12/40] i386: Emulate MMX vec_dupv2si with SSE [13/40] i386: Emulate MMX pshufw with SSE [15/40] i386: Emulate MMX sse_cvtpi2ps with SSE [16/40] i386: Emulate MMX mmx_pextrw with SSE [17/40] i386: Emulate MMX mmx_pinsrw with SSE [18/40] i386: Emulate MMX V4HI smaxmin/V8QI umaxmin with SSE [19/40] i386: Emulate MMX mmx_pmovmskb with SSE [20/40] i386: Emulate MMX mmx_umulv4hi3_highpart with SSE [21/40] i386: Emulate MMX maskmovq with SSE2 maskmovdqu [22/40] i386: Emulate MMX mmx_uavgv8qi3 with SSE [23/40] i386: Emulate MMX mmx_uavgv4hi3 with SSE [24/40] i386: Emulate MMX mmx_psadbw with SSE [25/40] i386: Emulate MMX movntq with SSE2 movntidi [26/40] i386: Emulate MMX umulv1siv1di3 with SSE2 [27/40] i386: Emulate MMX ssse3_ph<plusminus_mnemonic>wv4hi3 with SSE [28/40] i386: Emulate MMX ssse3_ph<plusminus_mnemonic>dv2si3 with SSE [29/40] i386: Emulate MMX ssse3_pmaddubsw with SSE [30/40] i386: Emulate MMX ssse3_pmulhrswv4hi3 with SSE [31/40] i386: Emulate MMX pshufb with SSE version [32/40] i386: Emulate MMX ssse3_psign<mode>3 with SSE [33/40] i386: Emulate MMX ssse3_palignrdi with SSE [34/40] i386: Emulate MMX abs<mode>2 with SSE [35/40] i386: Allow MMXMODE moves with TARGET_MMX_WITH_SSE [36/40] i386: Allow MMX vector expanders with TARGET_MMX_WITH_SSE [37/40] i386: Allow MMX intrinsic emulation with SSE [38/40] i386: Enable TM MMX intrinsics with SSE2 [39/40] i386: Add tests for MMX intrinsic emulations with SSE [40/40] i386: Also enable SSSE3 __m64 tests in 64-bit mode [41/40] Prevent allocation of MMX registers with TARGET_MMX_WITH_SSE

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20190214123031.13301-31-hjl.tools@gmail.com

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Subject: [PATCH 30/40] i386: Emulate MMX ssse3_pmulhrswv4hi3 with SSE
Date: Thu, 14 Feb 2019 04:30:21 -0800
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Series

V5: Emulate MMX intrinsics with SSE | expand

Commit Message

H.J. Lu Feb. 14, 2019, 12:30 p.m. UTC

Emulate MMX ssse3_pmulhrswv4hi3 with SSE.  Only SSE register source
operand is allowed.

	PR target/89021
	* config/i386/sse.md (*ssse3_pmulhrswv4hi3): Add SSE emulation.
---
 gcc/config/i386/sse.md | 20 +++++++++++++-------
 1 file changed, 13 insertions(+), 7 deletions(-)

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index a7d0889f3e1..cc7dbe79fa7 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -15677,25 +15677,31 @@ 
    (set_attr "mode" "<sseinsnmode>")])
 
 (define_insn "*ssse3_pmulhrswv4hi3"
-  [(set (match_operand:V4HI 0 "register_operand" "=y")
+  [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yv")
 	(truncate:V4HI
 	  (lshiftrt:V4SI
 	    (plus:V4SI
 	      (lshiftrt:V4SI
 		(mult:V4SI
 		  (sign_extend:V4SI
-		    (match_operand:V4HI 1 "nonimmediate_operand" "%0"))
+		    (match_operand:V4HI 1 "nonimmediate_operand" "%0,0,Yv"))
 		  (sign_extend:V4SI
-		    (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
+		    (match_operand:V4HI 2 "nonimmediate_operand" "ym,x,Yv")))
 		(const_int 14))
 	      (match_operand:V4HI 3 "const1_operand"))
 	    (const_int 1))))]
-  "TARGET_SSSE3 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
-  "pmulhrsw\t{%2, %0|%0, %2}"
-  [(set_attr "type" "sseimul")
+  "(TARGET_MMX || TARGET_MMX_WITH_SSE)
+   && TARGET_SSSE3
+   && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
+  "@
+   pmulhrsw\t{%2, %0|%0, %2}
+   pmulhrsw\t{%2, %0|%0, %2}
+   vpmulhrsw\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")
+   (set_attr "type" "sseimul")
    (set_attr "prefix_extra" "1")
    (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
-   (set_attr "mode" "DI")])
+   (set_attr "mode" "DI,TI,TI")])
 
 (define_insn "<ssse3_avx2>_pshufb<mode>3<mask_name>"
   [(set (match_operand:VI1_AVX512 0 "register_operand" "=x,x,v")

[30/40] i386: Emulate MMX ssse3_pmulhrswv4hi3 with SSE

Commit Message

Patch