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RISC-V: Set SLOW_BYTE_ACCESS=1

Message ID 20171103153438.29280-1-palmer@dabbelt.com
State New
Headers show
Series RISC-V: Set SLOW_BYTE_ACCESS=1 | expand

Commit Message

Palmer Dabbelt Nov. 3, 2017, 3:34 p.m. UTC
From: Andrew Waterman <andrew@sifive.com>

When implementing the RISC-V port, I took the name of this macro at
face value.  It appears we were mistaken in what this means, here's a
quote from the SPARC port that better describes what SLOW_BYTE_ACCESS
does

    /* Nonzero if access to memory by bytes is slow and undesirable.
       For RISC chips, it means that access to memory by bytes is no
       better than access by words when possible, so grab a whole word
       and maybe make use of that.  */

I've added the comment to our port as well.

See https://gcc.gnu.org/ml/gcc/2017-08/msg00202.html for more
discussion.  Thanks to Michael Clark and Andrew Pinski for the help!

gcc/ChangeLog

2017-10-03  Andrew Waterman  <andrew@sifive.com>

        * config/riscv/riscv.h (SLOW_BYTE_ACCESS): Change to 1.
---
 gcc/config/riscv/riscv.h | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

Comments

Palmer Dabbelt Nov. 5, 2017, 12:30 a.m. UTC | #1
Committed.

On Fri, 03 Nov 2017 08:34:38 PDT (-0700), Palmer Dabbelt wrote:
> From: Andrew Waterman <andrew@sifive.com>
>
> When implementing the RISC-V port, I took the name of this macro at
> face value.  It appears we were mistaken in what this means, here's a
> quote from the SPARC port that better describes what SLOW_BYTE_ACCESS
> does
>
>     /* Nonzero if access to memory by bytes is slow and undesirable.
>        For RISC chips, it means that access to memory by bytes is no
>        better than access by words when possible, so grab a whole word
>        and maybe make use of that.  */
>
> I've added the comment to our port as well.
>
> See https://gcc.gnu.org/ml/gcc/2017-08/msg00202.html for more
> discussion.  Thanks to Michael Clark and Andrew Pinski for the help!
>
> gcc/ChangeLog
>
> 2017-10-03  Andrew Waterman  <andrew@sifive.com>
>
>         * config/riscv/riscv.h (SLOW_BYTE_ACCESS): Change to 1.
> ---
>  gcc/config/riscv/riscv.h | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
> index e53555efe82f..a802a3f8cbbb 100644
> --- a/gcc/config/riscv/riscv.h
> +++ b/gcc/config/riscv/riscv.h
> @@ -615,7 +615,12 @@ typedef struct {
>  #define MOVE_MAX UNITS_PER_WORD
>  #define MAX_MOVE_MAX 8
>
> -#define SLOW_BYTE_ACCESS 0
> +/* The SPARC port says:
> +   Nonzero if access to memory by bytes is slow and undesirable.
> +   For RISC chips, it means that access to memory by bytes is no
> +   better than access by words when possible, so grab a whole word
> +   and maybe make use of that.  */
> +#define SLOW_BYTE_ACCESS 1
>
>  #define SHIFT_COUNT_TRUNCATED 1
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index e53555efe82f..a802a3f8cbbb 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -615,7 +615,12 @@  typedef struct {
 #define MOVE_MAX UNITS_PER_WORD
 #define MAX_MOVE_MAX 8
 
-#define SLOW_BYTE_ACCESS 0
+/* The SPARC port says:
+   Nonzero if access to memory by bytes is slow and undesirable.
+   For RISC chips, it means that access to memory by bytes is no
+   better than access by words when possible, so grab a whole word
+   and maybe make use of that.  */
+#define SLOW_BYTE_ACCESS 1
 
 #define SHIFT_COUNT_TRUNCATED 1