| Message ID | 20160226185242.GA32075@gate.crashing.org |
|---|---|
| State | New |
| Headers | show |
On Fri, Feb 26, 2016 at 1:52 PM, Segher Boessenkool <segher@kernel.crashing.org> wrote: > On Thu, Feb 25, 2016 at 10:52:29AM -0500, David Edelsohn wrote: >> Please add a short comment explaining why rs6000_insn_for_shift_mask >> doesn't need to match the logic in rs6000_is_valid_shift_mask >> converting rotates to simple shifts. > > I added this comment: > > --- trunk/gcc/config/rs6000/rs6000.c 2016/02/26 18:17:02 233754 > +++ trunk/gcc/config/rs6000/rs6000.c 2016/02/26 18:49:18 233755 > @@ -17438,9 +17438,12 @@ rs6000_insn_for_shift_mask (machine_mode > operands[2] = GEN_INT (32 - INTVAL (operands[2])); > operands[3] = GEN_INT (31 - nb); > operands[4] = GEN_INT (31 - ne); > + /* This insn can also be a 64-bit rotate with mask that really makes > + it just a shift right (with mask); the %h below are to adjust for > + that situation (shift count is >= 32 in that case). */ > if (dot) > - return "rlw%I2nm. %0,%1,%2,%3,%4"; > - return "rlw%I2nm %0,%1,%2,%3,%4"; > + return "rlw%I2nm. %0,%1,%h2,%3,%4"; > + return "rlw%I2nm %0,%1,%h2,%3,%4"; > } > > gcc_unreachable (); Thanks! - David
--- trunk/gcc/config/rs6000/rs6000.c 2016/02/26 18:17:02 233754 +++ trunk/gcc/config/rs6000/rs6000.c 2016/02/26 18:49:18 233755 @@ -17438,9 +17438,12 @@ rs6000_insn_for_shift_mask (machine_mode operands[2] = GEN_INT (32 - INTVAL (operands[2])); operands[3] = GEN_INT (31 - nb); operands[4] = GEN_INT (31 - ne); + /* This insn can also be a 64-bit rotate with mask that really makes + it just a shift right (with mask); the %h below are to adjust for + that situation (shift count is >= 32 in that case). */ if (dot) - return "rlw%I2nm. %0,%1,%2,%3,%4"; - return "rlw%I2nm %0,%1,%2,%3,%4"; + return "rlw%I2nm. %0,%1,%h2,%3,%4"; + return "rlw%I2nm %0,%1,%h2,%3,%4"; } gcc_unreachable ();