From patchwork Thu Nov 12 15:30:54 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ilya Enkovich X-Patchwork-Id: 543404 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 478841409C4 for ; Fri, 13 Nov 2015 02:31:33 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=Od/FqcKX; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:subject:message-id:mime-version:content-type; q=dns; s= default; b=MZFKI9mFL0oYDwxx4C+i7L9fRTsaymwNvaHhHUbAc6FcewKlqVp30 55uTGtjKmugNPmJxiwIs/6yAwMqHR9rGwOiM6FxJrKXfBdHarv+GkbcpoGrCb9xd xIUZwRakc59f+5+6N79TnClJVQg3U6FzxGQGO5ZtOSgC08cLbX+qbg= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:subject:message-id:mime-version:content-type; s= default; bh=E6WXyDrNV2cF94FkYYoHurrvsNs=; b=Od/FqcKXkG4fKwUifwFz 5IyNSHGLJxNyZrQclxJ2ADZsINYpL7M36EdacKX1UU4TtknBGc2hT7zOevWToxQG m6JdJQLWwO5wFmVlF5a/dhfWY/UDykqp/xiwWUHWN6qE1pTJLQtAANxPRE1XEfI2 mTu7/NPkntxSvGZK0zZVrMs= Received: (qmail 34838 invoked by alias); 12 Nov 2015 15:31:26 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 34824 invoked by uid 89); 12 Nov 2015 15:31:25 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.5 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-io0-f176.google.com Received: from mail-io0-f176.google.com (HELO mail-io0-f176.google.com) (209.85.223.176) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Thu, 12 Nov 2015 15:31:24 +0000 Received: by ioc74 with SMTP id 74so68125500ioc.2 for ; Thu, 12 Nov 2015 07:31:22 -0800 (PST) X-Received: by 10.107.10.199 with SMTP id 68mr14704885iok.75.1447342281753; Thu, 12 Nov 2015 07:31:21 -0800 (PST) Received: from msticlxl57.ims.intel.com (jfdmzpr03-ext.jf.intel.com. [134.134.139.72]) by smtp.gmail.com with ESMTPSA id b80sm5157157ioe.33.2015.11.12.07.31.20 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 12 Nov 2015 07:31:21 -0800 (PST) Date: Thu, 12 Nov 2015 18:30:54 +0300 From: Ilya Enkovich To: gcc-patches@gcc.gnu.org Subject: [PATCH, doc] Document some standard pattern names Message-ID: <20151112125824.GC51435@msticlxl57.ims.intel.com> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.23 (2014-03-12) X-IsSubscribed: yes Hi, This patch adds description for several standard pattern names. OK for trunk? Thanks, Ilya --- gcc/ 2015-11-12 Ilya Enkovich * doc/md.texi (vec_cmp@var{m}@var{n}): New item. (vec_cmpu@var{m}@var{n}): New item. (vcond@var{m}@var{n}): Specify comparison is signed. (vcondu@var{m}@var{n}): New item. (vcond_mask_@var{m}@var{n}): New item. (maskload@var{m}@var{n}): New item. (maskstore@var{m}@var{n}): New item. diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 71a2791..7fdc935 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -4749,17 +4749,51 @@ specify field index and operand 0 place to store value into. Initialize the vector to given values. Operand 0 is the vector to initialize and operand 1 is parallel containing values for individual fields. +@cindex @code{vec_cmp@var{m}@var{n}} instruction pattern +@item @samp{vec_cmp@var{m}@var{n}} +Output a vector comparison. Operand 0 of mode @var{n} is the destination for +predicate in operand 1 which is a signed vector comparison with operands of +mode @var{m} in operands 2 and 3. Predicate is computed by element-wise +evaluation of the vector comparison with a truth value of all-ones and a false +value of all-zeros. + +@cindex @code{vec_cmpu@var{m}@var{n}} instruction pattern +@item @samp{vec_cmpu@var{m}@var{n}} +Similar to @code{vec_cmp@var{m}@var{n}} but perform unsigned vector comparison. + @cindex @code{vcond@var{m}@var{n}} instruction pattern @item @samp{vcond@var{m}@var{n}} Output a conditional vector move. Operand 0 is the destination to receive a combination of operand 1 and operand 2, which are of mode @var{m}, -dependent on the outcome of the predicate in operand 3 which is a +dependent on the outcome of the predicate in operand 3 which is a signed vector comparison with operands of mode @var{n} in operands 4 and 5. The modes @var{m} and @var{n} should have the same size. Operand 0 will be set to the value @var{op1} & @var{msk} | @var{op2} & ~@var{msk} where @var{msk} is computed by element-wise evaluation of the vector comparison with a truth value of all-ones and a false value of all-zeros. +@cindex @code{vcondu@var{m}@var{n}} instruction pattern +@item @samp{vcondu@var{m}@var{n}} +Similar to @code{vcond@var{m}@var{n}} but performs unsigned vector +comparison. + +@cindex @code{vcond_mask_@var{m}@var{n}} instruction pattern +@item @samp{vcond_mask_@var{m}@var{n}} +Similar to @code{vcond@var{m}@var{n}} but operand 3 holds a pre-computed +result of vector comparison. + +@cindex @code{maskload@var{m}@var{n}} instruction pattern +@item @samp{maskload@var{m}@var{n}} +Perform a masked load of vector from memory operand 1 of mode @var{m} +into register operand 0. Mask is provided in register operand 2 of +mode @var{n}. + +@cindex @code{maskstore@var{m}@var{n}} instruction pattern +@item @samp{maskload@var{m}@var{n}} +Perform a masked store of vector from register operand 1 of mode @var{m} +into memory operand 0. Mask is provided in register operand 2 of +mode @var{n}. + @cindex @code{vec_perm@var{m}} instruction pattern @item @samp{vec_perm@var{m}} Output a (variable) vector permutation. Operand 0 is the destination