diff mbox

[i386] PR 59422 - Support more targets for function multi versioning

Message ID 20131223134805.GA9080@gmail.com
State New
Headers show

Commit Message

H.J. Lu Dec. 23, 2013, 1:48 p.m. UTC 
On Thu, Dec 19, 2013 at 11:20:39AM +0100, Allan Sandfeld Jensen wrote:
> On Thursday 19 December 2013, Gopalasubramanian, Ganesh wrote:
> > > Sorry, I must have been looking at an older version, but as I said I
> > > already did enable it in the latest patch. (see
> > > http://gcc.gnu.org/ml/gcc-patches/2013-12/msg01577.html )
> > 
> > Sorry for causing another revision but we would like to stick with "btver1"
> > and "btver2" rather than "BOBCAT" or "JAGUAR". Therefore the changes would
> > be like
> > 
> I will need to make an updated patch to move the new ISAs to the end of the 
> list anyway. I will send it in a few days to give AMD or Intel developers time 
> to comment on the current version.
> 

I renamed Intel processor names. Please update your patch.  Here is my
patch to add more Intel processor support.  You can add it to your
patch.

Thanks.


H.J.
---
From 2ef9b6959a4625d89cab6f06aec6bb2b37095264 Mon Sep 17 00:00:00 2001
From: "H.J. Lu" <hjl.tools@gmail.com>
Date: Mon, 23 Dec 2013 05:26:01 -0800
Subject: [PATCH 1/2] Handle haswell and silvermont

---
 ChangeLog.arch               | 18 ++++++++++++++++++
 gcc/config/i386/i386.c       | 14 ++++++++++++++
 libgcc/config/i386/cpuinfo.c | 15 +++++++++++++++
 3 files changed, 47 insertions(+)
 create mode 100644 ChangeLog.arch
diff mbox

Patch

diff --git a/ChangeLog.arch b/ChangeLog.arch
new file mode 100644
index 0000000..2030a76
--- /dev/null
+++ b/ChangeLog.arch
@@ -0,0 +1,18 @@ 
+gcc/
+
+2013-12-23   H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/i386/i386.c (get_builtin_code_for_version): Handle
+	PROCESSOR_HASWELL and PROCESSOR_SILVERMONT.
+	(processor_model): Add M_INTEL_COREI7_IVYBRIDGE and
+	M_INTEL_COREI7_HASWELL.
+	(arch_names_table): Add "ivybridge", "haswell", "bonnell",
+	"silvermont".
+
+libgcc/
+
+2013-12-23   H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/i386/cpuinfo.c (processor_subtypes): Add
+	INTEL_COREI7_IVYBRIDGE and INTEL_COREI7_HASWELL.
+	(get_intel_cpu): Check Ivy Bridge and Haswell processors.
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 2d480b3..d854b5b 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -30058,10 +30058,18 @@  get_builtin_code_for_version (tree decl, tree *predicate_list)
               arg_str = "sandybridge";
               priority = P_PROC_SSE4_2;
               break;
+	    case PROCESSOR_HASWELL:
+	      arg_str = "haswell";
+	      priority = P_PROC_SSE4_2;
+	      break;
 	    case PROCESSOR_BONNELL:
 	      arg_str = "bonnell";
 	      priority = P_PROC_SSSE3;
 	      break;
+	    case PROCESSOR_SILVERMONT:
+	      arg_str = "silvermont";
+	      priority = P_PROC_SSE4_2;
+	      break;
 	    case PROCESSOR_AMDFAM10:
 	      arg_str = "amdfam10h";
 	      priority = P_PROC_SSE4_a;
@@ -30959,6 +30967,8 @@  fold_builtin_cpu (tree fndecl, tree *args)
     M_INTEL_COREI7_NEHALEM,
     M_INTEL_COREI7_WESTMERE,
     M_INTEL_COREI7_SANDYBRIDGE,
+    M_INTEL_COREI7_IVYBRIDGE,
+    M_INTEL_COREI7_HASWELL,
     M_AMDFAM10H_BARCELONA,
     M_AMDFAM10H_SHANGHAI,
     M_AMDFAM10H_ISTANBUL,
@@ -30984,6 +30994,10 @@  fold_builtin_cpu (tree fndecl, tree *args)
       {"nehalem", M_INTEL_COREI7_NEHALEM},
       {"westmere", M_INTEL_COREI7_WESTMERE},
       {"sandybridge", M_INTEL_COREI7_SANDYBRIDGE},
+      {"ivybridge", M_INTEL_COREI7_IVYBRIDGE},
+      {"haswell", M_INTEL_COREI7_HASWELL},
+      {"bonnell", M_INTEL_BONNELL},
+      {"silvermont", M_INTEL_SILVERMONT},
       {"amdfam10h", M_AMDFAM10H},
       {"barcelona", M_AMDFAM10H_BARCELONA},
       {"shanghai", M_AMDFAM10H_SHANGHAI},
diff --git a/libgcc/config/i386/cpuinfo.c b/libgcc/config/i386/cpuinfo.c
index 4b0c189..577881b 100644
--- a/libgcc/config/i386/cpuinfo.c
+++ b/libgcc/config/i386/cpuinfo.c
@@ -70,6 +70,8 @@  enum processor_subtypes
   INTEL_COREI7_NEHALEM = 1,
   INTEL_COREI7_WESTMERE,
   INTEL_COREI7_SANDYBRIDGE,
+  INTEL_COREI7_IVYBRIDGE,
+  INTEL_COREI7_HASWELL,
   AMDFAM10H_BARCELONA,
   AMDFAM10H_SHANGHAI,
   AMDFAM10H_ISTANBUL,
@@ -196,6 +198,19 @@  get_intel_cpu (unsigned int family, unsigned int model, unsigned int brand_id)
 	      __cpu_model.__cpu_type = INTEL_COREI7;
 	      __cpu_model.__cpu_subtype = INTEL_COREI7_SANDYBRIDGE;
 	      break;
+	    case 0x3a:
+	    case 0x3e:
+	      /* Ivy Bridge.  */
+	      __cpu_model.__cpu_type = INTEL_COREI7;
+	      __cpu_model.__cpu_subtype = INTEL_COREI7_IVYBRIDGE;
+	      break;
+	    case 0x3c:
+	    case 0x45:
+	    case 0x46:
+	      /* Haswell.  */
+	      __cpu_model.__cpu_type = INTEL_COREI7;
+	      __cpu_model.__cpu_subtype = INTEL_COREI7_HASWELL;
+	      break;
 	    case 0x17:
 	    case 0x1d:
 	      /* Penryn.  */