diff --git a/gcc/config/i386/core2.md b/gcc/config/i386/core2.md
index 2e42675..daf7b8d 100644
--- a/gcc/config/i386/core2.md
+++ b/gcc/config/i386/core2.md
@@ -102,12 +102,12 @@
 ;; on decoder 0, and say that it takes a little while before the result
 ;; is available.
 (define_insn_reservation "c2_complex_insn" 6
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (eq_attr "type" "other,multi,str"))
 			 "c2_decoder0")
 
 (define_insn_reservation "c2_call" 1
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (eq_attr "type" "call,callv"))
 			 "c2_decoder0")
 
@@ -115,50 +115,50 @@
 ;; imovx always decodes to one uop, and also doesn't use the integer
 ;; units if it has memory operands.
 (define_insn_reservation "c2_imov" 1
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "none")
 				   (eq_attr "type" "imov,imovx")))
 			 "c2_decodern,(c2_p0|c2_p1|c2_p5)")
 
 (define_insn_reservation "c2_imov_load" 4
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "load")
 				   (eq_attr "type" "imov,imovx")))
 			 "c2_decodern,c2_p2")
 
 (define_insn_reservation "c2_imov_store" 1
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "store")
 				   (eq_attr "type" "imov")))
 			 "c2_decodern,c2_p4+c2_p3")
 
 (define_insn_reservation "c2_icmov" 2
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "none")
 				   (eq_attr "type" "icmov")))
 			 "c2_decoder0,(c2_p0|c2_p1|c2_p5)*2")
 
 (define_insn_reservation "c2_icmov_load" 2
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "load")
 				   (eq_attr "type" "icmov")))
 			 "c2_decoder0,c2_p2,(c2_p0|c2_p1|c2_p5)*2")
 
 (define_insn_reservation "c2_push_reg" 1
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "store")
 				   (eq_attr "type" "push")))
 			 "c2_decodern,c2_p4+c2_p3")
 
 (define_insn_reservation "c2_push_mem" 1
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "both")
 				   (eq_attr "type" "push")))
 			 "c2_decoder0,c2_p2,c2_p4+c2_p3")
 
 ;; lea executes on port 0 with latency one and throughput 1.
 (define_insn_reservation "c2_lea" 1
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "none")
 				   (eq_attr "type" "lea")))
 			 "c2_decodern,c2_p0")
@@ -167,61 +167,61 @@
 ;; The load and store units need to be reserved when memory operands
 ;; are involved.
 (define_insn_reservation "c2_shift_rotate" 1
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "none")
 				   (eq_attr "type" "ishift,ishift1,rotate,rotate1")))
 			 "c2_decodern,(c2_p0|c2_p5)")
 
 (define_insn_reservation "c2_shift_rotate_mem" 4
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "!none")
 				   (eq_attr "type" "ishift,ishift1,rotate,rotate1")))
 			 "c2_decoder0,c2_p2,(c2_p0|c2_p5),c2_p4+c2_p3")
 
 ;; See comments in ppro.md for the corresponding reservation.
 (define_insn_reservation "c2_branch" 1
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "none")
 				   (eq_attr "type" "ibr")))
 			 "c2_decodern,c2_p5")
 
 ;; ??? Indirect branches probably have worse latency than this.
 (define_insn_reservation "c2_indirect_branch" 6
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "!none")
 				   (eq_attr "type" "ibr")))
 			 "c2_decoder0,c2_p2+c2_p5")
 
 (define_insn_reservation "c2_leave" 4
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (eq_attr "type" "leave"))
 			 "c2_decoder0,c2_p2+(c2_p0|c2_p1),(c2_p0|c2_p1)")
 
 ;; mul and imul with two/three operands only execute on port 1 for HImode
 ;; and SImode, port 0 for DImode.
 (define_insn_reservation "c2_imul_hisi" 3
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "none")
 				   (and (eq_attr "mode" "HI,SI")
 					(eq_attr "type" "imul"))))
 			 "c2_decodern,c2_p1")
 
 (define_insn_reservation "c2_imul_hisi_mem" 3
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "!none")
 				   (and (eq_attr "mode" "HI,SI")
 					(eq_attr "type" "imul"))))
 			 "c2_decoder0,c2_p2+c2_p1")
 
 (define_insn_reservation "c2_imul_di" 5
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "none")
 				   (and (eq_attr "mode" "DI")
 					(eq_attr "type" "imul"))))
 			 "c2_decodern,c2_p0")
 
 (define_insn_reservation "c2_imul_di_mem" 5
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "!none")
 				   (and (eq_attr "mode" "DI")
 					(eq_attr "type" "imul"))))
@@ -231,42 +231,42 @@
 ;; QI, HI, and SI have issue latency 12, 21, and 37, respectively.
 ;; These issue latencies are modelled via the c2_div automaton.
 (define_insn_reservation "c2_idiv_QI" 19
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "none")
 				   (and (eq_attr "mode" "QI")
 					(eq_attr "type" "idiv"))))
 			 "c2_decoder0,(c2_p0+c2_idiv)*2,(c2_p0|c2_p1)+c2_idiv,c2_idiv*9")
 
 (define_insn_reservation "c2_idiv_QI_load" 19
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "load")
 				   (and (eq_attr "mode" "QI")
 					(eq_attr "type" "idiv"))))
 			 "c2_decoder0,c2_p2+c2_p0+c2_idiv,c2_p0+c2_idiv,(c2_p0|c2_p1)+c2_idiv,c2_idiv*9")
 
 (define_insn_reservation "c2_idiv_HI" 23
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "none")
 				   (and (eq_attr "mode" "HI")
 					(eq_attr "type" "idiv"))))
 			 "c2_decoder0,(c2_p0+c2_idiv)*3,(c2_p0|c2_p1)+c2_idiv,c2_idiv*17")
 
 (define_insn_reservation "c2_idiv_HI_load" 23
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "load")
 				   (and (eq_attr "mode" "HI")
 					(eq_attr "type" "idiv"))))
 			 "c2_decoder0,c2_p2+c2_p0+c2_idiv,c2_p0+c2_idiv,(c2_p0|c2_p1)+c2_idiv,c2_idiv*18")
 
 (define_insn_reservation "c2_idiv_SI" 39
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "none")
 				   (and (eq_attr "mode" "SI")
 					(eq_attr "type" "idiv"))))
 			 "c2_decoder0,(c2_p0+c2_idiv)*3,(c2_p0|c2_p1)+c2_idiv,c2_idiv*33")
 
 (define_insn_reservation "c2_idiv_SI_load" 39
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "load")
 				   (and (eq_attr "mode" "SI")
 					(eq_attr "type" "idiv"))))
@@ -275,90 +275,90 @@
 ;; x87 floating point operations.
 
 (define_insn_reservation "c2_fxch" 0
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (eq_attr "type" "fxch"))
 			 "c2_decodern")
 
 (define_insn_reservation "c2_fop" 3
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "none,unknown")
 				   (eq_attr "type" "fop")))
 			 "c2_decodern,c2_p1")
 
 (define_insn_reservation "c2_fop_load" 5
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "load")
 				   (eq_attr "type" "fop")))
 			 "c2_decoder0,c2_p2+c2_p1,c2_p1")
 
 (define_insn_reservation "c2_fop_store" 3
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "store")
 				   (eq_attr "type" "fop")))
 			 "c2_decoder0,c2_p0,c2_p0,c2_p0+c2_p4+c2_p3")
 
 (define_insn_reservation "c2_fop_both" 5
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "both")
 				   (eq_attr "type" "fop")))
 			 "c2_decoder0,c2_p2+c2_p0,c2_p0+c2_p4+c2_p3")
 
 (define_insn_reservation "c2_fsgn" 1
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (eq_attr "type" "fsgn"))
 			 "c2_decodern,c2_p0")
 
 (define_insn_reservation "c2_fistp" 5
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (eq_attr "type" "fistp"))
 			 "c2_decoder0,c2_p0*2,c2_p4+c2_p3")
 
 (define_insn_reservation "c2_fcmov" 2
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (eq_attr "type" "fcmov"))
 			 "c2_decoder0,c2_p0*2")
 
 (define_insn_reservation "c2_fcmp" 1
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "none")
 				   (eq_attr "type" "fcmp")))
 			 "c2_decodern,c2_p1")
 
 (define_insn_reservation "c2_fcmp_load" 4
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "load")
 				   (eq_attr "type" "fcmp")))
 			 "c2_decoder0,c2_p2+c2_p1")
 
 (define_insn_reservation "c2_fmov" 1
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "none")
 				   (eq_attr "type" "fmov")))
 			 "c2_decodern,c2_p0")
 
 (define_insn_reservation "c2_fmov_load" 1
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "load")
 				   (and (eq_attr "mode" "!XF")
 					(eq_attr "type" "fmov"))))
 			 "c2_decodern,c2_p2")
 
 (define_insn_reservation "c2_fmov_XF_load" 3
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "load")
 				   (and (eq_attr "mode" "XF")
 					(eq_attr "type" "fmov"))))
 			 "c2_decoder0,(c2_p2+c2_p0)*2")
 
 (define_insn_reservation "c2_fmov_store" 1
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "store")
 				   (and (eq_attr "mode" "!XF")
 					(eq_attr "type" "fmov"))))
 			 "c2_decodern,c2_p3+c2_p4")
 
 (define_insn_reservation "c2_fmov_XF_store" 3
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "store")
 				   (and (eq_attr "mode" "XF")
 					(eq_attr "type" "fmov"))))
@@ -367,13 +367,13 @@
 ;; fmul executes on port 0 with latency 5.  It has issue latency 2,
 ;; but we don't model this.
 (define_insn_reservation "c2_fmul" 5
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "none")
 				   (eq_attr "type" "fmul")))
 			 "c2_decoder0,c2_p0*2")
 
 (define_insn_reservation "c2_fmul_load" 6
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "load")
 				   (eq_attr "type" "fmul")))
 			 "c2_decoder0,c2_p2+c2_p0,c2_p0")
@@ -384,42 +384,42 @@
 ;; that.  Throughput is equal to latency - 1, which we model using the
 ;; c2_div automaton.
 (define_insn_reservation "c2_fdiv_SF" 18
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "none")
 				   (and (eq_attr "mode" "SF")
 					(eq_attr "type" "fdiv,fpspc"))))
 			 "c2_decodern,c2_p0+c2_fdiv,c2_fdiv*16")
 
 (define_insn_reservation "c2_fdiv_SF_load" 19
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "load")
 				   (and (eq_attr "mode" "SF")
 					(eq_attr "type" "fdiv,fpspc"))))
 			 "c2_decoder0,c2_p2+c2_p0+c2_fdiv,c2_fdiv*16")
 
 (define_insn_reservation "c2_fdiv_DF" 32
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "none")
 				   (and (eq_attr "mode" "DF")
 					(eq_attr "type" "fdiv,fpspc"))))
 			 "c2_decodern,c2_p0+c2_fdiv,c2_fdiv*30")
 
 (define_insn_reservation "c2_fdiv_DF_load" 33
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "load")
 				   (and (eq_attr "mode" "DF")
 					(eq_attr "type" "fdiv,fpspc"))))
 			 "c2_decoder0,c2_p2+c2_p0+c2_fdiv,c2_fdiv*30")
 
 (define_insn_reservation "c2_fdiv_XF" 38
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "none")
 				   (and (eq_attr "mode" "XF")
 					(eq_attr "type" "fdiv,fpspc"))))
 			 "c2_decodern,c2_p0+c2_fdiv,c2_fdiv*36")
 
 (define_insn_reservation "c2_fdiv_XF_load" 39
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "load")
 				   (and (eq_attr "mode" "XF")
 					(eq_attr "type" "fdiv,fpspc"))))
@@ -428,71 +428,71 @@
 ;; MMX instructions.
 
 (define_insn_reservation "c2_mmx_add" 1
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "none")
 				   (eq_attr "type" "mmxadd,sseiadd")))
 			 "c2_decodern,c2_p0|c2_p5")
 
 (define_insn_reservation "c2_mmx_add_load" 2
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "load")
 				   (eq_attr "type" "mmxadd,sseiadd")))
 			 "c2_decodern,c2_p2+c2_p0|c2_p5")
 
 (define_insn_reservation "c2_mmx_shft" 1
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "none")
 				   (eq_attr "type" "mmxshft")))
 			 "c2_decodern,c2_p0|c2_p5")
 
 (define_insn_reservation "c2_mmx_shft_load" 2
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "load")
 				   (eq_attr "type" "mmxshft")))
 			 "c2_decoder0,c2_p2+c2_p1")
 
 (define_insn_reservation "c2_mmx_sse_shft" 1
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "none")
 				   (and (eq_attr "type" "sseishft")
 					(eq_attr "length_immediate" "!0"))))
 			 "c2_decodern,c2_p1")
 
 (define_insn_reservation "c2_mmx_sse_shft_load" 2
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "load")
 				   (and (eq_attr "type" "sseishft")
 					(eq_attr "length_immediate" "!0"))))
 			 "c2_decodern,c2_p1")
 
 (define_insn_reservation "c2_mmx_sse_shft1" 2
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "none")
 				   (and (eq_attr "type" "sseishft")
 					(eq_attr "length_immediate" "0"))))
 			 "c2_decodern,c2_p1")
 
 (define_insn_reservation "c2_mmx_sse_shft1_load" 3
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "load")
 				   (and (eq_attr "type" "sseishft")
 					(eq_attr "length_immediate" "0"))))
 			 "c2_decodern,c2_p1")
 
 (define_insn_reservation "c2_mmx_mul" 3
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "none")
 				   (eq_attr "type" "mmxmul,sseimul")))
 			 "c2_decodern,c2_p1")
 
 (define_insn_reservation "c2_mmx_mul_load" 3
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "none")
 				   (eq_attr "type" "mmxmul,sseimul")))
 			 "c2_decoder0,c2_p2+c2_p1")
 
 (define_insn_reservation "c2_sse_mmxcvt" 4
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "mode" "DI")
 				   (eq_attr "type" "mmxcvt")))
 			 "c2_decodern,c2_p1")
@@ -500,94 +500,94 @@
 ;; FIXME: These are Pentium III only, but we cannot tell here if
 ;; we're generating code for PentiumPro/Pentium II or Pentium III
 ;; (define_insn_reservation "c2_sse_mmxshft" 2
-;;			 (and (eq_attr "cpu" "core2,corei7")
+;;			 (and (eq_attr "cpu" "core2,nehalem")
 ;;			      (and (eq_attr "mode" "TI")
 ;;				   (eq_attr "type" "mmxshft")))
 ;;			 "c2_decodern,c2_p0")
 
 ;; The sfence instruction.
 (define_insn_reservation "c2_sse_sfence" 3
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "unknown")
 				   (eq_attr "type" "sse")))
 			 "c2_decoder0,c2_p4+c2_p3")
 
 ;; FIXME: This reservation is all wrong when we're scheduling sqrtss.
 (define_insn_reservation "c2_sse_SFDF" 3
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "mode" "SF,DF")
 				   (eq_attr "type" "sse")))
 			 "c2_decodern,c2_p0")
 
 (define_insn_reservation "c2_sse_V4SF" 4
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "mode" "V4SF")
 				   (eq_attr "type" "sse")))
 			 "c2_decoder0,c2_p1*2")
 
 (define_insn_reservation "c2_sse_addcmp" 3
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "none")
 				   (eq_attr "type" "sseadd,sseadd1,ssecmp,ssecomi")))
 			 "c2_decodern,c2_p1")
 
 (define_insn_reservation "c2_sse_addcmp_load" 3
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "load")
 				   (eq_attr "type" "sseadd,sseadd1,ssecmp,ssecomi")))
 			 "c2_decodern,c2_p2+c2_p1")
 
 (define_insn_reservation "c2_sse_mul_SF" 4
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "none")
 				   (and (eq_attr "mode" "SF,V4SF")
 					(eq_attr "type" "ssemul"))))
 			"c2_decodern,c2_p0")
 
 (define_insn_reservation "c2_sse_mul_SF_load" 4
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "load")
 				   (and (eq_attr "mode" "SF,V4SF")
 					(eq_attr "type" "ssemul"))))
 			"c2_decodern,c2_p2+c2_p0")
 
 (define_insn_reservation "c2_sse_mul_DF" 5
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "none")
 				   (and (eq_attr "mode" "DF,V2DF")
 					(eq_attr "type" "ssemul"))))
 			"c2_decodern,c2_p0")
 
 (define_insn_reservation "c2_sse_mul_DF_load" 5
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "load")
 				   (and (eq_attr "mode" "DF,V2DF")
 					(eq_attr "type" "ssemul"))))
 			"c2_decodern,c2_p2+c2_p0")
 
 (define_insn_reservation "c2_sse_div_SF" 18
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "none")
 				   (and (eq_attr "mode" "SF,V4SF")
 					(eq_attr "type" "ssediv"))))
 			 "c2_decodern,c2_p0,c2_ssediv*17")
 
 (define_insn_reservation "c2_sse_div_SF_load" 18
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "none")
 				   (and (eq_attr "mode" "SF,V4SF")
 					(eq_attr "type" "ssediv"))))
 			 "c2_decodern,(c2_p2+c2_p0),c2_ssediv*17")
 
 (define_insn_reservation "c2_sse_div_DF" 32
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "none")
 				   (and (eq_attr "mode" "DF,V2DF")
 					(eq_attr "type" "ssediv"))))
 			 "c2_decodern,c2_p0,c2_ssediv*31")
 
 (define_insn_reservation "c2_sse_div_DF_load" 32
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "none")
 				   (and (eq_attr "mode" "DF,V2DF")
 					(eq_attr "type" "ssediv"))))
@@ -595,61 +595,61 @@
 
 ;; FIXME: these have limited throughput
 (define_insn_reservation "c2_sse_icvt_SF" 4
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "none")
 				   (and (eq_attr "mode" "SF")
 					(eq_attr "type" "sseicvt"))))
 			 "c2_decodern,c2_p1")
 
 (define_insn_reservation "c2_sse_icvt_SF_load" 4
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "!none")
 				   (and (eq_attr "mode" "SF")
 					(eq_attr "type" "sseicvt"))))
 			 "c2_decodern,c2_p2+c2_p1")
 
 (define_insn_reservation "c2_sse_icvt_DF" 4
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "none")
 				   (and (eq_attr "mode" "DF")
 					(eq_attr "type" "sseicvt"))))
 			 "c2_decoder0,c2_p0+c2_p1")
 
 (define_insn_reservation "c2_sse_icvt_DF_load" 4
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "!none")
 				   (and (eq_attr "mode" "DF")
 					(eq_attr "type" "sseicvt"))))
 			 "c2_decoder0,(c2_p2+c2_p1)")
 
 (define_insn_reservation "c2_sse_icvt_SI" 3
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "none")
 				   (and (eq_attr "mode" "SI")
 					(eq_attr "type" "sseicvt"))))
 			 "c2_decodern,c2_p1")
 
 (define_insn_reservation "c2_sse_icvt_SI_load" 3
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "!none")
 				   (and (eq_attr "mode" "SI")
 					(eq_attr "type" "sseicvt"))))
 			 "c2_decodern,(c2_p2+c2_p1)")
 
 (define_insn_reservation "c2_sse_mov" 1
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "none")
 				   (eq_attr "type" "ssemov")))
 			 "c2_decodern,(c2_p0|c2_p1|c2_p5)")
 
 (define_insn_reservation "c2_sse_mov_load" 2
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "load")
 				   (eq_attr "type" "ssemov")))
 			 "c2_decodern,c2_p2")
 
 (define_insn_reservation "c2_sse_mov_store" 1
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "store")
 				   (eq_attr "type" "ssemov")))
 			 "c2_decodern,c2_p4+c2_p3")
@@ -663,13 +663,13 @@
 ;; the three decoders.  Loads benefit from micro-op fusion and can be
 ;; treated in the same way.
 (define_insn_reservation "c2_insn" 1
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "none,unknown")
 				   (eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,sseishft1,mmx,mmxcmp")))
 			 "c2_decodern,(c2_p0|c2_p1|c2_p5)")
 
 (define_insn_reservation "c2_insn_load" 4
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "load")
 				   (eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,pop,sseishft1,mmx,mmxcmp")))
 			 "c2_decodern,c2_p2,(c2_p0|c2_p1|c2_p5)")
@@ -677,7 +677,7 @@
 ;; register-memory instructions have three uops,  so they have to be
 ;; decoded on c2_decoder0.
 (define_insn_reservation "c2_insn_store" 1
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "store")
 				   (eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,sseishft1,mmx,mmxcmp")))
 			 "c2_decoder0,(c2_p0|c2_p1|c2_p5),c2_p4+c2_p3")
@@ -685,7 +685,7 @@
 ;; read-modify-store instructions produce 4 uops so they have to be
 ;; decoded on c2_decoder0 as well.
 (define_insn_reservation "c2_insn_both" 4
-			 (and (eq_attr "cpu" "core2,corei7")
+			 (and (eq_attr "cpu" "core2,nehalem")
 			      (and (eq_attr "memory" "both")
 				   (eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,pop,sseishft1,mmx,mmxcmp")))
 			 "c2_decoder0,c2_p2,(c2_p0|c2_p1|c2_p5),c2_p4+c2_p3")
diff --git a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-i386.c
index 26ae601..4d0b264 100644
--- a/gcc/config/i386/driver-i386.c
+++ b/gcc/config/i386/driver-i386.c
@@ -643,13 +643,13 @@ const char *host_detect_local_cpu (int argc, const char **argv)
 	{
 	case 0x1c:
 	case 0x26:
-	  /* Atom.  */
-	  cpu = "atom";
+	  /* Bonnell.  */
+	  cpu = "bonnell";
 	  break;
 	case 0x37:
 	case 0x4d:
 	  /* Silvermont.  */
-	  cpu = "slm";
+	  cpu = "silvermont";
 	  break;
 	case 0x0f:
 	  /* Merom.  */
@@ -663,27 +663,29 @@ const char *host_detect_local_cpu (int argc, const char **argv)
 	case 0x1f:
 	case 0x2e:
 	  /* Nehalem.  */
+	  cpu = "nehalem";
+	  break;
 	case 0x25:
 	case 0x2c:
 	case 0x2f:
 	  /* Westmere.  */
-	  cpu = "corei7";
+	  cpu = "westmere";
 	  break;
 	case 0x2a:
 	case 0x2d:
 	  /* Sandy Bridge.  */
-	  cpu = "corei7-avx";
+	  cpu = "sandybridge";
 	  break;
 	case 0x3a:
 	case 0x3e:
 	  /* Ivy Bridge.  */
-	  cpu = "core-avx-i";
+	  cpu = "ivybridge";
 	  break;
 	case 0x3c:
 	case 0x45:
 	case 0x46:
 	  /* Haswell.  */
-	  cpu = "core-avx2";
+	  cpu = "haswell";
 	  break;
 	default:
 	  if (arch)
@@ -693,24 +695,24 @@ const char *host_detect_local_cpu (int argc, const char **argv)
 		cpu = "broadwell";
 	      else if (has_avx2)
 		/* Assume Haswell.  */
-		cpu = "core-avx2";
+		cpu = "haswell";
 	      else if (has_avx)
 		/* Assume Sandy Bridge.  */
-		cpu = "corei7-avx";
+		cpu = "sandybridge";
 	      else if (has_sse4_2)
 		{
 		  if (has_movbe)
-		    /* Assume SLM.  */
-		    cpu = "slm";
+		    /* Assume Silvermont.  */
+		    cpu = "silvermont";
 		  else
-		    /* Assume Core i7.  */
-		    cpu = "corei7";
+		    /* Assume Nehalem.  */
+		    cpu = "nehalem";
 		}
 	      else if (has_ssse3)
 		{
 		  if (has_movbe)
-		    /* Assume Atom.  */
-		    cpu = "atom";
+		    /* Assume Bonnell.  */
+		    cpu = "bonnell";
 		  else
 		    /* Assume Core 2.  */
 		    cpu = "core2";
diff --git a/gcc/config/i386/i386-c.c b/gcc/config/i386/i386-c.c
index ff1a17a..3710c6e 100644
--- a/gcc/config/i386/i386-c.c
+++ b/gcc/config/i386/i386-c.c
@@ -141,25 +141,35 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
       def_or_undef (parse_in, "__core2");
       def_or_undef (parse_in, "__core2__");
       break;
-    case PROCESSOR_COREI7:
+    case PROCESSOR_NEHALEM:
       def_or_undef (parse_in, "__corei7");
       def_or_undef (parse_in, "__corei7__");
+      def_or_undef (parse_in, "__nehalem");
+      def_or_undef (parse_in, "__nehalem__");
       break;
-    case PROCESSOR_COREI7_AVX:
+    case PROCESSOR_SANDYBRIDGE:
       def_or_undef (parse_in, "__corei7_avx");
       def_or_undef (parse_in, "__corei7_avx__");
+      def_or_undef (parse_in, "__sandybridge");
+      def_or_undef (parse_in, "__sandybridge__");
       break;
     case PROCESSOR_HASWELL:
       def_or_undef (parse_in, "__core_avx2");
       def_or_undef (parse_in, "__core_avx2__");
+      def_or_undef (parse_in, "__haswell");
+      def_or_undef (parse_in, "__haswell__");
       break;
-    case PROCESSOR_ATOM:
+    case PROCESSOR_BONNELL:
       def_or_undef (parse_in, "__atom");
       def_or_undef (parse_in, "__atom__");
+      def_or_undef (parse_in, "__bonnell");
+      def_or_undef (parse_in, "__bonnell__");
       break;
-    case PROCESSOR_SLM:
+    case PROCESSOR_SILVERMONT:
       def_or_undef (parse_in, "__slm");
       def_or_undef (parse_in, "__slm__");
+      def_or_undef (parse_in, "__silvermont");
+      def_or_undef (parse_in, "__silvermont__");
       break;
     /* use PROCESSOR_max to not set/unset the arch macro.  */
     case PROCESSOR_max:
@@ -246,20 +256,25 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
     case PROCESSOR_CORE2:
       def_or_undef (parse_in, "__tune_core2__");
       break;
-    case PROCESSOR_COREI7:
+    case PROCESSOR_NEHALEM:
       def_or_undef (parse_in, "__tune_corei7__");
+      def_or_undef (parse_in, "__tune_nehalem__");
       break;
-    case PROCESSOR_COREI7_AVX:
+    case PROCESSOR_SANDYBRIDGE:
       def_or_undef (parse_in, "__tune_corei7_avx__");
+      def_or_undef (parse_in, "__tune_sandybridge__");
       break;
     case PROCESSOR_HASWELL:
       def_or_undef (parse_in, "__tune_core_avx2__");
+      def_or_undef (parse_in, "__tune_haswell__");
       break;
-    case PROCESSOR_ATOM:
+    case PROCESSOR_BONNELL:
       def_or_undef (parse_in, "__tune_atom__");
+      def_or_undef (parse_in, "__tune_bonnell__");
       break;
-    case PROCESSOR_SLM:
+    case PROCESSOR_SILVERMONT:
       def_or_undef (parse_in, "__tune_slm__");
+      def_or_undef (parse_in, "__tune_silvermont__");
       break;
     case PROCESSOR_GENERIC:
       break;
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 0034d33..2d480b3 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -1935,12 +1935,12 @@ const struct processor_costs *ix86_cost = &pentium_cost;
 #define m_NOCONA (1<<PROCESSOR_NOCONA)
 #define m_P4_NOCONA (m_PENT4 | m_NOCONA)
 #define m_CORE2 (1<<PROCESSOR_CORE2)
-#define m_COREI7 (1<<PROCESSOR_COREI7)
-#define m_COREI7_AVX (1<<PROCESSOR_COREI7_AVX)
+#define m_NEHALEM (1<<PROCESSOR_NEHALEM)
+#define m_SANDYBRIDGE (1<<PROCESSOR_SANDYBRIDGE)
 #define m_HASWELL (1<<PROCESSOR_HASWELL)
-#define m_CORE_ALL (m_CORE2 | m_COREI7  | m_COREI7_AVX | m_HASWELL)
-#define m_ATOM (1<<PROCESSOR_ATOM)
-#define m_SLM (1<<PROCESSOR_SLM)
+#define m_CORE_ALL (m_CORE2 | m_NEHALEM  | m_SANDYBRIDGE | m_HASWELL)
+#define m_BONNELL (1<<PROCESSOR_BONNELL)
+#define m_SILVERMONT (1<<PROCESSOR_SILVERMONT)
 
 #define m_GEODE (1<<PROCESSOR_GEODE)
 #define m_K6 (1<<PROCESSOR_K6)
@@ -2435,6 +2435,14 @@ static const char *const cpu_names[TARGET_CPU_DEFAULT_max] =
   "core-avx2",
   "atom",
   "slm",
+  "nehalem",
+  "westmere",
+  "sandybridge",
+  "ivybridge",
+  "haswell",
+  "broadwell",
+  "bonnell",
+  "silvermont",
   "intel",
   "geode",
   "k6",
@@ -3069,6 +3077,27 @@ ix86_option_override_internal (bool main_args_p,
 #define PTA_AVX512PF		(HOST_WIDE_INT_1 << 42)
 #define PTA_AVX512CD		(HOST_WIDE_INT_1 << 43)
 
+#define PTA_CORE2 \
+  (PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 \
+   | PTA_CX16 | PTA_FXSR)
+#define PTA_NEHALEM \
+  (PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_POPCNT)
+#define PTA_WESTMERE \
+  (PTA_NEHALEM | PTA_AES | PTA_PCLMUL)
+#define PTA_SANDYBRIDGE \
+  (PTA_WESTMERE | PTA_AVX | PTA_XSAVE | PTA_XSAVEOPT)
+#define PTA_IVYBRIDGE \
+  (PTA_SANDYBRIDGE | PTA_FSGSBASE | PTA_RDRND | PTA_F16C)
+#define PTA_HASWELL \
+  (PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI | PTA_BMI2 | PTA_LZCNT \
+   | PTA_FMA | PTA_MOVBE | PTA_RTM | PTA_HLE)
+#define PTA_BROADWELL \
+  (PTA_HASWELL | PTA_ADX | PTA_PRFCHW | PTA_RDSEED)
+#define PTA_BONNELL \
+  (PTA_CORE2 | PTA_MOVBE)
+#define PTA_SILVERMONT \
+  (PTA_WESTMERE | PTA_MOVBE)
+
 /* if this reaches 64, need to widen struct pta flags below */
 
   static struct pta
@@ -3108,46 +3137,26 @@ ix86_option_override_internal (bool main_args_p,
       {"nocona", PROCESSOR_NOCONA, CPU_NONE,
 	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
 	| PTA_CX16 | PTA_NO_SAHF | PTA_FXSR},
-      {"core2", PROCESSOR_CORE2, CPU_CORE2,
-	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-	| PTA_SSSE3 | PTA_CX16 | PTA_FXSR},
-      {"corei7", PROCESSOR_COREI7, CPU_COREI7,
-	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3
-	| PTA_SSE4_1 | PTA_SSE4_2 | PTA_CX16 | PTA_POPCNT | PTA_FXSR},
-      {"corei7-avx", PROCESSOR_COREI7_AVX, CPU_COREI7,
-	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-	| PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX
-	| PTA_CX16 | PTA_POPCNT | PTA_AES | PTA_PCLMUL
-	| PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
-      {"core-avx-i", PROCESSOR_COREI7_AVX, CPU_COREI7,
-	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-	| PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX
-	| PTA_CX16 | PTA_POPCNT | PTA_AES | PTA_PCLMUL | PTA_FSGSBASE
-	| PTA_RDRND | PTA_F16C | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
-      {"core-avx2", PROCESSOR_HASWELL, CPU_COREI7,
-	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-	| PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX | PTA_AVX2
-	| PTA_CX16 | PTA_POPCNT | PTA_AES | PTA_PCLMUL | PTA_FSGSBASE
-	| PTA_RDRND | PTA_F16C | PTA_BMI | PTA_BMI2 | PTA_LZCNT
-	| PTA_FMA | PTA_MOVBE | PTA_RTM | PTA_HLE | PTA_FXSR | PTA_XSAVE
-	| PTA_XSAVEOPT},
-      {"broadwell", PROCESSOR_HASWELL, CPU_COREI7,
-	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-	| PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX | PTA_AVX2
-	| PTA_CX16 | PTA_POPCNT | PTA_AES | PTA_PCLMUL | PTA_FSGSBASE
-	| PTA_RDRND | PTA_F16C | PTA_BMI | PTA_BMI2 | PTA_LZCNT
-	| PTA_FMA | PTA_MOVBE | PTA_RTM | PTA_HLE | PTA_FXSR | PTA_XSAVE
-	| PTA_XSAVEOPT | PTA_ADX | PTA_PRFCHW | PTA_RDSEED},
-      {"atom", PROCESSOR_ATOM, CPU_ATOM,
-	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
-	| PTA_SSSE3 | PTA_CX16 | PTA_MOVBE | PTA_FXSR},
-      {"slm", PROCESSOR_SLM, CPU_SLM,
-	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3
-	| PTA_SSE4_1 | PTA_SSE4_2 | PTA_CX16 | PTA_POPCNT | PTA_AES
-	| PTA_PCLMUL | PTA_RDRND | PTA_MOVBE | PTA_FXSR},
-      {"intel", PROCESSOR_SLM, CPU_SLM,
-	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3
-	| PTA_SSE4_1 | PTA_SSE4_2 | PTA_CX16 | PTA_POPCNT | PTA_FXSR},
+      {"core2", PROCESSOR_CORE2, CPU_CORE2, PTA_CORE2},
+      {"nehalem", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM},
+      {"corei7", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM},
+      {"westmere", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_WESTMERE},
+      {"sandybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
+	PTA_SANDYBRIDGE},
+      {"corei7-avx", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
+	PTA_SANDYBRIDGE},
+      {"ivybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
+	PTA_IVYBRIDGE},
+      {"core-avx-i", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
+	PTA_IVYBRIDGE},
+      {"haswell", PROCESSOR_HASWELL, CPU_NEHALEM, PTA_HASWELL},
+      {"core-avx2", PROCESSOR_HASWELL, CPU_NEHALEM, PTA_HASWELL},
+      {"broadwell", PROCESSOR_HASWELL, CPU_NEHALEM, PTA_BROADWELL},
+      {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
+      {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
+      {"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
+      {"slm", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
+      {"intel", PROCESSOR_SILVERMONT, CPU_SLM, PTA_NEHALEM},
       {"geode", PROCESSOR_GEODE, CPU_GEODE,
 	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE | PTA_PRFCHW},
       {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},
@@ -17879,7 +17888,7 @@ ix86_lea_outperforms (rtx insn, unsigned int regno0, unsigned int regno1,
   /* For Silvermont if using a 2-source or 3-source LEA for
      non-destructive destination purposes, or due to wanting
      ability to use SCALE, the use of LEA is justified.  */
-  if (ix86_tune == PROCESSOR_SLM)
+  if (ix86_tune == PROCESSOR_SILVERMONT)
     {
       if (has_scale)
 	return true;
@@ -18247,7 +18256,7 @@ ix86_split_lea_for_addr (rtx insn, rtx operands[], enum machine_mode mode)
 
 /* Return true if it is ok to optimize an ADD operation to LEA
    operation to avoid flag register consumation.  For most processors,
-   ADD is faster than LEA.  For the processors like ATOM, if the
+   ADD is faster than LEA.  For the processors like BONNELL, if the
    destination register of LEA holds an actual address which will be
    used soon, LEA is better and otherwise ADD is better.  */
 
@@ -25005,8 +25014,8 @@ ix86_issue_rate (void)
   switch (ix86_tune)
     {
     case PROCESSOR_PENTIUM:
-    case PROCESSOR_ATOM:
-    case PROCESSOR_SLM:
+    case PROCESSOR_BONNELL:
+    case PROCESSOR_SILVERMONT:
     case PROCESSOR_K6:
     case PROCESSOR_BTVER2:
     case PROCESSOR_PENTIUM4:
@@ -25026,8 +25035,8 @@ ix86_issue_rate (void)
     case PROCESSOR_BDVER3:
     case PROCESSOR_BDVER4:
     case PROCESSOR_CORE2:
-    case PROCESSOR_COREI7:
-    case PROCESSOR_COREI7_AVX:
+    case PROCESSOR_NEHALEM:
+    case PROCESSOR_SANDYBRIDGE:
     case PROCESSOR_HASWELL:
       return 4;
 
@@ -25324,8 +25333,8 @@ ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
       break;
 
     case PROCESSOR_CORE2:
-    case PROCESSOR_COREI7:
-    case PROCESSOR_COREI7_AVX:
+    case PROCESSOR_NEHALEM:
+    case PROCESSOR_SANDYBRIDGE:
     case PROCESSOR_HASWELL:
       memory = get_attr_memory (insn);
 
@@ -25347,7 +25356,7 @@ ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
 	}
       break;
 
-    case PROCESSOR_SLM:
+    case PROCESSOR_SILVERMONT:
       if (!reload_completed)
 	return cost;
 
@@ -25411,11 +25420,11 @@ ia32_multipass_dfa_lookahead (void)
         return 4;
 
     case PROCESSOR_CORE2:
-    case PROCESSOR_COREI7:
-    case PROCESSOR_COREI7_AVX:
+    case PROCESSOR_NEHALEM:
+    case PROCESSOR_SANDYBRIDGE:
     case PROCESSOR_HASWELL:
-    case PROCESSOR_ATOM:
-    case PROCESSOR_SLM:
+    case PROCESSOR_BONNELL:
+    case PROCESSOR_SILVERMONT:
       /* Generally, we want haifa-sched:max_issue() to look ahead as far
 	 as many instructions can be executed on a cycle, i.e.,
 	 issue_rate.  I wonder why tuning for many CPUs does not do this.  */
@@ -25557,7 +25566,7 @@ do_reorder_for_imul (rtx *ready, int n_ready)
   int index = -1;
   int i;
 
-  if (ix86_tune != PROCESSOR_ATOM)
+  if (ix86_tune != PROCESSOR_BONNELL)
     return index;
 
   /* Check that IMUL instruction is on the top of ready list.  */
@@ -25637,7 +25646,7 @@ swap_top_of_ready_list (rtx *ready, int n_ready)
   int clock2 = -1;
   #define INSN_TICK(INSN) (HID (INSN)->tick)
 
-  if (ix86_tune != PROCESSOR_SLM)
+  if (ix86_tune != PROCESSOR_SILVERMONT)
     return false;
 
   if (!NONDEBUG_INSN_P (top))
@@ -25709,8 +25718,9 @@ ix86_sched_reorder (FILE *dump, int sched_verbose, rtx *ready, int *pn_ready,
   /* Set up issue rate.  */
   issue_rate = ix86_issue_rate ();
 
-  /* Do reodering for Atom/SLM only.  */
-  if (ix86_tune != PROCESSOR_ATOM && ix86_tune != PROCESSOR_SLM)
+  /* Do reodering for BONNELL/SILVERMONT only.  */
+  if (ix86_tune != PROCESSOR_BONNELL
+      && ix86_tune != PROCESSOR_SILVERMONT)
     return issue_rate;
 
   /* Nothing to do if ready list contains only 1 instruction.  */
@@ -26165,8 +26175,8 @@ ix86_sched_init_global (FILE *dump ATTRIBUTE_UNUSED,
   switch (ix86_tune)
     {
     case PROCESSOR_CORE2:
-    case PROCESSOR_COREI7:
-    case PROCESSOR_COREI7_AVX:
+    case PROCESSOR_NEHALEM:
+    case PROCESSOR_SANDYBRIDGE:
     case PROCESSOR_HASWELL:
       /* Do not perform multipass scheduling for pre-reload schedule
          to save compile time.  */
@@ -30040,16 +30050,16 @@ get_builtin_code_for_version (tree decl, tree *predicate_list)
 	      arg_str = "core2";
 	      priority = P_PROC_SSSE3;
 	      break;
-	    case PROCESSOR_COREI7:
-	      arg_str = "corei7";
+	    case PROCESSOR_NEHALEM:
+	      arg_str = "nehalem";
 	      priority = P_PROC_SSE4_2;
 	      break;
-            case PROCESSOR_COREI7_AVX:
-              arg_str = "corei7-avx";
+            case PROCESSOR_SANDYBRIDGE:
+              arg_str = "sandybridge";
               priority = P_PROC_SSE4_2;
               break;
-	    case PROCESSOR_ATOM:
-	      arg_str = "atom";
+	    case PROCESSOR_BONNELL:
+	      arg_str = "bonnell";
 	      priority = P_PROC_SSSE3;
 	      break;
 	    case PROCESSOR_AMDFAM10:
@@ -30939,12 +30949,12 @@ fold_builtin_cpu (tree fndecl, tree *args)
     M_INTEL = 1,
     M_AMD,
     M_CPU_TYPE_START,
-    M_INTEL_ATOM,
+    M_INTEL_BONNELL,
     M_INTEL_CORE2,
     M_INTEL_COREI7,
     M_AMDFAM10H,
     M_AMDFAM15H,
-    M_INTEL_SLM,
+    M_INTEL_SILVERMONT,
     M_CPU_SUBTYPE_START,
     M_INTEL_COREI7_NEHALEM,
     M_INTEL_COREI7_WESTMERE,
@@ -30967,8 +30977,8 @@ fold_builtin_cpu (tree fndecl, tree *args)
     {
       {"amd", M_AMD},
       {"intel", M_INTEL},
-      {"atom", M_INTEL_ATOM},
-      {"slm", M_INTEL_SLM},
+      {"atom", M_INTEL_BONNELL},
+      {"slm", M_INTEL_SILVERMONT},
       {"core2", M_INTEL_CORE2},
       {"corei7", M_INTEL_COREI7},
       {"nehalem", M_INTEL_COREI7_NEHALEM},
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index b6e7d46..aafc1ac 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -301,9 +301,11 @@ extern const struct processor_costs ix86_size_cost;
 #define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON)
 #define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA)
 #define TARGET_CORE2 (ix86_tune == PROCESSOR_CORE2)
-#define TARGET_COREI7 (ix86_tune == PROCESSOR_COREI7)
-#define TARGET_COREI7_AVX (ix86_tune == PROCESSOR_COREI7_AVX)
+#define TARGET_NEHALEM (ix86_tune == PROCESSOR_NEHALEM)
+#define TARGET_SANDYBRIDGE (ix86_tune == PROCESSOR_SANDYBRIDGE)
 #define TARGET_HASWELL (ix86_tune == PROCESSOR_HASWELL)
+#define TARGET_BONNELL (ix86_tune == PROCESSOR_BONNELL)
+#define TARGET_SILVERMONT (ix86_tune == PROCESSOR_SILVERMONT)
 #define TARGET_GENERIC (ix86_tune == PROCESSOR_GENERIC)
 #define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10)
 #define TARGET_BDVER1 (ix86_tune == PROCESSOR_BDVER1)
@@ -312,8 +314,6 @@ extern const struct processor_costs ix86_size_cost;
 #define TARGET_BDVER4 (ix86_tune == PROCESSOR_BDVER4)
 #define TARGET_BTVER1 (ix86_tune == PROCESSOR_BTVER1)
 #define TARGET_BTVER2 (ix86_tune == PROCESSOR_BTVER2)
-#define TARGET_ATOM (ix86_tune == PROCESSOR_ATOM)
-#define TARGET_SLM (ix86_tune == PROCESSOR_SLM)
 
 /* Feature tests against the various tunings.  */
 enum ix86_tune_indices {
@@ -625,9 +625,17 @@ enum target_cpu_default
   TARGET_CPU_DEFAULT_core2,
   TARGET_CPU_DEFAULT_corei7,
   TARGET_CPU_DEFAULT_corei7_avx,
-  TARGET_CPU_DEFAULT_haswell,
+  TARGET_CPU_DEFAULT_core_avx2,
   TARGET_CPU_DEFAULT_atom,
   TARGET_CPU_DEFAULT_slm,
+  TARGET_CPU_DEFAULT_nehalem,
+  TARGET_CPU_DEFAULT_westmere,
+  TARGET_CPU_DEFAULT_sandybridge,
+  TARGET_CPU_DEFAULT_ivybridge,
+  TARGET_CPU_DEFAULT_haswell,
+  TARGET_CPU_DEFAULT_broadwell,
+  TARGET_CPU_DEFAULT_bonnell,
+  TARGET_CPU_DEFAULT_silvermont,
   TARGET_CPU_DEFAULT_intel,
 
   TARGET_CPU_DEFAULT_geode,
@@ -2220,9 +2228,11 @@ enum processor_type
   PROCESSOR_K8,
   PROCESSOR_NOCONA,
   PROCESSOR_CORE2,
-  PROCESSOR_COREI7,
-  PROCESSOR_COREI7_AVX,
+  PROCESSOR_NEHALEM,
+  PROCESSOR_SANDYBRIDGE,
   PROCESSOR_HASWELL,
+  PROCESSOR_BONNELL,
+  PROCESSOR_SILVERMONT,
   PROCESSOR_GENERIC,
   PROCESSOR_AMDFAM10,
   PROCESSOR_BDVER1,
@@ -2231,8 +2241,6 @@ enum processor_type
   PROCESSOR_BDVER4,
   PROCESSOR_BTVER1,
   PROCESSOR_BTVER2,
-  PROCESSOR_ATOM,
-  PROCESSOR_SLM,
   PROCESSOR_max
 };
 
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index ab5b33f..7a16c8e 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -354,7 +354,7 @@
 
 
 ;; Processor type.
-(define_attr "cpu" "none,pentium,pentiumpro,geode,k6,athlon,k8,core2,corei7,
+(define_attr "cpu" "none,pentium,pentiumpro,geode,k6,athlon,k8,core2,nehalem,
 		    atom,slm,generic,amdfam10,bdver1,bdver2,bdver3,bdver4,
 		    btver1,btver2"
   (const (symbol_ref "ix86_schedule")))
diff --git a/gcc/config/i386/x86-tune.def b/gcc/config/i386/x86-tune.def
index 9539685..88e0402 100644
--- a/gcc/config/i386/x86-tune.def
+++ b/gcc/config/i386/x86-tune.def
@@ -40,7 +40,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
 
 /* X86_TUNE_SCHEDULE: Enable scheduling.  */
 DEF_TUNE (X86_TUNE_SCHEDULE, "schedule",
-          m_PENT | m_PPRO | m_CORE_ALL | m_ATOM | m_SLM | m_K6_GEODE 
+          m_PENT | m_PPRO | m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_K6_GEODE
           | m_AMD_MULTIPLE | m_GENERIC)
 
 /* X86_TUNE_PARTIAL_REG_DEPENDENCY: Enable more register renaming
@@ -48,7 +48,7 @@ DEF_TUNE (X86_TUNE_SCHEDULE, "schedule",
    over partial stores.  For example preffer MOVZBL or MOVQ to load 8bit
    value over movb.  */
 DEF_TUNE (X86_TUNE_PARTIAL_REG_DEPENDENCY, "partial_reg_dependency",
-          m_P4_NOCONA | m_CORE_ALL | m_ATOM | m_SLM | m_AMD_MULTIPLE 
+          m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_AMD_MULTIPLE
           | m_GENERIC)
 
 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: This knob promotes all store
@@ -58,7 +58,7 @@ DEF_TUNE (X86_TUNE_PARTIAL_REG_DEPENDENCY, "partial_reg_dependency",
    SPECfp regression, while enabling it on K8 brings roughly 2.4% regression
    that can be partly masked by careful scheduling of moves.  */
 DEF_TUNE (X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY, "sse_partial_reg_dependency",
-          m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_ATOM | m_SLM | m_AMDFAM10 
+          m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_AMDFAM10
           | m_BDVER | m_GENERIC)
 
 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
@@ -84,13 +84,13 @@ DEF_TUNE (X86_TUNE_PARTIAL_FLAG_REG_STALL, "partial_flag_reg_stall",
 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
    partial dependencies.  */
 DEF_TUNE (X86_TUNE_MOVX, "movx",
-          m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_ATOM | m_SLM | m_GEODE 
+          m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_GEODE
           | m_AMD_MULTIPLE  | m_GENERIC)
 
 /* X86_TUNE_MEMORY_MISMATCH_STALL: Avoid partial stores that are followed by
    full sized loads.  */
 DEF_TUNE (X86_TUNE_MEMORY_MISMATCH_STALL, "memory_mismatch_stall",
-          m_P4_NOCONA | m_CORE_ALL | m_ATOM | m_SLM | m_AMD_MULTIPLE | m_GENERIC)
+          m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_AMD_MULTIPLE | m_GENERIC)
 
 /* X86_TUNE_FUSE_CMP_AND_BRANCH_32: Fuse compare with a subsequent
    conditional jump instruction for 32 bit TARGET.
@@ -102,29 +102,29 @@ DEF_TUNE (X86_TUNE_FUSE_CMP_AND_BRANCH_32, "fuse_cmp_and_branch_32",
    conditional jump instruction for TARGET_64BIT.
    FIXME: revisit for generic.  */
 DEF_TUNE (X86_TUNE_FUSE_CMP_AND_BRANCH_64, "fuse_cmp_and_branch_64",
-          m_COREI7 | m_COREI7_AVX | m_HASWELL | m_BDVER)
+          m_NEHALEM | m_SANDYBRIDGE | m_HASWELL | m_BDVER)
 
 /* X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS: Fuse compare with a
    subsequent conditional jump instruction when the condition jump
    check sign flag (SF) or overflow flag (OF).  */
 DEF_TUNE (X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS, "fuse_cmp_and_branch_soflags",
-          m_COREI7 | m_COREI7_AVX | m_HASWELL | m_BDVER)
+          m_NEHALEM | m_SANDYBRIDGE | m_HASWELL | m_BDVER)
 
 /* X86_TUNE_FUSE_ALU_AND_BRANCH: Fuse alu with a subsequent conditional
    jump instruction when the alu instruction produces the CCFLAG consumed by
    the conditional jump instruction. */
 DEF_TUNE (X86_TUNE_FUSE_ALU_AND_BRANCH, "fuse_alu_and_branch",
-          m_COREI7_AVX | m_HASWELL)
+          m_SANDYBRIDGE | m_HASWELL)
 
 /* X86_TUNE_REASSOC_INT_TO_PARALLEL: Try to produce parallel computations
    during reassociation of integer computation.  */
 DEF_TUNE (X86_TUNE_REASSOC_INT_TO_PARALLEL, "reassoc_int_to_parallel",
-          m_ATOM)
+          m_BONNELL)
 
 /* X86_TUNE_REASSOC_FP_TO_PARALLEL: Try to produce parallel computations
    during reassociation of fp computation.  */
 DEF_TUNE (X86_TUNE_REASSOC_FP_TO_PARALLEL, "reassoc_fp_to_parallel",
-          m_ATOM | m_SLM | m_HASWELL | m_BDVER1 | m_BDVER2 | m_GENERIC)
+          m_BONNELL | m_SILVERMONT | m_HASWELL | m_BDVER1 | m_BDVER2 | m_GENERIC)
 
 /*****************************************************************************/
 /* Function prologue, epilogue and function calling sequences.               */
@@ -142,33 +142,33 @@ DEF_TUNE (X86_TUNE_REASSOC_FP_TO_PARALLEL, "reassoc_fp_to_parallel",
    Bobcat and Generic.  This is because disabling it causes large
    regression on mgrid due to IRA limitation leading to unecessary
    use of the frame pointer in 32bit mode.  */
-DEF_TUNE (X86_TUNE_ACCUMULATE_OUTGOING_ARGS, "accumulate_outgoing_args", 
-	  m_PPRO | m_P4_NOCONA | m_ATOM | m_SLM | m_AMD_MULTIPLE | m_GENERIC)
+DEF_TUNE (X86_TUNE_ACCUMULATE_OUTGOING_ARGS, "accumulate_outgoing_args",
+	  m_PPRO | m_P4_NOCONA | m_BONNELL | m_SILVERMONT | m_AMD_MULTIPLE | m_GENERIC)
 
 /* X86_TUNE_PROLOGUE_USING_MOVE: Do not use push/pop in prologues that are
    considered on critical path.  */
-DEF_TUNE (X86_TUNE_PROLOGUE_USING_MOVE, "prologue_using_move", 
+DEF_TUNE (X86_TUNE_PROLOGUE_USING_MOVE, "prologue_using_move",
           m_PPRO | m_ATHLON_K8)
 
 /* X86_TUNE_PROLOGUE_USING_MOVE: Do not use push/pop in epilogues that are
    considered on critical path.  */
 DEF_TUNE (X86_TUNE_EPILOGUE_USING_MOVE, "epilogue_using_move",
-          m_PPRO | m_ATHLON_K8)	
+          m_PPRO | m_ATHLON_K8)
 
 /* X86_TUNE_USE_LEAVE: Use "leave" instruction in epilogues where it fits.  */
-DEF_TUNE (X86_TUNE_USE_LEAVE, "use_leave", 
+DEF_TUNE (X86_TUNE_USE_LEAVE, "use_leave",
 	  m_386 | m_CORE_ALL | m_K6_GEODE | m_AMD_MULTIPLE | m_GENERIC)
 
 /* X86_TUNE_PUSH_MEMORY: Enable generation of "push mem" instructions.
    Some chips, like 486 and Pentium works faster with separate load
    and push instructions.  */
-DEF_TUNE (X86_TUNE_PUSH_MEMORY, "push_memory", 
-          m_386 | m_P4_NOCONA | m_CORE_ALL | m_K6_GEODE | m_AMD_MULTIPLE 
+DEF_TUNE (X86_TUNE_PUSH_MEMORY, "push_memory",
+          m_386 | m_P4_NOCONA | m_CORE_ALL | m_K6_GEODE | m_AMD_MULTIPLE
           | m_GENERIC)
 
 /* X86_TUNE_SINGLE_PUSH: Enable if single push insn is preferred
    over esp subtraction.  */
-DEF_TUNE (X86_TUNE_SINGLE_PUSH, "single_push", m_386 | m_486 | m_PENT 
+DEF_TUNE (X86_TUNE_SINGLE_PUSH, "single_push", m_386 | m_486 | m_PENT
           | m_K6_GEODE)
 
 /* X86_TUNE_DOUBLE_PUSH. Enable if double push insn is preferred
@@ -189,7 +189,7 @@ DEF_TUNE (X86_TUNE_DOUBLE_POP, "double_pop", m_PENT)
 
 /* X86_TUNE_PAD_SHORT_FUNCTION: Make every function to be at least 4
    instructions long.  */
-DEF_TUNE (X86_TUNE_PAD_SHORT_FUNCTION, "pad_short_function", m_ATOM)
+DEF_TUNE (X86_TUNE_PAD_SHORT_FUNCTION, "pad_short_function", m_BONNELL)
 
 /* X86_TUNE_PAD_RETURNS: Place NOP before every RET that is a destination
    of conditional jump or directly preceded by other jump instruction.
@@ -202,7 +202,7 @@ DEF_TUNE (X86_TUNE_PAD_RETURNS, "pad_returns",
 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
    than 4 branch instructions in the 16 byte window.  */
 DEF_TUNE (X86_TUNE_FOUR_JUMP_LIMIT, "four_jump_limit",
-          m_PPRO | m_P4_NOCONA | m_ATOM | m_SLM | m_ATHLON_K8 | m_AMDFAM10)
+          m_PPRO | m_P4_NOCONA | m_BONNELL | m_SILVERMONT | m_ATHLON_K8 | m_AMDFAM10)
 
 /*****************************************************************************/
 /* Integer instruction selection tuning                                      */
@@ -224,26 +224,26 @@ DEF_TUNE (X86_TUNE_READ_MODIFY, "read_modify", ~(m_PENT | m_PPRO))
 
 /* X86_TUNE_USE_INCDEC: Enable use of inc/dec instructions.   */
 DEF_TUNE (X86_TUNE_USE_INCDEC, "use_incdec",
-          ~(m_P4_NOCONA | m_CORE_ALL | m_ATOM | m_SLM | m_GENERIC))
+          ~(m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_GENERIC))
 
 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
    for DFmode copies */
 DEF_TUNE (X86_TUNE_INTEGER_DFMODE_MOVES, "integer_dfmode_moves",
-          ~(m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_ATOM | m_SLM 
+          ~(m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT
           | m_GEODE | m_AMD_MULTIPLE | m_GENERIC))
 
 /* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag
    will impact LEA instruction selection. */
-DEF_TUNE (X86_TUNE_OPT_AGU, "opt_agu", m_ATOM | m_SLM)
+DEF_TUNE (X86_TUNE_OPT_AGU, "opt_agu", m_BONNELL | m_SILVERMONT)
 
 /* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
-   vector path on AMD machines. 
+   vector path on AMD machines.
    FIXME: Do we need to enable this for core? */
 DEF_TUNE (X86_TUNE_SLOW_IMUL_IMM32_MEM, "slow_imul_imm32_mem",
           m_K8 | m_AMDFAM10)
 
 /* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
-   machines. 
+   machines.
    FIXME: Do we need to enable this for core? */
 DEF_TUNE (X86_TUNE_SLOW_IMUL_IMM8, "slow_imul_imm8",
           m_K8 | m_AMDFAM10)
@@ -251,7 +251,7 @@ DEF_TUNE (X86_TUNE_SLOW_IMUL_IMM8, "slow_imul_imm8",
 /* X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE: Try to avoid memory operands for
    a conditional move.  */
 DEF_TUNE (X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE, "avoid_mem_opnd_for_cmove",
-	  m_ATOM | m_SLM)
+	  m_BONNELL | m_SILVERMONT)
 
 /* X86_TUNE_SINGLE_STRINGOP: Enable use of single string operations, such
    as MOVS and STOS (without a REP prefix) to move/set sequences of bytes.  */
@@ -268,15 +268,15 @@ DEF_TUNE (X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES,
 
 /* X86_TUNE_USE_SAHF: Controls use of SAHF.  */
 DEF_TUNE (X86_TUNE_USE_SAHF, "use_sahf",
-          m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_ATOM | m_SLM | m_K6_GEODE
+          m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_K6_GEODE
           | m_K8 | m_AMDFAM10 | m_BDVER | m_BTVER | m_GENERIC)
 
 /* X86_TUNE_USE_CLTD: Controls use of CLTD and CTQO instructions.  */
-DEF_TUNE (X86_TUNE_USE_CLTD, "use_cltd", ~(m_PENT | m_ATOM | m_SLM | m_K6))
+DEF_TUNE (X86_TUNE_USE_CLTD, "use_cltd", ~(m_PENT | m_BONNELL | m_SILVERMONT | m_K6))
 
 /* X86_TUNE_USE_BT: Enable use of BT (bit test) instructions.  */
 DEF_TUNE (X86_TUNE_USE_BT, "use_bt",
-          m_CORE_ALL | m_ATOM | m_SLM | m_AMD_MULTIPLE | m_GENERIC)
+          m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_AMD_MULTIPLE | m_GENERIC)
 
 /*****************************************************************************/
 /* 387 instruction selection tuning                                          */
@@ -285,21 +285,21 @@ DEF_TUNE (X86_TUNE_USE_BT, "use_bt",
 /* X86_TUNE_USE_HIMODE_FIOP: Enables use of x87 instructions with 16bit
    integer operand.
    FIXME: Why this is disabled for modern chips?  */
-DEF_TUNE (X86_TUNE_USE_HIMODE_FIOP, "use_himode_fiop", 
+DEF_TUNE (X86_TUNE_USE_HIMODE_FIOP, "use_himode_fiop",
           m_386 | m_486 | m_K6_GEODE)
 
 /* X86_TUNE_USE_SIMODE_FIOP: Enables use of x87 instructions with 32bit
    integer operand.  */
 DEF_TUNE (X86_TUNE_USE_SIMODE_FIOP, "use_simode_fiop",
-          ~(m_PENT | m_PPRO | m_CORE_ALL | m_ATOM 
-            | m_SLM | m_AMD_MULTIPLE | m_GENERIC))
+          ~(m_PENT | m_PPRO | m_CORE_ALL | m_BONNELL
+            | m_SILVERMONT | m_AMD_MULTIPLE | m_GENERIC))
 
 /* X86_TUNE_USE_FFREEP: Use freep instruction instead of fstp.  */
 DEF_TUNE (X86_TUNE_USE_FFREEP, "use_ffreep", m_AMD_MULTIPLE)
 
 /* X86_TUNE_EXT_80387_CONSTANTS: Use fancy 80387 constants, such as PI.  */
 DEF_TUNE (X86_TUNE_EXT_80387_CONSTANTS, "ext_80387_constants",
-          m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_ATOM | m_SLM | m_K6_GEODE
+          m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_K6_GEODE
           | m_ATHLON_K8 | m_GENERIC)
 
 /*****************************************************************************/
@@ -308,7 +308,7 @@ DEF_TUNE (X86_TUNE_EXT_80387_CONSTANTS, "ext_80387_constants",
 
 /* X86_TUNE_VECTORIZE_DOUBLE: Enable double precision vector
    instructions.  */
-DEF_TUNE (X86_TUNE_VECTORIZE_DOUBLE, "vectorize_double", ~m_ATOM)
+DEF_TUNE (X86_TUNE_VECTORIZE_DOUBLE, "vectorize_double", ~m_BONNELL)
 
 /* X86_TUNE_GENERAL_REGS_SSE_SPILL: Try to spill general regs to SSE
    regs instead of memory.  */
@@ -318,12 +318,12 @@ DEF_TUNE (X86_TUNE_GENERAL_REGS_SSE_SPILL, "general_regs_sse_spill",
 /* X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL: Use movups for misaligned loads instead
    of a sequence loading registers by parts.  */
 DEF_TUNE (X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL, "sse_unaligned_load_optimal",
-          m_COREI7 | m_COREI7_AVX | m_HASWELL | m_AMDFAM10 | m_BDVER | m_BTVER | m_SLM | m_GENERIC)
+          m_NEHALEM | m_SANDYBRIDGE | m_HASWELL | m_AMDFAM10 | m_BDVER | m_BTVER | m_SILVERMONT | m_GENERIC)
 
 /* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL: Use movups for misaligned stores instead
    of a sequence loading registers by parts.  */
 DEF_TUNE (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL, "sse_unaligned_store_optimal",
-          m_COREI7 | m_COREI7_AVX | m_HASWELL | m_BDVER | m_SLM | m_GENERIC)
+          m_NEHALEM | m_SANDYBRIDGE | m_HASWELL | m_BDVER | m_SILVERMONT | m_GENERIC)
 
 /* Use packed single precision instructions where posisble.  I.e. movups instead
    of movupd.  */
@@ -360,7 +360,7 @@ DEF_TUNE (X86_TUNE_INTER_UNIT_CONVERSIONS, "inter_unit_conversions",
 /* X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS: Try to split memory operand for
    fp converts to destination register.  */
 DEF_TUNE (X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS, "split_mem_opnd_for_fp_converts",
-          m_SLM)
+          m_SILVERMONT)
 
 /* X86_TUNE_USE_VECTOR_FP_CONVERTS: Prefer vector packed SSE conversion
    from FP to FP.  This form of instructions avoids partial write to the
@@ -378,13 +378,13 @@ DEF_TUNE (X86_TUNE_USE_VECTOR_CONVERTS, "use_vector_converts", m_AMDFAM10)
 
 /* X86_TUNE_AVX256_UNALIGNED_LOAD_OPTIMAL: if false, unaligned loads are
    split.  */
-DEF_TUNE (X86_TUNE_AVX256_UNALIGNED_LOAD_OPTIMAL, "256_unaligned_load_optimal", 
-          ~(m_COREI7 | m_COREI7_AVX | m_GENERIC))
+DEF_TUNE (X86_TUNE_AVX256_UNALIGNED_LOAD_OPTIMAL, "256_unaligned_load_optimal",
+          ~(m_NEHALEM | m_SANDYBRIDGE | m_GENERIC))
 
 /* X86_TUNE_AVX256_UNALIGNED_STORE_OPTIMAL: if false, unaligned stores are
    split.  */
-DEF_TUNE (X86_TUNE_AVX256_UNALIGNED_STORE_OPTIMAL, "256_unaligned_store_optimal", 
-          ~(m_COREI7 | m_COREI7_AVX | m_BDVER | m_GENERIC))
+DEF_TUNE (X86_TUNE_AVX256_UNALIGNED_STORE_OPTIMAL, "256_unaligned_store_optimal",
+          ~(m_NEHALEM | m_SANDYBRIDGE | m_BDVER | m_GENERIC))
 
 /* X86_TUNE_AVX128_OPTIMAL: Enable 128-bit AVX instruction generation for
    the auto-vectorizer.  */
@@ -401,7 +401,7 @@ DEF_TUNE (X86_TUNE_DOUBLE_WITH_ADD, "double_with_add", ~m_386)
 /* X86_TUNE_ALWAYS_FANCY_MATH_387: controls use of fancy 387 operations,
    such as fsqrt, fprem, fsin, fcos, fsincos etc.
    Should be enabled for all targets that always has coprocesor.  */
-DEF_TUNE (X86_TUNE_ALWAYS_FANCY_MATH_387, "always_fancy_math_387", 
+DEF_TUNE (X86_TUNE_ALWAYS_FANCY_MATH_387, "always_fancy_math_387",
           ~(m_386 | m_486))
 
 /* X86_TUNE_UNROLL_STRLEN: Produce (quite lame) unrolled sequence for
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 93468a8..a10b6f5 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -14648,34 +14648,38 @@ SSE2 and SSE3 instruction set support.
 Intel Core 2 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3 and SSSE3
 instruction set support.
 
-@item corei7
-Intel Core i7 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
+@item nehalem
+Intel Nehalem CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
 SSE4.1, SSE4.2 and POPCNT instruction set support.
 
-@item corei7-avx
-Intel Core i7 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
+@item westmere
+Intel Westmere CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
+SSE4.1, SSE4.2, POPCNT, AES and PCLMUL instruction set support.
+
+@item sandybridge
+Intel Sandy Bridge CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
 SSE4.1, SSE4.2, POPCNT, AVX, AES and PCLMUL instruction set support.
 
-@item core-avx-i
-Intel Core CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
+@item ivybridge
+Intel Ivy Bridge CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
 SSE4.1, SSE4.2, POPCNT, AVX, AES, PCLMUL, FSGSBASE, RDRND and F16C
 instruction set support.
 
-@item core-avx2
-Intel Core CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
+@item haswell
+Intel Haswell CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
 SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
 BMI, BMI2 and F16C instruction set support.
 
 @item broadwell
 Intel Broadwell CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
 SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
-BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW instruction set support.
+BMI, BMI2, F16C, RDSEED, ADCX and PREFETCHW instruction set support.
 
-@item atom
-Intel Atom CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3 and SSSE3
+@item bonnell
+Intel Bonnell CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3 and SSSE3
 instruction set support.
 
-@item slm
+@item silvermont
 Intel Silvermont CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
 SSE4.1, SSE4.2, POPCNT, AES, PCLMUL and RDRND instruction set support.
 
diff --git a/libgcc/config/i386/cpuinfo.c b/libgcc/config/i386/cpuinfo.c
index 1a891e0..4b0c189 100644
--- a/libgcc/config/i386/cpuinfo.c
+++ b/libgcc/config/i386/cpuinfo.c
@@ -56,12 +56,12 @@ enum processor_vendor
 
 enum processor_types
 {
-  INTEL_ATOM = 1,
+  INTEL_BONNELL = 1,
   INTEL_CORE2,
   INTEL_COREI7,
   AMDFAM10H,
   AMDFAM15H,
-  INTEL_SLM,
+  INTEL_SILVERMONT,
   CPU_TYPE_MAX
 };
 
@@ -167,13 +167,13 @@ get_intel_cpu (unsigned int family, unsigned int model, unsigned int brand_id)
 	    {
 	    case 0x1c:
 	    case 0x26:
-	      /* Atom.  */
-	      __cpu_model.__cpu_type = INTEL_ATOM;
+	      /* Bonnell.  */
+	      __cpu_model.__cpu_type = INTEL_BONNELL;
 	      break;
 	    case 0x37:
 	    case 0x4d:
 	      /* Silvermont.  */
-	      __cpu_model.__cpu_type = INTEL_SLM;
+	      __cpu_model.__cpu_type = INTEL_SILVERMONT;
 	      break;
 	    case 0x1a:
 	    case 0x1e:
