diff mbox

[x86] march aliases

Message ID 20131220164740.GA46311@msticlxl7.ims.intel.com
State New
Headers show

Commit Message

Ilya Tocar Dec. 20, 2013, 4:47 p.m. UTC 
> > Perhaps we should add sandybridge, ivybridge and haswell aliases for
> > corei7-avx, core-avx-i, core-avx2?  I mean, it is a nightmare to remember
> > which one has the i7 in and which doesn't even for me.
> 
> Yes please, I think this is a good idea.

I've added aliases for haswell, sandybridge, ivybridge, bonnell,
nehalem and silvermont.

>BTW, I wonder if we add a bunch of new names to the table it isn't a right
>time to also introduce macros for some common PTA_* flag combinations,

IMO full list of PTA_* helps quickly identify what is supported.

2013-12-20  Tocar Ilya  <ilya.tocar@intel.com> 

	* config/i386/i386.c (ix86_option_override_internal): Add
	haswell, ivybridge, sandybridge, nehalem, bonnell, silvermont.
	* doc/invoke.texi: Document them.
---
 gcc/config/i386/i386.c | 27 +++++++++++++++++++++++++++
 gcc/doc/invoke.texi    | 32 ++++++++++++++++++++++++++++++++
 2 files changed, 59 insertions(+)

Comments

H.J. Lu Dec. 20, 2013, 4:55 p.m. UTC | #1 
On Fri, Dec 20, 2013 at 8:47 AM, Ilya Tocar <tocarip.intel@gmail.com> wrote:
>> > Perhaps we should add sandybridge, ivybridge and haswell aliases for
>> > corei7-avx, core-avx-i, core-avx2?  I mean, it is a nightmare to remember
>> > which one has the i7 in and which doesn't even for me.
>>
>> Yes please, I think this is a good idea.
>
> I've added aliases for haswell, sandybridge, ivybridge, bonnell,
> nehalem and silvermont.
>
>>BTW, I wonder if we add a bunch of new names to the table it isn't a right
>>time to also introduce macros for some common PTA_* flag combinations,
>
> IMO full list of PTA_* helps quickly identify what is supported.
>
> 2013-12-20  Tocar Ilya  <ilya.tocar@intel.com>
>
>         * config/i386/i386.c (ix86_option_override_internal): Add
>         haswell, ivybridge, sandybridge, nehalem, bonnell, silvermont.
>         * doc/invoke.texi: Document them.
> ---
>  gcc/config/i386/i386.c | 27 +++++++++++++++++++++++++++
>  gcc/doc/invoke.texi    | 32 ++++++++++++++++++++++++++++++++
>  2 files changed, 59 insertions(+)
>
> diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
> index 1710e8c..fcf2afe 100644
> --- a/gcc/config/i386/i386.c
> +++ b/gcc/config/i386/i386.c
> @@ -3111,9 +3111,17 @@ ix86_option_override_internal (bool main_args_p,
>        {"core2", PROCESSOR_CORE2, CPU_CORE2,
>         PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>         | PTA_SSSE3 | PTA_CX16 | PTA_FXSR},
> +      {"nehalem", PROCESSOR_COREI7, CPU_COREI7,
> +       PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3
> +       | PTA_SSE4_1 | PTA_SSE4_2 | PTA_CX16 | PTA_POPCNT | PTA_FXSR},
>        {"corei7", PROCESSOR_COREI7, CPU_COREI7,
>         PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3
>         | PTA_SSE4_1 | PTA_SSE4_2 | PTA_CX16 | PTA_POPCNT | PTA_FXSR},
> +      {"sandybridge", PROCESSOR_COREI7_AVX, CPU_COREI7,
> +       PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
> +       | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX
> +       | PTA_CX16 | PTA_POPCNT | PTA_AES | PTA_PCLMUL
> +       | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
>        {"corei7-avx", PROCESSOR_COREI7_AVX, CPU_COREI7,
>         PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>         | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX
> @@ -3124,6 +3132,11 @@ ix86_option_override_internal (bool main_args_p,
>         | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX
>         | PTA_CX16 | PTA_POPCNT | PTA_AES | PTA_PCLMUL | PTA_FSGSBASE
>         | PTA_RDRND | PTA_F16C | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
> +      {"ivybridge", PROCESSOR_COREI7_AVX, CPU_COREI7,
> +       PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
> +       | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX
> +       | PTA_CX16 | PTA_POPCNT | PTA_AES | PTA_PCLMUL | PTA_FSGSBASE
> +       | PTA_RDRND | PTA_F16C | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
>        {"core-avx2", PROCESSOR_HASWELL, CPU_COREI7,
>         PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>         | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX | PTA_AVX2
> @@ -3131,6 +3144,13 @@ ix86_option_override_internal (bool main_args_p,
>         | PTA_RDRND | PTA_F16C | PTA_BMI | PTA_BMI2 | PTA_LZCNT
>         | PTA_FMA | PTA_MOVBE | PTA_RTM | PTA_HLE | PTA_FXSR | PTA_XSAVE
>         | PTA_XSAVEOPT},
> +      {"haswell", PROCESSOR_HASWELL, CPU_COREI7,
> +       PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
> +       | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX | PTA_AVX2
> +       | PTA_CX16 | PTA_POPCNT | PTA_AES | PTA_PCLMUL | PTA_FSGSBASE
> +       | PTA_RDRND | PTA_F16C | PTA_BMI | PTA_BMI2 | PTA_LZCNT
> +       | PTA_FMA | PTA_MOVBE | PTA_RTM | PTA_HLE | PTA_FXSR | PTA_XSAVE
> +       | PTA_XSAVEOPT},
>        {"broadwell", PROCESSOR_HASWELL, CPU_COREI7,
>         PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>         | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX | PTA_AVX2
> @@ -3138,9 +3158,16 @@ ix86_option_override_internal (bool main_args_p,
>         | PTA_RDRND | PTA_F16C | PTA_BMI | PTA_BMI2 | PTA_LZCNT
>         | PTA_FMA | PTA_MOVBE | PTA_RTM | PTA_HLE | PTA_FXSR | PTA_XSAVE
>         | PTA_XSAVEOPT | PTA_ADX | PTA_PRFCHW | PTA_RDSEED},
> +      {"bonnell", PROCESSOR_ATOM, CPU_ATOM,
> +       PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
> +       | PTA_SSSE3 | PTA_CX16 | PTA_MOVBE | PTA_FXSR},
>        {"atom", PROCESSOR_ATOM, CPU_ATOM,
>         PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>         | PTA_SSSE3 | PTA_CX16 | PTA_MOVBE | PTA_FXSR},
> +      {"silvermont", PROCESSOR_SLM, CPU_SLM,
> +       PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3
> +       | PTA_SSE4_1 | PTA_SSE4_2 | PTA_CX16 | PTA_POPCNT | PTA_AES
> +       | PTA_PCLMUL | PTA_RDRND | PTA_MOVBE | PTA_FXSR},
>        {"slm", PROCESSOR_SLM, CPU_SLM,
>         PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3
>         | PTA_SSE4_1 | PTA_SSE4_2 | PTA_CX16 | PTA_POPCNT | PTA_AES
> diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
> index dcc1893..365ddbf 100644
> --- a/gcc/doc/invoke.texi
> +++ b/gcc/doc/invoke.texi
> @@ -14645,19 +14645,41 @@ SSE2 and SSE3 instruction set support.
>  Intel Core 2 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3 and SSSE3
>  instruction set support.
>
> +@item nehalem
> +Same as corei7.
> +Intel Core i7 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
> +SSE4.1, SSE4.2 and POPCNT instruction set support.
> +
>  @item corei7
>  Intel Core i7 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
>  SSE4.1, SSE4.2 and POPCNT instruction set support.
>
> +@item sandybridge
> +Same as corei7-avx.
> +Intel Core i7 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
> +SSE4.1, SSE4.2, POPCNT, AVX, AES and PCLMUL instruction set support.
> +
>  @item corei7-avx
>  Intel Core i7 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
>  SSE4.1, SSE4.2, POPCNT, AVX, AES and PCLMUL instruction set support.
>
> +@item ivybridge
> +Same as core-avx-i.
> +Intel Core CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
> +SSE4.1, SSE4.2, POPCNT, AVX, AES, PCLMUL, FSGSBASE, RDRND and F16C
> +instruction set support.
> +
>  @item core-avx-i
>  Intel Core CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
>  SSE4.1, SSE4.2, POPCNT, AVX, AES, PCLMUL, FSGSBASE, RDRND and F16C
>  instruction set support.
>
> +@item haswell
> +Same as core-avx2.
> +Intel Core CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
> +SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
> +BMI, BMI2 and F16C instruction set support.
> +
>  @item core-avx2
>  Intel Core CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
>  SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
> @@ -14672,6 +14694,16 @@ BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW instruction set support.
>  Intel Atom CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3 and SSSE3
>  instruction set support.
>
> +@item bonnell
> +Same as atom.
> +Intel Atom CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3 and SSSE3
> +instruction set support.
> +
> +@item silvermont
> +Same as slm.
> +Intel Silvermont CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
> +SSE4.1, SSE4.2, POPCNT, AES, PCLMUL and RDRND instruction set support.
> +
>  @item slm
>  Intel Silvermont CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
>  SSE4.1, SSE4.2, POPCNT, AES, PCLMUL and RDRND instruction set support.

Old names, like corei7, core-avx-i, atom, .. don't have precise
description for the processor.  I think gcc driver should keep
accepting them.  But they should be marked as undocumented
or deprecated.  They should be removed from documentation.
H.J. Lu Dec. 20, 2013, 10:54 p.m. UTC | #2 
On Fri, Dec 20, 2013 at 8:55 AM, H.J. Lu <hjl.tools@gmail.com> wrote:
> On Fri, Dec 20, 2013 at 8:47 AM, Ilya Tocar <tocarip.intel@gmail.com> wrote:
>>> > Perhaps we should add sandybridge, ivybridge and haswell aliases for
>>> > corei7-avx, core-avx-i, core-avx2?  I mean, it is a nightmare to remember
>>> > which one has the i7 in and which doesn't even for me.
>>>
>>> Yes please, I think this is a good idea.
>>
>> I've added aliases for haswell, sandybridge, ivybridge, bonnell,
>> nehalem and silvermont.
>>
>>>BTW, I wonder if we add a bunch of new names to the table it isn't a right
>>>time to also introduce macros for some common PTA_* flag combinations,
>>
>> IMO full list of PTA_* helps quickly identify what is supported.
>>
>> 2013-12-20  Tocar Ilya  <ilya.tocar@intel.com>
>>
>>         * config/i386/i386.c (ix86_option_override_internal): Add
>>         haswell, ivybridge, sandybridge, nehalem, bonnell, silvermont.
>>         * doc/invoke.texi: Document them.
>> ---
>>  gcc/config/i386/i386.c | 27 +++++++++++++++++++++++++++
>>  gcc/doc/invoke.texi    | 32 ++++++++++++++++++++++++++++++++
>>  2 files changed, 59 insertions(+)
>>
>> diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
>> index 1710e8c..fcf2afe 100644
>> --- a/gcc/config/i386/i386.c
>> +++ b/gcc/config/i386/i386.c
>> @@ -3111,9 +3111,17 @@ ix86_option_override_internal (bool main_args_p,
>>        {"core2", PROCESSOR_CORE2, CPU_CORE2,
>>         PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>         | PTA_SSSE3 | PTA_CX16 | PTA_FXSR},
>> +      {"nehalem", PROCESSOR_COREI7, CPU_COREI7,
>> +       PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3
>> +       | PTA_SSE4_1 | PTA_SSE4_2 | PTA_CX16 | PTA_POPCNT | PTA_FXSR},
>>        {"corei7", PROCESSOR_COREI7, CPU_COREI7,
>>         PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3
>>         | PTA_SSE4_1 | PTA_SSE4_2 | PTA_CX16 | PTA_POPCNT | PTA_FXSR},
>> +      {"sandybridge", PROCESSOR_COREI7_AVX, CPU_COREI7,
>> +       PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>> +       | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX
>> +       | PTA_CX16 | PTA_POPCNT | PTA_AES | PTA_PCLMUL
>> +       | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
>>        {"corei7-avx", PROCESSOR_COREI7_AVX, CPU_COREI7,
>>         PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>         | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX
>> @@ -3124,6 +3132,11 @@ ix86_option_override_internal (bool main_args_p,
>>         | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX
>>         | PTA_CX16 | PTA_POPCNT | PTA_AES | PTA_PCLMUL | PTA_FSGSBASE
>>         | PTA_RDRND | PTA_F16C | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
>> +      {"ivybridge", PROCESSOR_COREI7_AVX, CPU_COREI7,
>> +       PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>> +       | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX
>> +       | PTA_CX16 | PTA_POPCNT | PTA_AES | PTA_PCLMUL | PTA_FSGSBASE
>> +       | PTA_RDRND | PTA_F16C | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
>>        {"core-avx2", PROCESSOR_HASWELL, CPU_COREI7,
>>         PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>         | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX | PTA_AVX2
>> @@ -3131,6 +3144,13 @@ ix86_option_override_internal (bool main_args_p,
>>         | PTA_RDRND | PTA_F16C | PTA_BMI | PTA_BMI2 | PTA_LZCNT
>>         | PTA_FMA | PTA_MOVBE | PTA_RTM | PTA_HLE | PTA_FXSR | PTA_XSAVE
>>         | PTA_XSAVEOPT},
>> +      {"haswell", PROCESSOR_HASWELL, CPU_COREI7,
>> +       PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>> +       | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX | PTA_AVX2
>> +       | PTA_CX16 | PTA_POPCNT | PTA_AES | PTA_PCLMUL | PTA_FSGSBASE
>> +       | PTA_RDRND | PTA_F16C | PTA_BMI | PTA_BMI2 | PTA_LZCNT
>> +       | PTA_FMA | PTA_MOVBE | PTA_RTM | PTA_HLE | PTA_FXSR | PTA_XSAVE
>> +       | PTA_XSAVEOPT},
>>        {"broadwell", PROCESSOR_HASWELL, CPU_COREI7,
>>         PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>         | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX | PTA_AVX2
>> @@ -3138,9 +3158,16 @@ ix86_option_override_internal (bool main_args_p,
>>         | PTA_RDRND | PTA_F16C | PTA_BMI | PTA_BMI2 | PTA_LZCNT
>>         | PTA_FMA | PTA_MOVBE | PTA_RTM | PTA_HLE | PTA_FXSR | PTA_XSAVE
>>         | PTA_XSAVEOPT | PTA_ADX | PTA_PRFCHW | PTA_RDSEED},
>> +      {"bonnell", PROCESSOR_ATOM, CPU_ATOM,
>> +       PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>> +       | PTA_SSSE3 | PTA_CX16 | PTA_MOVBE | PTA_FXSR},
>>        {"atom", PROCESSOR_ATOM, CPU_ATOM,
>>         PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
>>         | PTA_SSSE3 | PTA_CX16 | PTA_MOVBE | PTA_FXSR},
>> +      {"silvermont", PROCESSOR_SLM, CPU_SLM,
>> +       PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3
>> +       | PTA_SSE4_1 | PTA_SSE4_2 | PTA_CX16 | PTA_POPCNT | PTA_AES
>> +       | PTA_PCLMUL | PTA_RDRND | PTA_MOVBE | PTA_FXSR},
>>        {"slm", PROCESSOR_SLM, CPU_SLM,
>>         PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3
>>         | PTA_SSE4_1 | PTA_SSE4_2 | PTA_CX16 | PTA_POPCNT | PTA_AES
>> diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
>> index dcc1893..365ddbf 100644
>> --- a/gcc/doc/invoke.texi
>> +++ b/gcc/doc/invoke.texi
>> @@ -14645,19 +14645,41 @@ SSE2 and SSE3 instruction set support.
>>  Intel Core 2 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3 and SSSE3
>>  instruction set support.
>>
>> +@item nehalem
>> +Same as corei7.
>> +Intel Core i7 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
>> +SSE4.1, SSE4.2 and POPCNT instruction set support.
>> +
>>  @item corei7
>>  Intel Core i7 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
>>  SSE4.1, SSE4.2 and POPCNT instruction set support.
>>
>> +@item sandybridge
>> +Same as corei7-avx.
>> +Intel Core i7 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
>> +SSE4.1, SSE4.2, POPCNT, AVX, AES and PCLMUL instruction set support.
>> +
>>  @item corei7-avx
>>  Intel Core i7 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
>>  SSE4.1, SSE4.2, POPCNT, AVX, AES and PCLMUL instruction set support.
>>
>> +@item ivybridge
>> +Same as core-avx-i.
>> +Intel Core CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
>> +SSE4.1, SSE4.2, POPCNT, AVX, AES, PCLMUL, FSGSBASE, RDRND and F16C
>> +instruction set support.
>> +
>>  @item core-avx-i
>>  Intel Core CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
>>  SSE4.1, SSE4.2, POPCNT, AVX, AES, PCLMUL, FSGSBASE, RDRND and F16C
>>  instruction set support.
>>
>> +@item haswell
>> +Same as core-avx2.
>> +Intel Core CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
>> +SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
>> +BMI, BMI2 and F16C instruction set support.
>> +
>>  @item core-avx2
>>  Intel Core CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
>>  SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
>> @@ -14672,6 +14694,16 @@ BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW instruction set support.
>>  Intel Atom CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3 and SSSE3
>>  instruction set support.
>>
>> +@item bonnell
>> +Same as atom.
>> +Intel Atom CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3 and SSSE3
>> +instruction set support.
>> +
>> +@item silvermont
>> +Same as slm.
>> +Intel Silvermont CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
>> +SSE4.1, SSE4.2, POPCNT, AES, PCLMUL and RDRND instruction set support.
>> +
>>  @item slm
>>  Intel Silvermont CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
>>  SSE4.1, SSE4.2, POPCNT, AES, PCLMUL and RDRND instruction set support.
>
> Old names, like corei7, core-avx-i, atom, .. don't have precise
> description for the processor.  I think gcc driver should keep
> accepting them.  But they should be marked as undocumented
> or deprecated.  They should be removed from documentation.
>
>

I didn't see westmere.
Uros Bizjak Dec. 22, 2013, 11:11 a.m. UTC | #3 
On Fri, Dec 20, 2013 at 5:47 PM, Ilya Tocar <tocarip.intel@gmail.com> wrote:
>> > Perhaps we should add sandybridge, ivybridge and haswell aliases for
>> > corei7-avx, core-avx-i, core-avx2?  I mean, it is a nightmare to remember
>> > which one has the i7 in and which doesn't even for me.
>>
>> Yes please, I think this is a good idea.
>
> I've added aliases for haswell, sandybridge, ivybridge, bonnell,
> nehalem and silvermont.
>
>>BTW, I wonder if we add a bunch of new names to the table it isn't a right
>>time to also introduce macros for some common PTA_* flag combinations,
>
> IMO full list of PTA_* helps quickly identify what is supported.
>
> 2013-12-20  Tocar Ilya  <ilya.tocar@intel.com>
>
>         * config/i386/i386.c (ix86_option_override_internal): Add
>         haswell, ivybridge, sandybridge, nehalem, bonnell, silvermont.
>         * doc/invoke.texi: Document them.

> diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
> index dcc1893..365ddbf 100644
> --- a/gcc/doc/invoke.texi
> +++ b/gcc/doc/invoke.texi
> @@ -14645,19 +14645,41 @@ SSE2 and SSE3 instruction set support.
>  Intel Core 2 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3 and SSSE3
>  instruction set support.
>
> +@item nehalem
> +Same as corei7.
> +Intel Core i7 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
> +SSE4.1, SSE4.2 and POPCNT instruction set support.
> +
>  @item corei7
>  Intel Core i7 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
>  SSE4.1, SSE4.2 and POPCNT instruction set support.

If these are the same, will it work to just add new @item under
existing one, like:

 @item corei7
+@item nehalem
 Intel Core i7 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
 SSE4.1, SSE4.2 and POPCNT instruction set support.

Uros.
Uros Bizjak Dec. 22, 2013, 11:19 a.m. UTC | #4 
On Fri, Dec 20, 2013 at 5:55 PM, H.J. Lu <hjl.tools@gmail.com> wrote:
> On Fri, Dec 20, 2013 at 8:47 AM, Ilya Tocar <tocarip.intel@gmail.com> wrote:
>>> > Perhaps we should add sandybridge, ivybridge and haswell aliases for
>>> > corei7-avx, core-avx-i, core-avx2?  I mean, it is a nightmare to remember
>>> > which one has the i7 in and which doesn't even for me.
>>>
>>> Yes please, I think this is a good idea.
>>
>> I've added aliases for haswell, sandybridge, ivybridge, bonnell,
>> nehalem and silvermont.
>>
> Old names, like corei7, core-avx-i, atom, .. don't have precise
> description for the processor.  I think gcc driver should keep
> accepting them.  But they should be marked as undocumented
> or deprecated.  They should be removed from documentation.

How about we leave these as -march=... to refer to the architecture,
and reintroduce -mcpu= to refer to the exact cpu? Internally, the
-mcpu would use some architecture specific base PTA_ attributes (as
Jakub suggested) and would add some fine-tuning PTA_ attributes, based
on -mcpu selection. This way, -march stays as is, and can still be
used for some generally distributed binaries.

Uros.
Jakub Jelinek Dec. 22, 2013, 12:55 p.m. UTC | #5 
On Sun, Dec 22, 2013 at 12:19:56PM +0100, Uros Bizjak wrote:
> On Fri, Dec 20, 2013 at 5:55 PM, H.J. Lu <hjl.tools@gmail.com> wrote:
> > On Fri, Dec 20, 2013 at 8:47 AM, Ilya Tocar <tocarip.intel@gmail.com> wrote:
> >>> > Perhaps we should add sandybridge, ivybridge and haswell aliases for
> >>> > corei7-avx, core-avx-i, core-avx2?  I mean, it is a nightmare to remember
> >>> > which one has the i7 in and which doesn't even for me.
> >>>
> >>> Yes please, I think this is a good idea.
> >>
> >> I've added aliases for haswell, sandybridge, ivybridge, bonnell,
> >> nehalem and silvermont.
> >>
> > Old names, like corei7, core-avx-i, atom, .. don't have precise
> > description for the processor.  I think gcc driver should keep
> > accepting them.  But they should be marked as undocumented
> > or deprecated.  They should be removed from documentation.
> 
> How about we leave these as -march=... to refer to the architecture,
> and reintroduce -mcpu= to refer to the exact cpu? Internally, the
> -mcpu would use some architecture specific base PTA_ attributes (as
> Jakub suggested) and would add some fine-tuning PTA_ attributes, based
> on -mcpu selection. This way, -march stays as is, and can still be
> used for some generally distributed binaries.

-mcpu is problematic, because it means various things among different
targets, and even on i?86/x86_64 it used to mean something already in the
past.  Sometimes -mcpu= is what -march= is now on i?86/x86_64, sometimes
what -mtune= is.  I'd say we don't need to deprecate anything, just add new
aliases for the sometimes harder to remember names.  But everything just
IMHO.

	Jakub
diff mbox

Patch

diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 1710e8c..fcf2afe 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -3111,9 +3111,17 @@  ix86_option_override_internal (bool main_args_p,
       {"core2", PROCESSOR_CORE2, CPU_CORE2,
 	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
 	| PTA_SSSE3 | PTA_CX16 | PTA_FXSR},
+      {"nehalem", PROCESSOR_COREI7, CPU_COREI7,
+	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3
+	| PTA_SSE4_1 | PTA_SSE4_2 | PTA_CX16 | PTA_POPCNT | PTA_FXSR},
       {"corei7", PROCESSOR_COREI7, CPU_COREI7,
 	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3
 	| PTA_SSE4_1 | PTA_SSE4_2 | PTA_CX16 | PTA_POPCNT | PTA_FXSR},
+      {"sandybridge", PROCESSOR_COREI7_AVX, CPU_COREI7,
+	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+	| PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX
+	| PTA_CX16 | PTA_POPCNT | PTA_AES | PTA_PCLMUL
+	| PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
       {"corei7-avx", PROCESSOR_COREI7_AVX, CPU_COREI7,
 	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
 	| PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX
@@ -3124,6 +3132,11 @@  ix86_option_override_internal (bool main_args_p,
 	| PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX
 	| PTA_CX16 | PTA_POPCNT | PTA_AES | PTA_PCLMUL | PTA_FSGSBASE
 	| PTA_RDRND | PTA_F16C | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
+      {"ivybridge", PROCESSOR_COREI7_AVX, CPU_COREI7,
+	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+	| PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX
+	| PTA_CX16 | PTA_POPCNT | PTA_AES | PTA_PCLMUL | PTA_FSGSBASE
+	| PTA_RDRND | PTA_F16C | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
       {"core-avx2", PROCESSOR_HASWELL, CPU_COREI7,
 	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
 	| PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX | PTA_AVX2
@@ -3131,6 +3144,13 @@  ix86_option_override_internal (bool main_args_p,
 	| PTA_RDRND | PTA_F16C | PTA_BMI | PTA_BMI2 | PTA_LZCNT
 	| PTA_FMA | PTA_MOVBE | PTA_RTM | PTA_HLE | PTA_FXSR | PTA_XSAVE
 	| PTA_XSAVEOPT},
+      {"haswell", PROCESSOR_HASWELL, CPU_COREI7,
+	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+	| PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX | PTA_AVX2
+	| PTA_CX16 | PTA_POPCNT | PTA_AES | PTA_PCLMUL | PTA_FSGSBASE
+	| PTA_RDRND | PTA_F16C | PTA_BMI | PTA_BMI2 | PTA_LZCNT
+	| PTA_FMA | PTA_MOVBE | PTA_RTM | PTA_HLE | PTA_FXSR | PTA_XSAVE
+	| PTA_XSAVEOPT},
       {"broadwell", PROCESSOR_HASWELL, CPU_COREI7,
 	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
 	| PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AVX | PTA_AVX2
@@ -3138,9 +3158,16 @@  ix86_option_override_internal (bool main_args_p,
 	| PTA_RDRND | PTA_F16C | PTA_BMI | PTA_BMI2 | PTA_LZCNT
 	| PTA_FMA | PTA_MOVBE | PTA_RTM | PTA_HLE | PTA_FXSR | PTA_XSAVE
 	| PTA_XSAVEOPT | PTA_ADX | PTA_PRFCHW | PTA_RDSEED},
+      {"bonnell", PROCESSOR_ATOM, CPU_ATOM,
+	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+	| PTA_SSSE3 | PTA_CX16 | PTA_MOVBE | PTA_FXSR},
       {"atom", PROCESSOR_ATOM, CPU_ATOM,
 	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
 	| PTA_SSSE3 | PTA_CX16 | PTA_MOVBE | PTA_FXSR},
+      {"silvermont", PROCESSOR_SLM, CPU_SLM,
+	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3
+	| PTA_SSE4_1 | PTA_SSE4_2 | PTA_CX16 | PTA_POPCNT | PTA_AES
+	| PTA_PCLMUL | PTA_RDRND | PTA_MOVBE | PTA_FXSR},
       {"slm", PROCESSOR_SLM, CPU_SLM,
 	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3
 	| PTA_SSE4_1 | PTA_SSE4_2 | PTA_CX16 | PTA_POPCNT | PTA_AES
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index dcc1893..365ddbf 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -14645,19 +14645,41 @@  SSE2 and SSE3 instruction set support.
 Intel Core 2 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3 and SSSE3
 instruction set support.
 
+@item nehalem
+Same as corei7.
+Intel Core i7 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
+SSE4.1, SSE4.2 and POPCNT instruction set support.
+
 @item corei7
 Intel Core i7 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
 SSE4.1, SSE4.2 and POPCNT instruction set support.
 
+@item sandybridge
+Same as corei7-avx.
+Intel Core i7 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
+SSE4.1, SSE4.2, POPCNT, AVX, AES and PCLMUL instruction set support.
+
 @item corei7-avx
 Intel Core i7 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
 SSE4.1, SSE4.2, POPCNT, AVX, AES and PCLMUL instruction set support.
 
+@item ivybridge
+Same as core-avx-i.
+Intel Core CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
+SSE4.1, SSE4.2, POPCNT, AVX, AES, PCLMUL, FSGSBASE, RDRND and F16C
+instruction set support.
+
 @item core-avx-i
 Intel Core CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
 SSE4.1, SSE4.2, POPCNT, AVX, AES, PCLMUL, FSGSBASE, RDRND and F16C
 instruction set support.
 
+@item haswell
+Same as core-avx2.
+Intel Core CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
+SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
+BMI, BMI2 and F16C instruction set support.
+
 @item core-avx2
 Intel Core CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
 SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
@@ -14672,6 +14694,16 @@  BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW instruction set support.
 Intel Atom CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3 and SSSE3
 instruction set support.
 
+@item bonnell
+Same as atom.
+Intel Atom CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3 and SSSE3
+instruction set support.
+
+@item silvermont
+Same as slm.
+Intel Silvermont CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
+SSE4.1, SSE4.2, POPCNT, AES, PCLMUL and RDRND instruction set support.
+
 @item slm
 Intel Silvermont CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
 SSE4.1, SSE4.2, POPCNT, AES, PCLMUL and RDRND instruction set support.