From patchwork Sat Nov 16 12:06:09 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joern Rennecke X-Patchwork-Id: 291771 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id D1E662C00A0 for ; Sat, 16 Nov 2013 23:06:28 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:to:subject:mime-version:content-type :content-transfer-encoding; q=dns; s=default; b=swo1RA2wyze3Ivl8 g2wiyzX8urBxgp37m32DJcnGeZQ2qNSdB5lbMJBC6TTUquLTXTIP+rPFnndqT2vg BgV8jxDEr8yo8a58d1Baio3hpb5ybayp5pg1rfyef2FS5Fb5C9OnovfQDmzCXvbd UpGUIoIBkNKnDOYgrIb9GnfRMXY= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:to:subject:mime-version:content-type :content-transfer-encoding; s=default; bh=ssZiGyEH6NhhkTJzS6Jldk eGz8w=; b=qk1P0Uj6bMyQh6yVe8v2fk2/y+Ny+2zK2xs3aOtHoMrlpMt98vSrsw tCvHqGZMYFlF1eDIC5wQrpaZEQq1VmLL9mQy5E0IF8oWeEZkgZKzsI40RBVVqDmX VGI6i5qeL8XLhtXdKUd39L3CNO6TVelm1TcyZGcNSRV9sbEo4iPoI= Received: (qmail 13602 invoked by alias); 16 Nov 2013 12:06:19 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 13593 invoked by uid 89); 16 Nov 2013 12:06:19 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=0.3 required=5.0 tests=AWL, BAYES_60, RDNS_NONE, URIBL_BLOCKED autolearn=no version=3.3.2 X-HELO: c62.cesmail.net Received: from Unknown (HELO c62.cesmail.net) (216.154.195.54) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA encrypted) ESMTPS; Sat, 16 Nov 2013 12:06:18 +0000 Received: from unknown (HELO delta2) ([192.168.1.50]) by c62.cesmail.net with ESMTP; 16 Nov 2013 07:06:10 -0500 Received: from cust213-dsl91-135-11.idnet.net (cust213-dsl91-135-11.idnet.net [91.135.11.213]) by webmail.spamcop.net (Horde MIME library) with HTTP; Sat, 16 Nov 2013 07:06:09 -0500 Message-ID: <20131116070609.nns1g2iycsogsgwk-nzlynne@webmail.spamcop.net> Date: Sat, 16 Nov 2013 07:06:09 -0500 From: Joern Rennecke To: gcc-patches@gcc.gnu.org Subject: Committed: arc.c: Make predication in delay slots explicit MIME-Version: 1.0 User-Agent: Internet Messaging Program (IMP) H3 (4.1.4) 2013-11-16 Joern Rennecke * config/arc/arc.c (arc_predicate_delay_insns): New function. (pass_data_arc_predicate_delay_insns): New pass_data instance. (pass_arc_predicate_delay_insns): New subclass of rtl_opt_class. (make_pass_arc_predicate_delay_insns): New function. (arc_init): Register pass_arc_predicate_delay_insns if flag_delayed_branch is active. Index: config/arc/arc.c =================================================================== --- config/arc/arc.c (revision 204900) +++ config/arc/arc.c (revision 204901) @@ -632,6 +632,44 @@ make_pass_arc_ifcvt (gcc::context *ctxt) return new pass_arc_ifcvt (ctxt); } +static unsigned arc_predicate_delay_insns (void); + +namespace { + +const pass_data pass_data_arc_predicate_delay_insns = +{ + RTL_PASS, + "arc_predicate_delay_insns", /* name */ + OPTGROUP_NONE, /* optinfo_flags */ + false, /* has_gate */ + true, /* has_execute */ + TV_IFCVT2, /* tv_id */ + 0, /* properties_required */ + 0, /* properties_provided */ + 0, /* properties_destroyed */ + 0, /* todo_flags_start */ + TODO_df_finish /* todo_flags_finish */ +}; + +class pass_arc_predicate_delay_insns : public rtl_opt_pass +{ +public: + pass_arc_predicate_delay_insns(gcc::context *ctxt) + : rtl_opt_pass(pass_data_arc_predicate_delay_insns, ctxt) + {} + + /* opt_pass methods: */ + unsigned int execute () { return arc_predicate_delay_insns (); } +}; + +} // anon namespace + +rtl_opt_pass * +make_pass_arc_predicate_delay_insns (gcc::context *ctxt) +{ + return new pass_arc_predicate_delay_insns (ctxt); +} + /* Called by OVERRIDE_OPTIONS to initialize various things. */ void @@ -752,6 +790,16 @@ arc_init (void) register_pass (&arc_ifcvt4_info); register_pass (&arc_ifcvt5_info); } + + if (flag_delayed_branch) + { + opt_pass *pass_arc_predicate_delay_insns + = make_pass_arc_predicate_delay_insns (g); + struct register_pass_info arc_predicate_delay_info + = { pass_arc_predicate_delay_insns, "dbr", 1, PASS_POS_INSERT_AFTER }; + + register_pass (&arc_predicate_delay_info); + } } /* Check ARC options, generate derived target attributes. */ @@ -8296,6 +8344,74 @@ arc_ifcvt (void) } return 0; } + +/* Find annulled delay insns and convert them to use the appropriate predicate. + This allows branch shortening to size up these insns properly. */ + +static unsigned +arc_predicate_delay_insns (void) +{ + for (rtx insn = get_insns (); insn; insn = NEXT_INSN (insn)) + { + rtx pat, jump, dlay, src, cond, *patp; + int reverse; + + if (!NONJUMP_INSN_P (insn) + || GET_CODE (pat = PATTERN (insn)) != SEQUENCE) + continue; + jump = XVECEXP (pat, 0, 0); + dlay = XVECEXP (pat, 0, 1); + if (!JUMP_P (jump) || !INSN_ANNULLED_BRANCH_P (jump)) + continue; + /* If the branch insn does the annulling, leave the delay insn alone. */ + if (!TARGET_AT_DBR_CONDEXEC && !INSN_FROM_TARGET_P (dlay)) + continue; + /* ??? Could also leave DLAY un-conditionalized if its target is dead + on the other path. */ + gcc_assert (GET_CODE (PATTERN (jump)) == SET); + gcc_assert (SET_DEST (PATTERN (jump)) == pc_rtx); + src = SET_SRC (PATTERN (jump)); + gcc_assert (GET_CODE (src) == IF_THEN_ELSE); + cond = XEXP (src, 0); + if (XEXP (src, 2) == pc_rtx) + reverse = 0; + else if (XEXP (src, 1) == pc_rtx) + reverse = 1; + else + gcc_unreachable (); + if (!INSN_FROM_TARGET_P (dlay) != reverse) + { + enum machine_mode ccm = GET_MODE (XEXP (cond, 0)); + enum rtx_code code = reverse_condition (GET_CODE (cond)); + if (code == UNKNOWN || ccm == CC_FP_GTmode || ccm == CC_FP_GEmode) + code = reverse_condition_maybe_unordered (GET_CODE (cond)); + + cond = gen_rtx_fmt_ee (code, GET_MODE (cond), + copy_rtx (XEXP (cond, 0)), + copy_rtx (XEXP (cond, 1))); + } + else + cond = copy_rtx (cond); + patp = &PATTERN (dlay); + pat = *patp; + /* dwarf2out.c:dwarf2out_frame_debug_expr doesn't know + what to do with COND_EXEC. */ + if (RTX_FRAME_RELATED_P (dlay)) + { + /* As this is the delay slot insn of an anulled branch, + dwarf2out.c:scan_trace understands the anulling semantics + without the COND_EXEC. */ + rtx note = alloc_reg_note (REG_FRAME_RELATED_EXPR, pat, + REG_NOTES (dlay)); + validate_change (dlay, ®_NOTES (dlay), note, 1); + } + pat = gen_rtx_COND_EXEC (VOIDmode, cond, pat); + validate_change (dlay, patp, pat, 1); + if (!apply_change_group ()) + gcc_unreachable (); + } + return 0; +} /* For ARC600: If a write to a core reg >=32 appears in a delay slot (other than of a forward brcc), it creates a hazard when there is a read