From patchwork Wed Nov 6 07:15:34 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kirill Yukhin X-Patchwork-Id: 288739 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 684C92C00A7 for ; Wed, 6 Nov 2013 18:17:10 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:references:mime-version :content-type:in-reply-to; q=dns; s=default; b=okWTAvhDzw6Je0PTi jkMvIMG8XTQZ+PSCflEGHg8+oh0h7gFA8fwrAhdpk2gvKZ8Mc7ZO1n3uY/GYdAsP i5iQJBUUdionYAo1Fs0MFP3JAV/D5dEfdPWZF0Dig4MfdRAUqX8wOhaPPLzAUXkc SCyrvOjoTiSl16U/amr0QfOzD0= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:references:mime-version :content-type:in-reply-to; s=default; bh=JH0E5XGmToTRm7wTePA5TBb iugY=; b=jC3DjyRrYBV7l8P0j4QX7f7vt7Lqc3cXXt7eMLHYKVJBZevvpw/rdiR +jLv8EVtCkynHdEjkkxh/uqrsRhH9yYx3l3GtPxwNYEIeSVA2XfExxXMaX76bV7t w/DApzbinyH4QXkMep9JLBZHtvotiIZYZ2QB+8walZOY+TUYcTCo= Received: (qmail 6004 invoked by alias); 6 Nov 2013 07:16:59 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 5991 invoked by uid 89); 6 Nov 2013 07:16:57 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.5 required=5.0 tests=AWL, BAYES_50, FREEMAIL_FROM, RDNS_NONE, SPF_PASS, URIBL_BLOCKED autolearn=no version=3.3.2 X-HELO: mail-pd0-f175.google.com Received: from Unknown (HELO mail-pd0-f175.google.com) (209.85.192.175) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Wed, 06 Nov 2013 07:16:28 +0000 Received: by mail-pd0-f175.google.com with SMTP id g10so9744838pdj.34 for ; Tue, 05 Nov 2013 23:16:20 -0800 (PST) X-Received: by 10.68.212.102 with SMTP id nj6mr1778956pbc.160.1383722180464; Tue, 05 Nov 2013 23:16:20 -0800 (PST) Received: from msticlxl57.ims.intel.com (fmdmzpr04-ext.fm.intel.com. [192.55.55.39]) by mx.google.com with ESMTPSA id ye1sm45678463pab.19.2013.11.05.23.16.17 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 05 Nov 2013 23:16:19 -0800 (PST) Date: Wed, 6 Nov 2013 10:15:34 +0300 From: Kirill Yukhin To: Uros Bizjak , Richard Henderson , Jakub Jelinek Cc: GCC Patches Subject: Re: [PATCH i386 4/8] [AVX512] [4/n] Add substed patterns: `sd' subst. Message-ID: <20131106071534.GA23881@msticlxl57.ims.intel.com> References: <20130814074404.GE52726@msticlxl57.ims.intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20130814074404.GE52726@msticlxl57.ims.intel.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-IsSubscribed: yes Hello, This small patch introduces `sd' subst. `sd' (Source-Destination) subst is almost the same, as the usual mask-subst, but it's only used for zero-masking. The reason is that some patterns already have an operand with constraint "0" and we can't add a new operand with the same constraint. So, we add only zero-masking here by subst and manually write a pattern for merge-masking where we use match_dup instead of an operand with constraint "0". Bootstrap pass. Is it ok for trunk? --- Thanks, K --- gcc/config/i386/sse.md | 180 ++++++++++++++++++++++++++++++++++++----------- gcc/config/i386/subst.md | 17 +++++ 2 files changed, 156 insertions(+), 41 deletions(-) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 298791d..6b41060 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -2752,17 +2752,17 @@ (match_operand:FMAMODE 3 "nonimmediate_operand")))] "") -(define_insn "fma_fmadd_" +(define_insn "fma_fmadd_" [(set (match_operand:FMAMODE 0 "register_operand" "=v,v,v,x,x") (fma:FMAMODE (match_operand:FMAMODE 1 "nonimmediate_operand" "%0, 0, v, x,x") (match_operand:FMAMODE 2 "nonimmediate_operand" "vm, v,vm, x,m") (match_operand:FMAMODE 3 "nonimmediate_operand" " v,vm, 0,xm,x")))] - "" + "" "@ - vfmadd132\t{%2, %3, %0|%0, %3, %2} - vfmadd213\t{%3, %2, %0|%0, %2, %3} - vfmadd231\t{%2, %1, %0|%0, %1, %2} + vfmadd132\t{%2, %3, %0|%0, %3, %2} + vfmadd213\t{%3, %2, %0|%0, %2, %3} + vfmadd231\t{%2, %1, %0|%0, %1, %2} vfmadd\t{%3, %2, %1, %0|%0, %1, %2, %3} vfmadd\t{%3, %2, %1, %0|%0, %1, %2, %3}" [(set_attr "isa" "fma_avx512f,fma_avx512f,fma_avx512f,fma4,fma4") @@ -2801,18 +2801,18 @@ (set_attr "type" "ssemuladd") (set_attr "mode" "")]) -(define_insn "*fma_fmsub_" +(define_insn "fma_fmsub_" [(set (match_operand:FMAMODE 0 "register_operand" "=v,v,v,x,x") (fma:FMAMODE (match_operand:FMAMODE 1 "nonimmediate_operand" "%0, 0, v, x,x") (match_operand:FMAMODE 2 "nonimmediate_operand" "vm, v,vm, x,m") (neg:FMAMODE - (match_operand:FMAMODE 3 "nonimmediate_operand" " v,vm, 0,xm,x"))))] - "" + (match_operand:FMAMODE 3 "nonimmediate_operand" "" v,vm, 0,xm,x"))))] + "" "@ - vfmsub132\t{%2, %3, %0|%0, %3, %2} - vfmsub213\t{%3, %2, %0|%0, %2, %3} - vfmsub231\t{%2, %1, %0|%0, %1, %2} + vfmsub132\t{%2, %3, %0|%0, %3, %2} + vfmsub213\t{%3, %2, %0|%0, %2, %3} + vfmsub231\t{%2, %1, %0|%0, %1, %2} vfmsub\t{%3, %2, %1, %0|%0, %1, %2, %3} vfmsub\t{%3, %2, %1, %0|%0, %1, %2, %3}" [(set_attr "isa" "fma_avx512f,fma_avx512f,fma_avx512f,fma4,fma4") @@ -2853,18 +2853,18 @@ (set_attr "type" "ssemuladd") (set_attr "mode" "")]) -(define_insn "*fma_fnmadd_" +(define_insn "fma_fnmadd_" [(set (match_operand:FMAMODE 0 "register_operand" "=v,v,v,x,x") (fma:FMAMODE (neg:FMAMODE (match_operand:FMAMODE 1 "nonimmediate_operand" "%0, 0, v, x,x")) (match_operand:FMAMODE 2 "nonimmediate_operand" "vm, v,vm, x,m") (match_operand:FMAMODE 3 "nonimmediate_operand" " v,vm, 0,xm,x")))] - "" + "" "@ - vfnmadd132\t{%2, %3, %0|%0, %3, %2} - vfnmadd213\t{%3, %2, %0|%0, %2, %3} - vfnmadd231\t{%2, %1, %0|%0, %1, %2} + vfnmadd132\t{%2, %3, %0|%0, %3, %2} + vfnmadd213\t{%3, %2, %0|%0, %2, %3} + vfnmadd231\t{%2, %1, %0|%0, %1, %2} vfnmadd\t{%3, %2, %1, %0|%0, %1, %2, %3} vfnmadd\t{%3, %2, %1, %0|%0, %1, %2, %3}" [(set_attr "isa" "fma_avx512f,fma_avx512f,fma_avx512f,fma4,fma4") @@ -2905,7 +2905,7 @@ (set_attr "type" "ssemuladd") (set_attr "mode" "")]) -(define_insn "*fma_fnmsub_" +(define_insn "fma_fnmsub_" [(set (match_operand:FMAMODE 0 "register_operand" "=v,v,v,x,x") (fma:FMAMODE (neg:FMAMODE @@ -2913,11 +2913,11 @@ (match_operand:FMAMODE 2 "nonimmediate_operand" "vm, v,vm, x,m") (neg:FMAMODE (match_operand:FMAMODE 3 "nonimmediate_operand" " v,vm, 0,xm,x"))))] - "" + "" "@ - vfnmsub132\t{%2, %3, %0|%0, %3, %2} - vfnmsub213\t{%3, %2, %0|%0, %2, %3} - vfnmsub231\t{%2, %1, %0|%0, %1, %2} + vfnmsub132\t{%2, %3, %0|%0, %3, %2} + vfnmsub213\t{%3, %2, %0|%0, %2, %3} + vfnmsub231\t{%2, %1, %0|%0, %1, %2} vfnmsub\t{%3, %2, %1, %0|%0, %1, %2, %3} vfnmsub\t{%3, %2, %1, %0|%0, %1, %2, %3}" [(set_attr "isa" "fma_avx512f,fma_avx512f,fma_avx512f,fma4,fma4") @@ -2980,18 +2980,32 @@ UNSPEC_FMADDSUB))] "TARGET_FMA || TARGET_FMA4 || TARGET_AVX512F") -(define_insn "fma_fmaddsub_" +(define_expand "avx512f_fmaddsub__maskz" + [(match_operand:VF_512 0 "register_operand") + (match_operand:VF_512 1 "nonimmediate_operand") + (match_operand:VF_512 2 "nonimmediate_operand") + (match_operand:VF_512 3 "nonimmediate_operand") + (match_operand: 4 "register_operand")] + "TARGET_AVX512F" +{ + emit_insn (gen_fma_fmaddsub__maskz_1 ( + operands[0], operands[1], operands[2], operands[3], + CONST0_RTX (mode), operands[4])); + DONE; +}) + +(define_insn "fma_fmaddsub_" [(set (match_operand:VF 0 "register_operand" "=v,v,v,x,x") (unspec:VF [(match_operand:VF 1 "nonimmediate_operand" "%0, 0, v, x,x") (match_operand:VF 2 "nonimmediate_operand" "vm, v,vm, x,m") (match_operand:VF 3 "nonimmediate_operand" " v,vm, 0,xm,x")] UNSPEC_FMADDSUB))] - "(TARGET_FMA || TARGET_FMA4 || TARGET_AVX512F)" + "(TARGET_FMA || TARGET_FMA4 || TARGET_AVX512F) && " "@ - vfmaddsub132\t{%2, %3, %0|%0, %3, %2} - vfmaddsub213\t{%3, %2, %0|%0, %2, %3} - vfmaddsub231\t{%2, %1, %0|%0, %1, %2} + vfmaddsub132\t{%2, %3, %0|%0, %3, %2} + vfmaddsub213\t{%3, %2, %0|%0, %2, %3} + vfmaddsub231\t{%2, %1, %0|%0, %1, %2} vfmaddsub\t{%3, %2, %1, %0|%0, %1, %2, %3} vfmaddsub\t{%3, %2, %1, %0|%0, %1, %2, %3}" [(set_attr "isa" "fma_avx512f,fma_avx512f,fma_avx512f,fma4,fma4") @@ -3032,7 +3046,7 @@ (set_attr "type" "ssemuladd") (set_attr "mode" "")]) -(define_insn "*fma_fmsubadd_" +(define_insn "fma_fmsubadd_" [(set (match_operand:VF 0 "register_operand" "=v,v,v,x,x") (unspec:VF [(match_operand:VF 1 "nonimmediate_operand" "%0, 0, v, x,x") @@ -3040,11 +3054,11 @@ (neg:VF (match_operand:VF 3 "nonimmediate_operand" " v,vm, 0,xm,x"))] UNSPEC_FMADDSUB))] - "(TARGET_FMA || TARGET_FMA4 || TARGET_AVX512F)" + "(TARGET_FMA || TARGET_FMA4 || TARGET_AVX512F) && " "@ - vfmsubadd132\t{%2, %3, %0|%0, %3, %2} - vfmsubadd213\t{%3, %2, %0|%0, %2, %3} - vfmsubadd231\t{%2, %1, %0|%0, %1, %2} + vfmsubadd132\t{%2, %3, %0|%0, %3, %2} + vfmsubadd213\t{%3, %2, %0|%0, %2, %3} + vfmsubadd231\t{%2, %1, %0|%0, %1, %2} vfmsubadd\t{%3, %2, %1, %0|%0, %1, %2, %3} vfmsubadd\t{%3, %2, %1, %0|%0, %1, %2, %3}" [(set_attr "isa" "fma_avx512f,fma_avx512f,fma_avx512f,fma4,fma4") @@ -6706,7 +6720,22 @@ [(set_attr "prefix" "evex") (set_attr "mode" "")]) -(define_insn "avx512f_vternlog" +(define_expand "avx512f_vternlog_maskz" + [(match_operand:VI48_512 0 "register_operand") + (match_operand:VI48_512 1 "register_operand") + (match_operand:VI48_512 2 "register_operand") + (match_operand:VI48_512 3 "nonimmediate_operand") + (match_operand:SI 4 "const_0_to_255_operand") + (match_operand: 5 "register_operand")] + "TARGET_AVX512F" +{ + emit_insn (gen_avx512f_vternlog_maskz_1 ( + operands[0], operands[1], operands[2], operands[3], + operands[4], CONST0_RTX (mode), operands[5])); + DONE; +}) + +(define_insn "avx512f_vternlog" [(set (match_operand:VI48_512 0 "register_operand" "=v") (unspec:VI48_512 [(match_operand:VI48_512 1 "register_operand" "0") @@ -6715,7 +6744,7 @@ (match_operand:SI 4 "const_0_to_255_operand")] UNSPEC_VTERNLOG))] "TARGET_AVX512F" - "vpternlog\t{%4, %3, %2, %0|%0, %2, %3, %4}" + "vpternlog\t{%4, %3, %2, %0|%0, %2, %3, %4}" [(set_attr "type" "sselog") (set_attr "prefix" "evex") (set_attr "mode" "")]) @@ -6802,7 +6831,23 @@ DONE; }) -(define_insn "avx512f_fixupimm" + +(define_expand "avx512f_fixupimm_maskz" + [(match_operand:VF_512 0 "register_operand") + (match_operand:VF_512 1 "register_operand") + (match_operand:VF_512 2 "register_operand") + (match_operand: 3 "nonimmediate_operand") + (match_operand:SI 4 "const_0_to_255_operand") + (match_operand: 5 "register_operand")] + "TARGET_AVX512F" +{ + emit_insn (gen_avx512f_fixupimm_maskz_1 ( + operands[0], operands[1], operands[2], operands[3], + operands[4], CONST0_RTX (mode), operands[5])); + DONE; +}) + +(define_insn "avx512f_fixupimm" [(set (match_operand:VF_512 0 "register_operand" "=v") (unspec:VF_512 [(match_operand:VF_512 1 "register_operand" "0") @@ -6811,7 +6856,7 @@ (match_operand:SI 4 "const_0_to_255_operand")] UNSPEC_FIXUPIMM))] "TARGET_AVX512F" - "vfixupimm\t{%4, %3, %2, %0|%0, %2, %3, %4}"; + "vfixupimm\t{%4, %3, %2, %0|%0, %2, %3, %4}"; [(set_attr "prefix" "evex") (set_attr "mode" "")]) @@ -6831,7 +6876,22 @@ [(set_attr "prefix" "evex") (set_attr "mode" "")]) -(define_insn "avx512f_sfixupimm" +(define_expand "avx512f_sfixupimm_maskz" + [(match_operand:VF_128 0 "register_operand") + (match_operand:VF_128 1 "register_operand") + (match_operand:VF_128 2 "register_operand") + (match_operand: 3 "nonimmediate_operand") + (match_operand:SI 4 "const_0_to_255_operand") + (match_operand: 5 "register_operand")] + "TARGET_AVX512F" +{ + emit_insn (gen_avx512f_sfixupimm_maskz_1 ( + operands[0], operands[1], operands[2], operands[3], + operands[4], CONST0_RTX (mode), operands[5])); + DONE; +}) + +(define_insn "avx512f_sfixupimm" [(set (match_operand:VF_128 0 "register_operand" "=v") (vec_merge:VF_128 (unspec:VF_128 @@ -6843,7 +6903,7 @@ (match_dup 1) (const_int 1)))] "TARGET_AVX512F" - "vfixupimm\t{%4, %3, %2, %0|%0, %2, %3, %4}"; + "vfixupimm\t{%4, %3, %2, %0|%0, %2, %3, %4}"; [(set_attr "prefix" "evex") (set_attr "mode" "")]) @@ -14138,7 +14198,21 @@ (set_attr "prefix" "") (set_attr "mode" "")]) -(define_insn "avx512f_vpermi2var3" +(define_expand "avx512f_vpermi2var3_maskz" + [(match_operand:VI48F_512 0 "register_operand" "=v") + (match_operand:VI48F_512 1 "register_operand" "v") + (match_operand: 2 "register_operand" "0") + (match_operand:VI48F_512 3 "nonimmediate_operand" "vm") + (match_operand: 4 "register_operand" "k")] + "TARGET_AVX512F" +{ + emit_insn (gen_avx512f_vpermi2var3_maskz_1 ( + operands[0], operands[1], operands[2], operands[3], + CONST0_RTX (mode), operands[4])); + DONE; +}) + +(define_insn "avx512f_vpermi2var3" [(set (match_operand:VI48F_512 0 "register_operand" "=v") (unspec:VI48F_512 [(match_operand:VI48F_512 1 "register_operand" "v") @@ -14146,7 +14220,7 @@ (match_operand:VI48F_512 3 "nonimmediate_operand" "vm")] UNSPEC_VPERMI2))] "TARGET_AVX512F" - "vpermi2\t{%3, %1, %0|%0, %1, %3}" + "vpermi2\t{%3, %1, %0|%0, %1, %3}" [(set_attr "type" "sselog") (set_attr "prefix" "evex") (set_attr "mode" "")]) @@ -14167,7 +14241,21 @@ (set_attr "prefix" "evex") (set_attr "mode" "")]) -(define_insn "avx512f_vpermt2var3" +(define_expand "avx512f_vpermt2var3_maskz" + [(match_operand:VI48F_512 0 "register_operand" "=v") + (match_operand: 1 "register_operand" "v") + (match_operand:VI48F_512 2 "register_operand" "0") + (match_operand:VI48F_512 3 "nonimmediate_operand" "vm") + (match_operand: 4 "register_operand" "k")] + "TARGET_AVX512F" +{ + emit_insn (gen_avx512f_vpermt2var3_maskz_1 ( + operands[0], operands[1], operands[2], operands[3], + CONST0_RTX (mode), operands[4])); + DONE; +}) + +(define_insn "avx512f_vpermt2var3" [(set (match_operand:VI48F_512 0 "register_operand" "=v") (unspec:VI48F_512 [(match_operand: 1 "register_operand" "v") @@ -14175,7 +14263,7 @@ (match_operand:VI48F_512 3 "nonimmediate_operand" "vm")] UNSPEC_VPERMT2))] "TARGET_AVX512F" - "vpermt2\t{%3, %1, %0|%0, %1, %3}" + "vpermt2\t{%3, %1, %0|%0, %1, %3}" [(set_attr "type" "sselog") (set_attr "prefix" "evex") (set_attr "mode" "")]) @@ -15167,6 +15255,16 @@ (set_attr "memory" "store") (set_attr "mode" "")]) +(define_expand "avx512f_expand_maskz" + [(set (match_operand:VI48F_512 0 "register_operand") + (unspec:VI48F_512 + [(match_operand:VI48F_512 1 "nonimmediate_operand") + (match_operand:VI48F_512 2 "vector_move_operand") + (match_operand: 3 "register_operand")] + UNSPEC_EXPAND))] + "TARGET_AVX512F" + "operands[2] = CONST0_RTX (mode);") + (define_insn "avx512f_expand_mask" [(set (match_operand:VI48F_512 0 "register_operand" "=v,v") (unspec:VI48F_512 diff --git a/gcc/config/i386/subst.md b/gcc/config/i386/subst.md index b537c5e..f81741f 100644 --- a/gcc/config/i386/subst.md +++ b/gcc/config/i386/subst.md @@ -93,3 +93,20 @@ (and:SUBST_S (match_dup 1) (match_operand:SUBST_S 3 "register_operand" "k")))]) + +(define_subst_attr "sd_maskz_name" "sd" "" "_maskz_1") +(define_subst_attr "sd_mask_op4" "sd" "" "%{%5%}%N4") +(define_subst_attr "sd_mask_op5" "sd" "" "%{%6%}%N5") +(define_subst_attr "sd_mask_codefor" "sd" "*" "") +(define_subst_attr "sd_mask_mode512bit_condition" "sd" "1" "(GET_MODE_SIZE (GET_MODE (operands[0])) == 64)") + +(define_subst "sd" + [(set (match_operand:SUBST_V 0) + (match_operand:SUBST_V 1))] + "" + [(set (match_dup 0) + (vec_merge:SUBST_V + (match_dup 1) + (match_operand:SUBST_V 2 "const0_operand" "C") + (match_operand: 3 "register_operand" "k"))) +])