From patchwork Wed Jul 10 11:08:14 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ulrich Weigand X-Patchwork-Id: 258012 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "localhost", Issuer "www.qmailtoaster.com" (not verified)) by ozlabs.org (Postfix) with ESMTPS id B34292C02C3 for ; Wed, 10 Jul 2013 21:08:35 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:subject:to:date:from:cc:mime-version:content-type :content-transfer-encoding; q=dns; s=default; b=nABTKbN+9PsuhWV/ Oc4LCe9QmRYW3PaMS0NuZKZDvIvxXY0vBY+8bQcvyYfcctNjg0bVPuZPTwOzLmsg XW5aD5EQ1yO9/Is2s6YRiyB+EkHA3VnxFyHIfwP83fIb0PEzBscXrkOJKrdCvhWR lA1ENO4lxJuPX8k2KAS2qDoOCmA= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:subject:to:date:from:cc:mime-version:content-type :content-transfer-encoding; s=default; bh=2kq2ILsnUWlP7rKzmnGsqe QJ9sc=; b=c/O+FB++Lpr+5QKWr41SymGb+WAMzsJNkkaovS/IUZtpClNmOazrIB TN/a2BToLxwanAU8C7qFDN0Az5gKwtkDvR1PYqFx5HAQocMDXgzIdLY4Rt7rk58E goTFBVOpqc+9J/Tr53OLVHXNTb+phqySWOdAiLrETWVkra1ESFzhY= Received: (qmail 16316 invoked by alias); 10 Jul 2013 11:08:28 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 16285 invoked by uid 89); 10 Jul 2013 11:08:23 -0000 X-Spam-SWARE-Status: No, score=-3.2 required=5.0 tests=AWL, BAYES_00, MSGID_FROM_MTA_HEADER, RCVD_IN_DNSWL_MED, RCVD_IN_HOSTKARMA_W, RP_MATCHES_RCVD, SPF_PASS autolearn=ham version=3.3.1 Received: from e06smtp11.uk.ibm.com (HELO e06smtp11.uk.ibm.com) (195.75.94.107) by sourceware.org (qpsmtpd/0.84/v0.84-167-ge50287c) with ESMTP; Wed, 10 Jul 2013 11:08:21 +0000 Received: from /spool/local by e06smtp11.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Wed, 10 Jul 2013 12:02:38 +0100 Received: from b06cxnps3075.portsmouth.uk.ibm.com (d06relay10.portsmouth.uk.ibm.com [9.149.109.195]) by d06dlp01.portsmouth.uk.ibm.com (Postfix) with ESMTP id 8F04C17D805A for ; Wed, 10 Jul 2013 12:09:51 +0100 (BST) Received: from d06av02.portsmouth.uk.ibm.com (d06av02.portsmouth.uk.ibm.com [9.149.37.228]) by b06cxnps3075.portsmouth.uk.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id r6AB85ei52756622 for ; Wed, 10 Jul 2013 11:08:06 GMT Received: from d06av02.portsmouth.uk.ibm.com (localhost [127.0.0.1]) by d06av02.portsmouth.uk.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id r6AB8G4L025761 for ; Wed, 10 Jul 2013 05:08:16 -0600 Received: from tuxmaker.boeblingen.de.ibm.com (tuxmaker.boeblingen.de.ibm.com [9.152.85.9]) by d06av02.portsmouth.uk.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with SMTP id r6AB8Fr4025718; Wed, 10 Jul 2013 05:08:15 -0600 Message-Id: <201307101108.r6AB8Fr4025718@d06av02.portsmouth.uk.ibm.com> Received: by tuxmaker.boeblingen.de.ibm.com (sSMTP sendmail emulation); Wed, 10 Jul 2013 13:08:14 +0200 Subject: [PATCH, rs6000] Keep TOC register live in TLS lo_sum patterns To: gcc-patches@gcc.gnu.org Date: Wed, 10 Jul 2013 13:08:14 +0200 (CEST) From: "Ulrich Weigand" Cc: dje.gcc@gmail.com MIME-Version: 1.0 X-TM-AS-MML: No X-Content-Scanned: Fidelis XPS MAILER x-cbid: 13071011-5024-0000-0000-0000068C7A03 Hello, the ppc64 linker performs an optimization to avoid multi-instruction TOC accesses in some cases: /* Multi-instruction sequences that access the TOC can be optimized, eg. addis ra,r2,0; addi rb,ra,x; to nop; addi rb,r2,x; */ For this optimization to be valid, the TOC register r2 has to be live at the point of the second instruction (addi rb,ra,x), even though this instruction -on its face- does not use r2. It is apparently the responsibility of the compiler to keep r2 live at this point on any such instruction (identified by using some low-part TOC relocation). There is code in rs6000.md that does this for "normal" accesses to variables in the TOC. However, code that accesses TLS-related information in the TOC (GOT_TLSGD and friends) does *not* ensure r2 is live. This usually doesn't matter because r2 tends to live across the whole function anyway. However, in the context of some out-of-tree patches I ran into a situation where this caused a bug. Since it would probably be theoretically possible to run into this issue even with mainline GCC (and in any case fixing the problem doesn't have any drawbacks), I'd suggest to fix this on mainline. This patch adds an extra operand to the UNSPEC operands of the TLS-related lo_sum patterns, used to enforce keeping the TOC register live. Tested with no regressions on powerpc64-linux. OK for mainline? Bye, Ulrich ChangeLog: * config/rs6000/rs6000.md (""*tls_gd_low"): Require GOT register as additional operand in UNSPEC. ("*tls_ld_low"): Likewise. ("*tls_got_dtprel_low"): Likewise. ("*tls_got_tprel_low"): Likewise. ("*tls_gd"): Update splitter. ("*tls_ld"): Likewise. ("tls_got_dtprel_"): Likewise. ("tls_got_tprel_"): Likewise. Index: gcc/config/rs6000/rs6000.md =================================================================== --- gcc/config/rs6000/rs6000.md (revision 200784) +++ gcc/config/rs6000/rs6000.md (working copy) @@ -10989,7 +10989,7 @@ (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGD))) (set (match_dup 0) (lo_sum:TLSmode (match_dup 3) - (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)))] + (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGD)))] " { operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode); @@ -11012,7 +11012,8 @@ (define_insn "*tls_gd_low" [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b") (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b") - (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")] + (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b") + (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")] UNSPEC_TLSGD)))] "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL" "addi %0,%1,%2@got@tlsgd@l" @@ -11124,7 +11125,7 @@ (unspec:TLSmode [(const_int 0) (match_dup 1)] UNSPEC_TLSLD))) (set (match_dup 0) (lo_sum:TLSmode (match_dup 2) - (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)))] + (unspec:TLSmode [(const_int 0) (match_dup 1)] UNSPEC_TLSLD)))] " { operands[2] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode); @@ -11147,7 +11148,9 @@ (define_insn "*tls_ld_low" [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b") (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b") - (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)))] + (unspec:TLSmode [(const_int 0) + (match_operand:TLSmode 2 "gpc_reg_operand" "b")] + UNSPEC_TLSLD)))] "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL" "addi %0,%1,%&@got@tlsld@l" [(set_attr "length" "4")]) @@ -11219,7 +11222,7 @@ (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTDTPREL))) (set (match_dup 0) (lo_sum:TLSmode (match_dup 3) - (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGOTDTPREL)))] + (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTDTPREL)))] " { operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode); @@ -11242,7 +11245,8 @@ (define_insn "*tls_got_dtprel_low" [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r") (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b") - (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")] + (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b") + (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")] UNSPEC_TLSGOTDTPREL)))] "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL" "l %0,%2@got@dtprel@l(%1)" @@ -11288,7 +11292,7 @@ (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTTPREL))) (set (match_dup 0) (lo_sum:TLSmode (match_dup 3) - (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGOTTPREL)))] + (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTTPREL)))] " { operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode); @@ -11311,7 +11315,8 @@ (define_insn "*tls_got_tprel_low" [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r") (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b") - (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")] + (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b") + (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")] UNSPEC_TLSGOTTPREL)))] "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL" "l %0,%2@got@tprel@l(%1)"