@@ -3332,22 +3332,8 @@ (define_insn "extendsidi2_1"
"!TARGET_64BIT"
"#")
-;; Extend to memory case when source register does die.
-(define_split
- [(set (match_operand:DI 0 "memory_operand")
- (sign_extend:DI (match_operand:SI 1 "register_operand")))
- (clobber (reg:CC FLAGS_REG))
- (clobber (match_operand:SI 2 "register_operand"))]
- "(reload_completed
- && dead_or_set_p (insn, operands[1])
- && !reg_mentioned_p (operands[1], operands[0]))"
- [(set (match_dup 3) (match_dup 1))
- (parallel [(set (match_dup 1) (ashiftrt:SI (match_dup 1) (const_int 31)))
- (clobber (reg:CC FLAGS_REG))])
- (set (match_dup 4) (match_dup 1))]
- "split_double_mode (DImode, &operands[0], 1, &operands[3], &operands[4]);")
-
-;; Extend to memory case when source register does not die.
+;; Split the memory case. If the source register doesn't die, it will stay
+;; this way, if it does die, following peephole2s take care of it.
(define_split
[(set (match_operand:DI 0 "memory_operand")
(sign_extend:DI (match_operand:SI 1 "register_operand")))
@@ -3376,6 +3362,48 @@ (define_split
DONE;
})
+;; Peepholes for the case where the source register does die, after
+;; being split with the above splitter.
+(define_peephole2
+ [(set (match_operand:SI 0 "memory_operand")
+ (match_operand:SI 1 "register_operand"))
+ (set (match_operand:SI 2 "register_operand") (match_dup 1))
+ (parallel [(set (match_dup 2)
+ (ashiftrt:SI (match_dup 2)
+ (match_operand:QI 3 "const_int_operand")))
+ (clobber (reg:CC FLAGS_REG))])
+ (set (match_operand:SI 4 "memory_operand") (match_dup 2))]
+ "INTVAL (operands[3]) == 31
+ && REGNO (operands[1]) != REGNO (operands[2])
+ && peep2_reg_dead_p (2, operands[1])
+ && peep2_reg_dead_p (4, operands[2])
+ && !reg_mentioned_p (operands[2], operands[4])"
+ [(set (match_dup 0) (match_dup 1))
+ (parallel [(set (match_dup 1) (ashiftrt:SI (match_dup 1) (const_int 31)))
+ (clobber (reg:CC FLAGS_REG))])
+ (set (match_dup 4) (match_dup 1))])
+
+(define_peephole2
+ [(set (match_operand:SI 0 "memory_operand")
+ (match_operand:SI 1 "register_operand"))
+ (parallel [(set (match_operand:SI 2 "register_operand")
+ (ashiftrt:SI (match_dup 1)
+ (match_operand:QI 3 "const_int_operand")))
+ (clobber (reg:CC FLAGS_REG))])
+ (set (match_operand:SI 4 "memory_operand") (match_dup 2))]
+ "INTVAL (operands[3]) == 31
+ /* cltd is shorter than sarl $31, %eax */
+ && !optimize_function_for_size_p (cfun)
+ && true_regnum (operands[1]) == AX_REG
+ && true_regnum (operands[2]) == DX_REG
+ && peep2_reg_dead_p (2, operands[1])
+ && peep2_reg_dead_p (3, operands[2])
+ && !reg_mentioned_p (operands[2], operands[4])"
+ [(set (match_dup 0) (match_dup 1))
+ (parallel [(set (match_dup 1) (ashiftrt:SI (match_dup 1) (const_int 31)))
+ (clobber (reg:CC FLAGS_REG))])
+ (set (match_dup 4) (match_dup 1))])
+
;; Extend to register case. Optimize case where source and destination
;; registers match and cases where we can use cltd.
(define_split
@@ -0,0 +1,21 @@
+/* PR rtl-optimization/57300 */
+/* { dg-do run } */
+/* { dg-options "-O3" } */
+/* { dg-additional-options "-msse2" { target sse2_runtime } } */
+
+extern void abort (void);
+int a, b, d[10];
+long long c;
+
+int
+main ()
+{
+ int e;
+ for (e = 0; e < 10; e++)
+ d[e] = 1;
+ if (d[0])
+ c = a = (b == 0 || 1 % b);
+ if (a != 1)
+ abort ();
+ return 0;
+}
@@ -0,0 +1,25 @@
+/* PR rtl-optimization/57281 */
+
+int a = 1, b, d, *e = &d;
+long long c, *g = &c;
+volatile long long f;
+
+int
+foo (int h)
+{
+ int j = *g = b;
+ return h == 0 ? j : 0;
+}
+
+int
+main ()
+{
+ int h = a;
+ for (; b != -20; b--)
+ {
+ (int) f;
+ *e = 0;
+ *e = foo (h);
+ }
+ return 0;
+}