From patchwork Mon May 13 16:43:58 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jakub Jelinek X-Patchwork-Id: 243459 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "localhost", Issuer "www.qmailtoaster.com" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 0CC332C009C for ; Tue, 14 May 2013 02:44:14 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:reply-to:references:mime-version :content-type:in-reply-to; q=dns; s=default; b=DpZbPy1nM0TgyY+ro bOp6nOeN/CkrJA/5bWFJ7PwQ7gceD1FiFzLYDAqpf+7QBg9OpixM+LZmaeT6Oh+3 LqLoSLhkB/0hk6sbyO/TjaQH4ASPRGj/GDSZyYrfW/GNcs6nlFzWUCtpG66km76J ZcpMMPdljXLDRWThilI09SwxG0= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:reply-to:references:mime-version :content-type:in-reply-to; s=default; bh=2send0uuGjGmyw6ogqZ34We Czek=; b=SZeHJmaNRqV3Q9LT97DA/InaEh7lmW0XoyOAwvn8VDZQLAtOj5RCIfj vkYBcLhoLCnjCapKjk9rmFqtCM45dgturJxHH2jCTdG1c0DSEyu6gZcOPzRrvKxl GV+hhP+8F6+PfTF1oXyEV2/B0lE5rUwT0y70S09ok6RmUfO32gSk= Received: (qmail 26712 invoked by alias); 13 May 2013 16:44:08 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 26703 invoked by uid 89); 13 May 2013 16:44:08 -0000 X-Spam-SWARE-Status: No, score=-6.7 required=5.0 tests=AWL, BAYES_00, RCVD_IN_HOSTKARMA_W, RCVD_IN_HOSTKARMA_WL, RP_MATCHES_RCVD, SPF_HELO_PASS, SPF_PASS autolearn=ham version=3.3.1 Received: from mx1.redhat.com (HELO mx1.redhat.com) (209.132.183.28) by sourceware.org (qpsmtpd/0.84/v0.84-167-ge50287c) with ESMTP; Mon, 13 May 2013 16:44:07 +0000 Received: from int-mx09.intmail.prod.int.phx2.redhat.com (int-mx09.intmail.prod.int.phx2.redhat.com [10.5.11.22]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id r4DGi5mF007681 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Mon, 13 May 2013 12:44:06 -0400 Received: from zalov.cz (vpn-60-18.rdu2.redhat.com [10.10.60.18]) by int-mx09.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id r4DGi48r002722 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 13 May 2013 12:44:05 -0400 Received: from zalov.cz (localhost [127.0.0.1]) by zalov.cz (8.14.5/8.14.5) with ESMTP id r4DGi2WI008443; Mon, 13 May 2013 18:44:03 +0200 Received: (from jakub@localhost) by zalov.cz (8.14.5/8.14.5/Submit) id r4DGi06k008442; Mon, 13 May 2013 18:44:00 +0200 Date: Mon, 13 May 2013 18:43:58 +0200 From: Jakub Jelinek To: Jan Hubicka , Richard Biener Cc: Uros Bizjak , gcc-patches@gcc.gnu.org Subject: [PATCH] Improve rotation by mode bitsize - 1 (take 2) Message-ID: <20130513164358.GB1377@tucnak.redhat.com> Reply-To: Jakub Jelinek References: <20130509184556.GI1377@tucnak.redhat.com> <20130510134849.GD23785@atrey.karlin.mff.cuni.cz> <20130510140926.GN1377@tucnak.redhat.com> <20130510171538.GB7824@kam.mff.cuni.cz> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20130510171538.GB7824@kam.mff.cuni.cz> User-Agent: Mutt/1.5.21 (2010-09-15) On Fri, May 10, 2013 at 07:15:38PM +0200, Jan Hubicka wrote: > It seems to me that it is not different from normalizing reg-10 into reg+(-10) > we do for years (and for good reason). It is still target preference when use > add and when sub to perform the arithmetic, but it makes sense to keep single > canonical form of the expression both in RTL and Gimple. > > For example we may want to be able to prove that > (rotate reg 31) == (rotatert reg 1) > is true or > (rotate reg 30) == (rotatert reg 2) > is also true or cross jump both variants into one instruction. Ok, this patch reverts my earlier patch and does the canonicalization, for now for RTL only. Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk? 2013-05-13 Jakub Jelinek * expmed.c (expand_shift_1): Canonicalize rotates by constant bitsize / 2 to bitsize - 1. * simplify-rt.x (simplify_binary_operation_1) : Likewise. Revert: 2013-05-10 Jakub Jelinek * config/i386/i386.md (rotateinv): New code attr. (*3_1, *si3_1_zext, *qi3_1_slp): Emit rorl %eax instead of roll $31, %eax, etc. Jakub --- gcc/expmed.c.jj 2013-05-13 13:03:31.000000000 +0200 +++ gcc/expmed.c 2013-05-13 15:22:39.456194286 +0200 @@ -2122,6 +2122,20 @@ expand_shift_1 (enum tree_code code, enu op1 = SUBREG_REG (op1); } + /* Canonicalize rotates by constant amount. If op1 is bitsize / 2, + prefer left rotation, if op1 is from bitsize / 2 + 1 to + bitsize - 1, use other direction of rotate with 1 .. bitsize / 2 - 1 + amount instead. */ + if (rotate + && CONST_INT_P (op1) + && IN_RANGE (INTVAL (op1), GET_MODE_BITSIZE (mode) / 2 + left, + GET_MODE_BITSIZE (mode) - 1)) + { + op1 = GEN_INT (GET_MODE_BITSIZE (mode) - INTVAL (op1)); + left = !left; + code = left ? LROTATE_EXPR : RROTATE_EXPR; + } + if (op1 == const0_rtx) return shifted; --- gcc/simplify-rtx.c.jj 2013-05-02 12:42:25.000000000 +0200 +++ gcc/simplify-rtx.c 2013-05-13 15:48:31.171182716 +0200 @@ -3250,6 +3250,18 @@ simplify_binary_operation_1 (enum rtx_co case ROTATERT: case ROTATE: + /* Canonicalize rotates by constant amount. If op1 is bitsize / 2, + prefer left rotation, if op1 is from bitsize / 2 + 1 to + bitsize - 1, use other direction of rotate with 1 .. bitsize / 2 - 1 + amount instead. */ + if (CONST_INT_P (trueop1) + && IN_RANGE (INTVAL (trueop1), + GET_MODE_BITSIZE (mode) / 2 + (code == ROTATE), + GET_MODE_BITSIZE (mode) - 1)) + return simplify_gen_binary (code == ROTATE ? ROTATERT : ROTATE, + mode, op0, GEN_INT (GET_MODE_BITSIZE (mode) + - INTVAL (trueop1))); + /* FALLTHRU */ case ASHIFTRT: if (trueop1 == CONST0_RTX (mode)) return op0; --- gcc/config/i386/i386.md.jj 2013-05-13 09:44:51.675494325 +0200 +++ gcc/config/i386/i386.md 2013-05-13 15:09:37.461637593 +0200 @@ -762,9 +762,6 @@ (define_code_attr rotate_insn [(rotate " ;; Base name for insn mnemonic. (define_code_attr rotate [(rotate "rol") (rotatert "ror")]) -;; Base name for insn mnemonic of rotation in the other direction. -(define_code_attr rotateinv [(rotate "ror") (rotatert "rol")]) - ;; Mapping of abs neg operators (define_code_iterator absneg [abs neg]) @@ -9755,15 +9752,11 @@ (define_insn "*3_1" return "#"; default: - if (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)) - { - if (operands[2] == const1_rtx) - return "{}\t%0"; - if (CONST_INT_P (operands[2]) - && INTVAL (operands[2]) == GET_MODE_BITSIZE (mode) - 1) - return "{}\t%0"; - } - return "{}\t{%2, %0|%0, %2}"; + if (operands[2] == const1_rtx + && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))) + return "{}\t%0"; + else + return "{}\t{%2, %0|%0, %2}"; } } [(set_attr "isa" "*,bmi2") @@ -9825,14 +9818,11 @@ (define_insn "*si3_1_zext" return "#"; default: - if (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)) - { - if (operands[2] == const1_rtx) - return "{l}\t%k0"; - if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 31) - return "{l}\t%k0"; - } - return "{l}\t{%2, %k0|%k0, %2}"; + if (operands[2] == const1_rtx + && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))) + return "{l}\t%k0"; + else + return "{l}\t{%2, %k0|%k0, %2}"; } } [(set_attr "isa" "*,bmi2") @@ -9879,15 +9869,11 @@ (define_insn "*3_1" (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (, mode, operands)" { - if (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)) - { - if (operands[2] == const1_rtx) - return "{}\t%0"; - if (CONST_INT_P (operands[2]) - && INTVAL (operands[2]) == GET_MODE_BITSIZE (mode) - 1) - return "{}\t%0"; - } - return "{}\t{%2, %0|%0, %2}"; + if (operands[2] == const1_rtx + && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))) + return "{}\t%0"; + else + return "{}\t{%2, %0|%0, %2}"; } [(set_attr "type" "rotate") (set (attr "length_immediate") @@ -9909,14 +9895,11 @@ (define_insn "*qi3_1_slp" || (operands[1] == const1_rtx && TARGET_SHIFT1))" { - if (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)) - { - if (operands[2] == const1_rtx) - return "{b}\t%0"; - if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 7) - return "{b}\t%0"; - } - return "{b}\t{%1, %0|%0, %1}"; + if (operands[1] == const1_rtx + && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))) + return "{b}\t%0"; + else + return "{b}\t{%1, %0|%0, %1}"; } [(set_attr "type" "rotate1") (set (attr "length_immediate")