From patchwork Wed Mar 27 06:43:40 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Walter Lee X-Patchwork-Id: 231596 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "localhost", Issuer "www.qmailtoaster.com" (not verified)) by ozlabs.org (Postfix) with ESMTPS id CEDDC2C009F for ; Wed, 27 Mar 2013 17:44:10 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :message-id:from:to:subject:reply-to:mime-version:content-type; q=dns; s=default; b=kFYzhGQZyhuheDFsf2N4mT9hRL5PTvrht/Xe2xu7A0O GjOyXwe3lDfS2ikZiw2JnhvX/ZfwKOfPapt6nUoRlMHGDdaVksCq8COgfyCzfq7Q foCu2JDRdFRRLTWl1dP3EvrGATAufcsvmU0cQZUYwvuP9D+pW7wi/QYd8JLxFnJ4 = DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :message-id:from:to:subject:reply-to:mime-version:content-type; s=default; bh=MgRqHMkfjwwP2HgmVJCpKnXyeNM=; b=ZaEQYUq/rJtkqdWjH 93HE9ZY7Ri2Mgv8e5B+rnFTX8m/Fd123NYT3SeV7u8UmiYdPyBYatDaXDVlMhBEM f24fNjCxKdCu5iWfyfi1OxBk9zM3Q9Q8QaFk+AFmuDTAw495c55UuaXtWxF1EcIA 6cojj7dbQJzHDL0UYRgNI/kJdM= Received: (qmail 16823 invoked by alias); 27 Mar 2013 06:43:59 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 16805 invoked by uid 89); 27 Mar 2013 06:43:46 -0000 X-Spam-SWARE-Status: No, score=-2.7 required=5.0 tests=AWL, BAYES_00, RP_MATCHES_RCVD, TW_MN autolearn=ham version=3.3.1 Received: from usmamail.tilera.com (HELO USMAMAIL.TILERA.COM) (12.216.194.151) by sourceware.org (qpsmtpd/0.84/v0.84-167-ge50287c) with ESMTP; Wed, 27 Mar 2013 06:43:43 +0000 Received: from farm-0001.internal.tilera.com (10.2.0.31) by USMAEXCH2.tad.internal.tilera.com (10.3.0.33) with Microsoft SMTP Server (TLS) id 14.0.722.0; Wed, 27 Mar 2013 02:43:41 -0400 Received: (from walt@localhost) by farm-0001.internal.tilera.com (8.14.4/8.12.11/Submit) id r2R6heP5007929; Wed, 27 Mar 2013 02:43:40 -0400 Date: Wed, 27 Mar 2013 02:43:40 -0400 Message-ID: <201303270643.r2R6heP5007929@farm-0001.internal.tilera.com> From: Walter Lee To: Subject: [committed] TILE-Gx: fixes for vector pattern using const 0 Reply-To: Walter Lee MIME-Version: 1.0 This patch replaces (const_int 0) in vector patterns with its const_vector representation. Backported to 4.7 and 4.8. * config/tilegx/tilegx.md (insn_mnz_): Replaced by ... (insn_mnz_v8qi): ... this ... (insn_mnz_v4hi): ... and this. Replace (const_int 0) with the vector equivalent. (insn_vmnz): Replaced by ... (insn_v1mnz): ... this ... (insn_v2mnz): ... and this. Replace (const_int 0) with the vector equivalent. (insn_mz_): Replaced by ... (insn_mz_v8qi): ... this ... (insn_mz_v4hi): ... and this. Replace (const_int 0) with the vector equivalent. (insn_vmz): Replaced by ... (insn_v1mz): ... this ... (insn_v2mz): ... and this. Replace (const_int 0) with the vector equivalent. Index: gcc/config/tilegx/tilegx.md =================================================================== --- gcc/config/tilegx/tilegx.md (revision 197134) +++ gcc/config/tilegx/tilegx.md (working copy) @@ -4597,57 +4597,147 @@ ;; insn_v1mz ;; insn_v2mnz ;; insn_v2mz -(define_insn "insn_mnz_" - [(set (match_operand:VEC48MODE 0 "register_operand" "=r") - (if_then_else:VEC48MODE - (ne:VEC48MODE - (match_operand:VEC48MODE 1 "reg_or_0_operand" "rO") - (const_int 0)) - (match_operand:VEC48MODE 2 "reg_or_0_operand" "rO") - (const_int 0)))] +(define_insn "insn_mnz_v8qi" + [(set (match_operand:V8QI 0 "register_operand" "=r") + (if_then_else:V8QI + (ne:V8QI + (match_operand:V8QI 1 "reg_or_0_operand" "rO") + (const_vector:V8QI [(const_int 0) (const_int 0) + (const_int 0) (const_int 0) + (const_int 0) (const_int 0) + (const_int 0) (const_int 0)])) + (match_operand:V8QI 2 "reg_or_0_operand" "rO") + (const_vector:V8QI [(const_int 0) (const_int 0) + (const_int 0) (const_int 0) + (const_int 0) (const_int 0) + (const_int 0) (const_int 0)])))] "" - "vmnz\t%0, %r1, %r2" + "v1mnz\t%0, %r1, %r2" [(set_attr "type" "X01")]) -(define_expand "insn_vmnz" +(define_expand "insn_v1mnz" [(set (match_operand:DI 0 "register_operand" "") - (if_then_else:VEC48MODE - (ne:VEC48MODE + (if_then_else:V8QI + (ne:V8QI (match_operand:DI 1 "reg_or_0_operand" "") - (const_int 0)) + (const_vector:V8QI [(const_int 0) (const_int 0) + (const_int 0) (const_int 0) + (const_int 0) (const_int 0) + (const_int 0) (const_int 0)]) + ) (match_operand:DI 2 "reg_or_0_operand" "") - (const_int 0)))] + (const_vector:V8QI [(const_int 0) (const_int 0) + (const_int 0) (const_int 0) + (const_int 0) (const_int 0) + (const_int 0) (const_int 0)])))] "" { - tilegx_expand_builtin_vector_binop (gen_insn_mnz_, mode, - operands[0], mode, operands[1], + tilegx_expand_builtin_vector_binop (gen_insn_mnz_v8qi, V8QImode, + operands[0], V8QImode, operands[1], operands[2], true); DONE; }) -(define_insn "insn_mz_" - [(set (match_operand:VEC48MODE 0 "register_operand" "=r") - (if_then_else:VEC48MODE - (ne:VEC48MODE - (match_operand:VEC48MODE 1 "reg_or_0_operand" "rO") - (const_int 0)) - (const_int 0) - (match_operand:VEC48MODE 2 "reg_or_0_operand" "rO")))] +(define_insn "insn_mz_v8qi" + [(set (match_operand:V8QI 0 "register_operand" "=r") + (if_then_else:V8QI + (ne:V8QI + (match_operand:V8QI 1 "reg_or_0_operand" "rO") + (const_vector:V8QI [(const_int 0) (const_int 0) + (const_int 0) (const_int 0) + (const_int 0) (const_int 0) + (const_int 0) (const_int 0)])) + (const_vector:V8QI [(const_int 0) (const_int 0) + (const_int 0) (const_int 0) + (const_int 0) (const_int 0) + (const_int 0) (const_int 0)]) + (match_operand:V8QI 2 "reg_or_0_operand" "rO")))] "" - "vmz\t%0, %r1, %r2" + "v1mz\t%0, %r1, %r2" [(set_attr "type" "X01")]) -(define_expand "insn_vmz" + +(define_expand "insn_v1mz" [(set (match_operand:DI 0 "register_operand" "") - (if_then_else:VEC48MODE - (ne:VEC48MODE + (if_then_else:V8QI + (ne:V8QI (match_operand:DI 1 "reg_or_0_operand" "") - (const_int 0)) - (const_int 0) + (const_vector:V8QI [(const_int 0) (const_int 0) + (const_int 0) (const_int 0) + (const_int 0) (const_int 0) + (const_int 0) (const_int 0)])) + (const_vector:V8QI [(const_int 0) (const_int 0) + (const_int 0) (const_int 0) + (const_int 0) (const_int 0) + (const_int 0) (const_int 0)]) (match_operand:DI 2 "reg_or_0_operand" "")))] "" { - tilegx_expand_builtin_vector_binop (gen_insn_mz_, mode, - operands[0], mode, operands[1], + tilegx_expand_builtin_vector_binop (gen_insn_mz_v8qi, V8QImode, + operands[0], V8QImode, operands[1], + operands[2], true); + DONE; +}) + +(define_insn "insn_mnz_v4hi" + [(set (match_operand:V4HI 0 "register_operand" "=r") + (if_then_else:V4HI + (ne:V4HI + (match_operand:V4HI 1 "reg_or_0_operand" "rO") + (const_vector:V4HI [(const_int 0) (const_int 0) + (const_int 0) (const_int 0)])) + (match_operand:V4HI 2 "reg_or_0_operand" "rO") + (const_vector:V4HI [(const_int 0) (const_int 0) + (const_int 0) (const_int 0)])))] + "" + "v2mnz\t%0, %r1, %r2" + [(set_attr "type" "X01")]) + +(define_expand "insn_v2mnz" + [(set (match_operand:DI 0 "register_operand" "") + (if_then_else:V4HI + (ne:V4HI + (match_operand:DI 1 "reg_or_0_operand" "") + (const_vector:V4HI [(const_int 0) (const_int 0) + (const_int 0) (const_int 0)])) + (match_operand:DI 2 "reg_or_0_operand" "") + (const_vector:V4HI [(const_int 0) (const_int 0) + (const_int 0) (const_int 0)])))] + "" +{ + tilegx_expand_builtin_vector_binop (gen_insn_mnz_v4hi, V4HImode, + operands[0], V4HImode, operands[1], + operands[2], true); + DONE; +}) + +(define_insn "insn_mz_v4hi" + [(set (match_operand:V4HI 0 "register_operand" "=r") + (if_then_else:V4HI + (ne:V4HI + (match_operand:V4HI 1 "reg_or_0_operand" "rO") + (const_vector:V4HI [(const_int 0) (const_int 0) + (const_int 0) (const_int 0)])) + (const_vector:V4HI [(const_int 0) (const_int 0) + (const_int 0) (const_int 0)]) + (match_operand:V4HI 2 "reg_or_0_operand" "rO")))] + "" + "v2mz\t%0, %r1, %r2" + [(set_attr "type" "X01")]) + +(define_expand "insn_v2mz" + [(set (match_operand:DI 0 "register_operand" "") + (if_then_else:V4HI + (ne:V4HI + (match_operand:DI 1 "reg_or_0_operand" "") + (const_vector:V4HI [(const_int 0) (const_int 0) + (const_int 0) (const_int 0)])) + (const_vector:V4HI [(const_int 0) (const_int 0) + (const_int 0) (const_int 0)]) + (match_operand:DI 2 "reg_or_0_operand" "")))] + "" +{ + tilegx_expand_builtin_vector_binop (gen_insn_mz_v4hi, V4HImode, + operands[0], V4HImode, operands[1], operands[2], true); DONE; })