diff mbox

[RFA/ARM] : Correct Neon testsuite generation

Message ID 20120312171934.GE7462@e103070-lin.arm.com
State New
Headers show

Commit Message

Matthew Gretton-Dann March 12, 2012, 5:19 p.m. UTC
All,

The commit to fix PR51534 did not update the testsuite (as no changes were
expected there).

Unfortunately, this means that I didn't notice that the Neon testsuite generator
is broken.  The attached patch fixes the generator.

Checked by re-running the Neon testsuite and arm_neon.h generators and ensuring no
changes in the generated testsuite/header.

OK for trunk?

OK for backporting to GCC 4.7?

Thanks,

Matt

gcc/ChangeLog:

2012-03-12  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>

	* config/arm/neon.ml (ops): Fixup expected instructions for
	unsigned vector compares.

Comments

Richard Earnshaw March 13, 2012, 10:19 a.m. UTC | #1
On 12/03/12 17:19, Matthew Gretton-Dann wrote:
> All,
> 
> The commit to fix PR51534 did not update the testsuite (as no changes were
> expected there).
> 
> Unfortunately, this means that I didn't notice that the Neon testsuite generator
> is broken.  The attached patch fixes the generator.
> 
> Checked by re-running the Neon testsuite and arm_neon.h generators and ensuring no
> changes in the generated testsuite/header.
> 
> OK for trunk?
> 
> OK for backporting to GCC 4.7?
> 

This is OK for trunk

It's OK for 4.7 if the RM's agree.

R.

> Thanks,
> 
> Matt
> 
> gcc/ChangeLog:
> 
> 2012-03-12  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
> 
> 	* config/arm/neon.ml (ops): Fixup expected instructions for
> 	unsigned vector compares.
> 
> 
> 1-RFA-GCC32A-569-Correct-Neon-testsuite-generation.txt
> 
> 
> diff --git a/gcc/config/arm/neon.ml b/gcc/config/arm/neon.ml
> index 363e55c..85eb5ec 100644
> --- a/gcc/config/arm/neon.ml
> +++ b/gcc/config/arm/neon.ml
> @@ -780,14 +780,19 @@ let ops =
>  
>      (* Comparison, greater-than or equal.  *)
>      Vcge, [], All (3, Dreg), "vcge", cmp_sign_matters, F32 :: s_8_32;
> -    Vcge, [Builtin_name "vcgeu"], All (3, Dreg), "vcge", cmp_sign_matters, u_8_32;
> +    Vcge, [Instruction_name ["vcge"]; Builtin_name "vcgeu"],
> +      All (3, Dreg), "vcge", cmp_sign_matters,
> +      u_8_32;
>      Vcge, [], All (3, Qreg), "vcgeQ", cmp_sign_matters, F32 :: s_8_32;
> -    Vcge, [Builtin_name "vcgeu"], All (3, Qreg), "vcgeQ", cmp_sign_matters, u_8_32;
> +    Vcge, [Instruction_name ["vcge"]; Builtin_name "vcgeu"],
> +      All (3, Qreg), "vcgeQ", cmp_sign_matters,
> +      u_8_32;
>  
>      (* Comparison, less-than or equal.  *)
>      Vcle, [Flipped "vcge"], All (3, Dreg), "vcle", cmp_sign_matters,
>        F32 :: s_8_32;
> -    Vcle, [Flipped "vcgeu"], All (3, Dreg), "vcle", cmp_sign_matters,
> +    Vcle, [Instruction_name ["vcge"]; Flipped "vcgeu"],
> +      All (3, Dreg), "vcle", cmp_sign_matters,
>        u_8_32;
>      Vcle, [Instruction_name ["vcge"]; Flipped "vcgeQ"],
>        All (3, Qreg), "vcleQ", cmp_sign_matters,
> @@ -798,14 +803,19 @@ let ops =
>  
>      (* Comparison, greater-than.  *)
>      Vcgt, [], All (3, Dreg), "vcgt", cmp_sign_matters, F32 :: s_8_32;
> -    Vcgt, [Builtin_name "vcgtu"], All (3, Dreg), "vcgt", cmp_sign_matters, u_8_32;
> +    Vcgt, [Instruction_name ["vcgt"]; Builtin_name "vcgtu"],
> +      All (3, Dreg), "vcgt", cmp_sign_matters,
> +      u_8_32;
>      Vcgt, [], All (3, Qreg), "vcgtQ", cmp_sign_matters, F32 :: s_8_32;
> -    Vcgt, [Builtin_name "vcgtu"], All (3, Qreg), "vcgtQ", cmp_sign_matters, u_8_32;
> +    Vcgt, [Instruction_name ["vcgt"]; Builtin_name "vcgtu"],
> +      All (3, Qreg), "vcgtQ", cmp_sign_matters,
> +      u_8_32;
>  
>      (* Comparison, less-than.  *)
>      Vclt, [Flipped "vcgt"], All (3, Dreg), "vclt", cmp_sign_matters,
>        F32 :: s_8_32;
> -    Vclt, [Flipped "vcgtu"], All (3, Dreg), "vclt", cmp_sign_matters,
> +    Vclt, [Instruction_name ["vcgt"]; Flipped "vcgtu"],
> +      All (3, Dreg), "vclt", cmp_sign_matters,
>        u_8_32;
>      Vclt, [Instruction_name ["vcgt"]; Flipped "vcgtQ"],
>        All (3, Qreg), "vcltQ", cmp_sign_matters,
diff mbox

Patch

diff --git a/gcc/config/arm/neon.ml b/gcc/config/arm/neon.ml
index 363e55c..85eb5ec 100644
--- a/gcc/config/arm/neon.ml
+++ b/gcc/config/arm/neon.ml
@@ -780,14 +780,19 @@  let ops =
 
     (* Comparison, greater-than or equal.  *)
     Vcge, [], All (3, Dreg), "vcge", cmp_sign_matters, F32 :: s_8_32;
-    Vcge, [Builtin_name "vcgeu"], All (3, Dreg), "vcge", cmp_sign_matters, u_8_32;
+    Vcge, [Instruction_name ["vcge"]; Builtin_name "vcgeu"],
+      All (3, Dreg), "vcge", cmp_sign_matters,
+      u_8_32;
     Vcge, [], All (3, Qreg), "vcgeQ", cmp_sign_matters, F32 :: s_8_32;
-    Vcge, [Builtin_name "vcgeu"], All (3, Qreg), "vcgeQ", cmp_sign_matters, u_8_32;
+    Vcge, [Instruction_name ["vcge"]; Builtin_name "vcgeu"],
+      All (3, Qreg), "vcgeQ", cmp_sign_matters,
+      u_8_32;
 
     (* Comparison, less-than or equal.  *)
     Vcle, [Flipped "vcge"], All (3, Dreg), "vcle", cmp_sign_matters,
       F32 :: s_8_32;
-    Vcle, [Flipped "vcgeu"], All (3, Dreg), "vcle", cmp_sign_matters,
+    Vcle, [Instruction_name ["vcge"]; Flipped "vcgeu"],
+      All (3, Dreg), "vcle", cmp_sign_matters,
       u_8_32;
     Vcle, [Instruction_name ["vcge"]; Flipped "vcgeQ"],
       All (3, Qreg), "vcleQ", cmp_sign_matters,
@@ -798,14 +803,19 @@  let ops =
 
     (* Comparison, greater-than.  *)
     Vcgt, [], All (3, Dreg), "vcgt", cmp_sign_matters, F32 :: s_8_32;
-    Vcgt, [Builtin_name "vcgtu"], All (3, Dreg), "vcgt", cmp_sign_matters, u_8_32;
+    Vcgt, [Instruction_name ["vcgt"]; Builtin_name "vcgtu"],
+      All (3, Dreg), "vcgt", cmp_sign_matters,
+      u_8_32;
     Vcgt, [], All (3, Qreg), "vcgtQ", cmp_sign_matters, F32 :: s_8_32;
-    Vcgt, [Builtin_name "vcgtu"], All (3, Qreg), "vcgtQ", cmp_sign_matters, u_8_32;
+    Vcgt, [Instruction_name ["vcgt"]; Builtin_name "vcgtu"],
+      All (3, Qreg), "vcgtQ", cmp_sign_matters,
+      u_8_32;
 
     (* Comparison, less-than.  *)
     Vclt, [Flipped "vcgt"], All (3, Dreg), "vclt", cmp_sign_matters,
       F32 :: s_8_32;
-    Vclt, [Flipped "vcgtu"], All (3, Dreg), "vclt", cmp_sign_matters,
+    Vclt, [Instruction_name ["vcgt"]; Flipped "vcgtu"],
+      All (3, Dreg), "vclt", cmp_sign_matters,
       u_8_32;
     Vclt, [Instruction_name ["vcgt"]; Flipped "vcgtQ"],
       All (3, Qreg), "vcltQ", cmp_sign_matters,