[committed,SH] Add atomic patterns

Message ID	20111205.080727.470553350.kkojima@rr.iij4u.or.jp
State	New
Headers	show Return-Path: <gcc-patches-return-309125-incoming=patchwork.ozlabs.org@gcc.gnu.org> Date: Mon, 05 Dec 2011 08:07:27 +0900 (JST) Message-Id: <20111205.080727.470553350.kkojima@rr.iij4u.or.jp> To: gcc-patches@gcc.gnu.org Subject: [patch committed SH] Add atomic patterns From: Kaz Kojima <kkojima@rr.iij4u.or.jp> Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk Sender: gcc-patches-owner@gcc.gnu.org

diff -uprN ORIG/trunk/gcc/config/sh/linux.h trunk/gcc/config/sh/linux.h --- ORIG/trunk/gcc/config/sh/linux.h 2011-11-13 09:19:44.000000000 +0900 +++ trunk/gcc/config/sh/linux.h 2011-12-04 08:05:43.000000000 +0900 @@ -41,7 +41,7 @@ along with GCC; see the file COPYING3. #undef TARGET_DEFAULT #define TARGET_DEFAULT \ (TARGET_CPU_DEFAULT | MASK_USERMODE | TARGET_ENDIAN_DEFAULT \ - | TARGET_OPT_DEFAULT) + | TARGET_OPT_DEFAULT | MASK_SOFT_ATOMIC) #define TARGET_ASM_FILE_END file_end_indicate_exec_stack diff -uprN ORIG/trunk/gcc/config/sh/sh.md trunk/gcc/config/sh/sh.md --- ORIG/trunk/gcc/config/sh/sh.md 2011-12-03 10:03:41.000000000 +0900 +++ trunk/gcc/config/sh/sh.md 2011-12-04 08:05:43.000000000 +0900 @@ -13667,3 +13667,5 @@ mov.l\\t1f,r0\\n\\ "ld%M1.q\t%m1, %0\;ld%M2.q\t%m2, %3\;cmpeq\t%0, %3, %0\;movi\t0, %3" [(set_attr "type" "other") (set_attr "length" "16")]) + +(include "sync.md") diff -uprN ORIG/trunk/gcc/config/sh/sh.opt trunk/gcc/config/sh/sh.opt --- ORIG/trunk/gcc/config/sh/sh.opt 2010-10-23 09:51:12.000000000 +0900 +++ trunk/gcc/config/sh/sh.opt 2011-12-05 07:56:25.000000000 +0900 @@ -1,6 +1,6 @@ ; Options for the SH port of the compiler. -; Copyright (C) 2005, 2006, 2007, 2008, 2009, 2010 +; Copyright (C) 2005, 2006, 2007, 2008, 2009, 2010, 2011 ; Free Software Foundation, Inc. ; ; This file is part of GCC. @@ -319,6 +319,10 @@ mrenesas Target Mask(HITACHI) MaskExists Follow Renesas (formerly Hitachi) / SuperH calling conventions +msoft-atomic +Target Report Mask(SOFT_ATOMIC) +Use software atomic sequences supported by kernel + mspace Target RejectNegative Alias(Os) Deprecated. Use -Os instead diff -uprN ORIG/trunk/gcc/config/sh/sync.md trunk/gcc/config/sh/sync.md --- ORIG/trunk/gcc/config/sh/sync.md 1970-01-01 09:00:00.000000000 +0900 +++ trunk/gcc/config/sh/sync.md 2011-12-04 08:14:20.000000000 +0900 @@ -0,0 +1,312 @@ +;; GCC machine description for SH synchronization instructions. +;; Copyright (C) 2011 +;; Free Software Foundation, Inc. +;; +;; This file is part of GCC. +;; +;; GCC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 3, or (at your option) +;; any later version. +;; +;; GCC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. +;; +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; <http://www.gnu.org/licenses/>. + +(define_c_enum "unspec" [ + UNSPEC_ATOMIC +]) + +(define_c_enum "unspecv" [ + UNSPECV_CMPXCHG_1 + UNSPECV_CMPXCHG_2 + UNSPECV_CMPXCHG_3 +]) + +(define_mode_iterator I124 [QI HI SI]) + +(define_mode_attr i124suffix [(QI "b") (HI "w") (SI "l")]) +(define_mode_attr i124extend_insn [(QI "exts.b") (HI "exts.w") (SI "mov")]) + +(define_code_iterator FETCHOP [plus minus ior xor and]) +(define_code_attr fetchop_name + [(plus "add") (minus "sub") (ior "ior") (xor "xor") (and "and")]) +(define_code_attr fetchop_insn + [(plus "add") (minus "sub") (ior "or") (xor "xor") (and "and")]) + +;; Linux specific atomic patterns for the Renesas / SuperH SH CPUs. +;; Linux kernel for SH3/4 has implemented the support for software +;; atomic sequences. + +(define_expand "atomic_compare_and_swap<mode>" + [(match_operand:QI 0 "register_operand" "") ;; bool success output + (match_operand:I124 1 "register_operand" "") ;; oldval output + (match_operand:I124 2 "memory_operand" "") ;; memory + (match_operand:I124 3 "register_operand" "") ;; expected input + (match_operand:I124 4 "register_operand" "") ;; newval input + (match_operand:SI 5 "const_int_operand" "") ;; is_weak + (match_operand:SI 6 "const_int_operand" "") ;; success model + (match_operand:SI 7 "const_int_operand" "")] ;; failure model + "TARGET_SOFT_ATOMIC && !TARGET_SHMEDIA" +{ + rtx addr; + + addr = force_reg (Pmode, XEXP (operands[2], 0)); + emit_insn (gen_atomic_compare_and_swap<mode>_soft + (gen_lowpart (SImode, operands[1]), addr, operands[3], + operands[4])); + if (<MODE>mode == QImode) + emit_insn (gen_zero_extendqisi2 (gen_lowpart (SImode, operands[1]), + operands[1])); + else if (<MODE>mode == HImode) + emit_insn (gen_zero_extendhisi2 (gen_lowpart (SImode, operands[1]), + operands[1])); + emit_insn (gen_movqi (operands[0], gen_rtx_REG (QImode, T_REG))); + DONE; +}) + +(define_insn "atomic_compare_and_swap<mode>_soft" + [(set (match_operand:SI 0 "register_operand" "=&u") + (unspec_volatile:SI + [(mem:I124 (match_operand:SI 1 "register_operand" "u")) + (match_operand:I124 2 "register_operand" "u") + (match_operand:I124 3 "register_operand" "u")] + UNSPECV_CMPXCHG_1)) + (set (mem:I124 (match_dup 1)) + (unspec_volatile:I124 [(const_int 0)] UNSPECV_CMPXCHG_2)) + (set (reg:QI T_REG) + (unspec_volatile:QI [(const_int 0)] UNSPECV_CMPXCHG_3)) + (clobber (match_scratch:SI 4 "=&u")) + (clobber (reg:SI R0_REG)) + (clobber (reg:SI R1_REG))] + "TARGET_SOFT_ATOMIC && !TARGET_SHMEDIA" + "* +{ + return \"\\ +mova\\t1f, r0\\n\\ +\\t<i124extend_insn>\\t%2, %4\\n\\ +\\tmov\\tr15, r1\\n\\ +\\tmov\\t#(0f-1f), r15\\n\\ +0:\\tmov.<i124suffix>\\t@%1, %0\\n\\ +\\tcmp/eq\\t%0, %4\\n\\ +\\tbf\\t1f\\n\\ +\\tmov.<i124suffix>\\t%3, @%1\\n\\ +\\t.align\\t2\\n\\ +1:\\tmov\tr1, r15\"; +}" + [(set_attr "length" "20")]) + +(define_expand "atomic_fetch_<fetchop_name><mode>" + [(set (match_operand:I124 0 "register_operand" "") + (match_operand:I124 1 "memory_operand" "")) + (set (match_dup 1) + (unspec:I124 + [(FETCHOP:I124 (match_dup 1) + (match_operand:I124 2 "register_operand" ""))] + UNSPEC_ATOMIC)) + (match_operand:SI 3 "const_int_operand" "")] + "TARGET_SOFT_ATOMIC && !TARGET_SHMEDIA" +{ + rtx addr; + + addr = force_reg (Pmode, XEXP (operands[1], 0)); + emit_insn (gen_atomic_fetch_<fetchop_name><mode>_soft + (operands[0], addr, operands[2])); + if (<MODE>mode == QImode) + emit_insn (gen_zero_extendqisi2 (gen_lowpart (SImode, operands[0]), + operands[0])); + else if (<MODE>mode == HImode) + emit_insn (gen_zero_extendhisi2 (gen_lowpart (SImode, operands[0]), + operands[0])); + DONE; +}) + +(define_insn "atomic_fetch_<fetchop_name><mode>_soft" + [(set (match_operand:I124 0 "register_operand" "=&u") + (mem:I124 (match_operand:SI 1 "register_operand" "u"))) + (set (mem:I124 (match_dup 1)) + (unspec:I124 + [(FETCHOP:I124 (mem:I124 (match_dup 1)) + (match_operand:I124 2 "register_operand" "u"))] + UNSPEC_ATOMIC)) + (clobber (match_scratch:I124 3 "=&u")) + (clobber (reg:SI R0_REG)) + (clobber (reg:SI R1_REG))] + "TARGET_SOFT_ATOMIC && !TARGET_SHMEDIA" + "* +{ + return \"\\ +mova\\t1f, r0\\n\\ +\\tmov\\tr15, r1\\n\\ +\\tmov\\t#(0f-1f), r15\\n\\ +0:\\tmov.<i124suffix>\\t@%1, %0\\n\\ +\\tmov\\t%0, %3\\n\\ +\\t<fetchop_insn>\\t%2, %3\\n\\ +\\tmov.<i124suffix>\\t%3, @%1\\n\\ +\\t.align\\t2\\n\\ +1:\\tmov\tr1, r15\"; +}" + [(set_attr "length" "18")]) + +(define_expand "atomic_fetch_nand<mode>" + [(set (match_operand:I124 0 "register_operand" "") + (match_operand:I124 1 "memory_operand" "")) + (set (match_dup 1) + (unspec:I124 + [(not:I124 (and:I124 (match_dup 1) + (match_operand:I124 2 "register_operand" "")))] + UNSPEC_ATOMIC)) + (match_operand:SI 3 "const_int_operand" "")] + "TARGET_SOFT_ATOMIC && !TARGET_SHMEDIA" +{ + rtx addr; + + addr = force_reg (Pmode, XEXP (operands[1], 0)); + emit_insn (gen_atomic_fetch_nand<mode>_soft + (operands[0], addr, operands[2])); + if (<MODE>mode == QImode) + emit_insn (gen_zero_extendqisi2 (gen_lowpart (SImode, operands[0]), + operands[0])); + else if (<MODE>mode == HImode) + emit_insn (gen_zero_extendhisi2 (gen_lowpart (SImode, operands[0]), + operands[0])); + DONE; +}) + +(define_insn "atomic_fetch_nand<mode>_soft" + [(set (match_operand:I124 0 "register_operand" "=&u") + (mem:I124 (match_operand:SI 1 "register_operand" "u"))) + (set (mem:I124 (match_dup 1)) + (unspec:I124 + [(not:I124 (and:I124 (mem:I124 (match_dup 1)) + (match_operand:I124 2 "register_operand" "u")))] + UNSPEC_ATOMIC)) + (clobber (match_scratch:I124 3 "=&u")) + (clobber (reg:SI R0_REG)) + (clobber (reg:SI R1_REG))] + "TARGET_SOFT_ATOMIC && !TARGET_SHMEDIA" + "* +{ + return \"\\ +mova\\t1f, r0\\n\\ +\\tmov\\tr15, r1\\n\\ +\\tmov\\t#(0f-1f), r15\\n\\ +0:\\tmov.<i124suffix>\\t@%1, %0\\n\\ +\\tmov\\t%2, %3\\n\\ +\\tand\\t%0, %3\\n\\ +\\tnot\\t%3, %3\\n\\ +\\tmov.<i124suffix>\\t%3, @%1\\n\\ +\\t.align\\t2\\n\\ +1:\\tmov\tr1, r15\"; +}" + [(set_attr "length" "20")]) + +(define_expand "atomic_<fetchop_name>_fetch<mode>" + [(set (match_operand:I124 0 "register_operand" "") + (FETCHOP:I124 + (match_operand:I124 1 "memory_operand" "") + (match_operand:I124 2 "register_operand" ""))) + (set (match_dup 1) + (unspec:I124 + [(FETCHOP:I124 (match_dup 1) (match_dup 2))] + UNSPEC_ATOMIC)) + (match_operand:SI 3 "const_int_operand" "")] + "TARGET_SOFT_ATOMIC && !TARGET_SHMEDIA" +{ + rtx addr; + + addr = force_reg (Pmode, XEXP (operands[1], 0)); + emit_insn (gen_atomic_<fetchop_name>_fetch<mode>_soft + (operands[0], addr, operands[2])); + if (<MODE>mode == QImode) + emit_insn (gen_zero_extendqisi2 (gen_lowpart (SImode, operands[0]), + operands[0])); + else if (<MODE>mode == HImode) + emit_insn (gen_zero_extendhisi2 (gen_lowpart (SImode, operands[0]), + operands[0])); + DONE; +}) + +(define_insn "atomic_<fetchop_name>_fetch<mode>_soft" + [(set (match_operand:I124 0 "register_operand" "=&u") + (FETCHOP:I124 + (mem:I124 (match_operand:SI 1 "register_operand" "u")) + (match_operand:I124 2 "register_operand" "u"))) + (set (mem:I124 (match_dup 1)) + (unspec:I124 + [(FETCHOP:I124 (mem:I124 (match_dup 1)) (match_dup 2))] + UNSPEC_ATOMIC)) + (clobber (reg:SI R0_REG)) + (clobber (reg:SI R1_REG))] + "TARGET_SOFT_ATOMIC && !TARGET_SHMEDIA" + "* +{ + return \"\\ +mova\\t1f, r0\\n\\ +\\tmov\\tr15, r1\\n\\ +\\tmov\\t#(0f-1f), r15\\n\\ +0:\\tmov.<i124suffix>\\t@%1, %0\\n\\ +\\t<fetchop_insn>\\t%2, %0\\n\\ +\\tmov.<i124suffix>\\t%0, @%1\\n\\ +\\t.align\\t2\\n\\ +1:\\tmov\tr1, r15\"; +}" + [(set_attr "length" "16")]) + +(define_expand "atomic_nand_fetch<mode>" + [(set (match_operand:I124 0 "register_operand" "") + (not:I124 (and:I124 + (match_operand:I124 1 "memory_operand" "") + (match_operand:I124 2 "register_operand" "")))) + (set (match_dup 1) + (unspec:I124 + [(not:I124 (and:I124 (match_dup 1) (match_dup 2)))] + UNSPEC_ATOMIC)) + (match_operand:SI 3 "const_int_operand" "")] + "TARGET_SOFT_ATOMIC && !TARGET_SHMEDIA" +{ + rtx addr; + + addr = force_reg (Pmode, XEXP (operands[1], 0)); + emit_insn (gen_atomic_nand_fetch<mode>_soft + (operands[0], addr, operands[2])); + if (<MODE>mode == QImode) + emit_insn (gen_zero_extendqisi2 (gen_lowpart (SImode, operands[0]), + operands[0])); + else if (<MODE>mode == HImode) + emit_insn (gen_zero_extendhisi2 (gen_lowpart (SImode, operands[0]), + operands[0])); + DONE; +}) + +(define_insn "atomic_nand_fetch<mode>_soft" + [(set (match_operand:I124 0 "register_operand" "=&u") + (not:I124 (and:I124 + (mem:I124 (match_operand:SI 1 "register_operand" "u")) + (match_operand:I124 2 "register_operand" "u")))) + (set (mem:I124 (match_dup 1)) + (unspec:I124 + [(not:I124 (and:I124 (mem:I124 (match_dup 1)) (match_dup 2)))] + UNSPEC_ATOMIC)) + (clobber (reg:SI R0_REG)) + (clobber (reg:SI R1_REG))] + "TARGET_SOFT_ATOMIC && !TARGET_SHMEDIA" + "* +{ + return \"\\ +mova\\t1f, r0\\n\\ +\\tmov\\tr15, r1\\n\\ +\\tmov\\t#(0f-1f), r15\\n\\ +0:\\tmov.<i124suffix>\\t@%1, %0\\n\\ +\\tand\\t%2, %0\\n\\ +\\tnot\\t%0, %0\\n\\ +\\tmov.<i124suffix>\\t%0, @%1\\n\\ +\\t.align\\t2\\n\\ +1:\\tmov\tr1, r15\"; +}" + [(set_attr "length" "18")]) diff -uprN ORIG/trunk/gcc/doc/invoke.texi trunk/gcc/doc/invoke.texi --- ORIG/trunk/gcc/doc/invoke.texi 2011-12-01 09:37:58.000000000 +0900 +++ trunk/gcc/doc/invoke.texi 2011-12-04 08:05:43.000000000 +0900 @@ -877,7 +877,7 @@ See RS/6000 and PowerPC Options. -mprefergot -musermode -multcost=@var{number} -mdiv=@var{strategy} @gol -mdivsi3_libfunc=@var{name} -mfixed-range=@var{register-range} @gol -madjust-unroll -mindexed-addressing -mgettrcost=@var{number} -mpt-fixed @gol --maccumulate-outgoing-args -minvalid-symbols} +-maccumulate-outgoing-args -minvalid-symbols -msoft-atomic} @emph{Solaris 2 Options} @gccoptlist{-mimpure-text -mno-impure-text @gol @@ -17547,6 +17547,11 @@ Dump instruction size and location in th This option is deprecated. It pads structures to multiple of 4 bytes, which is incompatible with the SH ABI@. +@item -msoft-atomic +@opindex msoft-atomic +Generate software atomic sequences for the atomic operations. +This is the default when the target is @code{sh-*-linux*}. + @item -mspace @opindex mspace Optimize for space instead of speed. Implied by @option{-Os}.

[committed,SH] Add atomic patterns

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