From patchwork Mon Oct 3 23:00:55 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 117515 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id B73A8B6F75 for ; Tue, 4 Oct 2011 10:01:14 +1100 (EST) Received: (qmail 12110 invoked by alias); 3 Oct 2011 23:01:12 -0000 Received: (qmail 12100 invoked by uid 22791); 3 Oct 2011 23:01:11 -0000 X-SWARE-Spam-Status: No, hits=-1.8 required=5.0 tests=AWL, BAYES_00, NO_DNS_FOR_FROM, RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from mga14.intel.com (HELO mga14.intel.com) (143.182.124.37) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Mon, 03 Oct 2011 23:00:57 +0000 Received: from azsmga002.ch.intel.com ([10.2.17.35]) by azsmga102.ch.intel.com with ESMTP; 03 Oct 2011 16:00:57 -0700 X-ExtLoop1: 1 Received: from gnu-6.sc.intel.com ([10.3.194.135]) by AZSMGA002.ch.intel.com with ESMTP; 03 Oct 2011 16:00:56 -0700 Received: by gnu-6.sc.intel.com (Postfix, from userid 500) id D8DF2C1A60; Mon, 3 Oct 2011 16:00:55 -0700 (PDT) Date: Mon, 3 Oct 2011 16:00:55 -0700 From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Cc: ubizjak@gmail.com Subject: PATCH: PR target/50603: [x32] Unnecessary lea Message-ID: <20111003230055.GA27052@intel.com> Reply-To: "H.J. Lu" MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org This patch improves address combine for x32 by forcing the memory memory operand of PLUS operation into register. Tested on Linux/x86-64 with -mx32. OK for trunk? Thanks. H.J. --- 2011-10-03 H.J. Lu PR target/50603 * config/i386/i386.c (ix86_fixup_binary_operands): Force the memory operand of PLUS operation into register for x32. diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 9b079af..922f691 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -15713,6 +15713,16 @@ ix86_fixup_binary_operands (enum rtx_code code, enum machine_mode mode, else src2 = force_reg (mode, src2); } + else + { + /* Improve address combine in x32 mode. */ + if (TARGET_X32 + && code == PLUS + && !MEM_P (dst) + && !MEM_P (src1) + && MEM_P (src2) ) + src2 = force_reg (mode, src2); + } /* If the destination is memory, and we do not have matching source operands, do things in registers. */