diff mbox

PATCH: PR target/49142: Invalid 8bit register operand

Message ID 20110524155424.GA7400@intel.com
State New
Headers show

Commit Message

H.J. Lu May 24, 2011, 3:54 p.m. UTC
Hi,

We are working on a new optimization, which turns off TARGET_MOVX.
GCC generates:

movb %ah, %dil

But %ah can only be used with %[abcd][hl].  This patch adds QIreg_operand
and uses it in *movqi_extv_1_rex64/*movqi_extzv_2_rex64.  OK for trunk
if there is no regression?

Thanks.


H.J.
---
2011-05-24  H.J. Lu  <hongjiu.lu@intel.com>

	PR target/49142
	* config/i386/i386.md (*movqi_extv_1_rex64): Replace
	q_regs_operand with QIreg_operand.
	(*movqi_extzv_2_rex64): Likewise.

	* config/i386/predicates.md (QIreg_operand): New.

Comments

Uros Bizjak May 25, 2011, 2 p.m. UTC | #1
On Tue, May 24, 2011 at 5:54 PM, H.J. Lu <hongjiu.lu@intel.com> wrote:
> Hi,
>
> We are working on a new optimization, which turns off TARGET_MOVX.
> GCC generates:
>
> movb %ah, %dil
>
> But %ah can only be used with %[abcd][hl].  This patch adds QIreg_operand
> and uses it in *movqi_extv_1_rex64/*movqi_extzv_2_rex64.  OK for trunk
> if there is no regression?

If this is the case, then please change "q_regs_operand" predicate to
accept just QI_REG_P registers.

Uros.
H.J. Lu May 25, 2011, 2:42 p.m. UTC | #2
On Wed, May 25, 2011 at 7:00 AM, Uros Bizjak <ubizjak@gmail.com> wrote:
> On Tue, May 24, 2011 at 5:54 PM, H.J. Lu <hongjiu.lu@intel.com> wrote:
>> Hi,
>>
>> We are working on a new optimization, which turns off TARGET_MOVX.
>> GCC generates:
>>
>> movb %ah, %dil
>>
>> But %ah can only be used with %[abcd][hl].  This patch adds QIreg_operand
>> and uses it in *movqi_extv_1_rex64/*movqi_extzv_2_rex64.  OK for trunk
>> if there is no regression?
>
> If this is the case, then please change "q_regs_operand" predicate to
> accept just QI_REG_P registers.
>

I thought about it.  It is a problem only with %[abcd]h.  I am not sure if
changing q_regs_operand to  accept just QI_REG_P registers will negatively
impact

(define_peephole2
  [(set (reg FLAGS_REG) (match_operand 0 "" ""))
   (set (match_operand:QI 1 "register_operand" "")
        (match_operator:QI 2 "ix86_comparison_operator"
          [(reg FLAGS_REG) (const_int 0)]))
   (set (match_operand 3 "q_regs_operand" "")
        (zero_extend (match_dup 1)))]
  "(peep2_reg_dead_p (3, operands[1])
    || operands_match_p (operands[1], operands[3]))
   && ! reg_overlap_mentioned_p (operands[3], operands[0])"
  [(set (match_dup 4) (match_dup 0))
   (set (strict_low_part (match_dup 5))
        (match_dup 2))]

(define_peephole2
  [(set (reg FLAGS_REG) (match_operand 0 "" ""))
   (set (match_operand:QI 1 "register_operand" "")
        (match_operator:QI 2 "ix86_comparison_operator"
          [(reg FLAGS_REG) (const_int 0)]))
   (parallel [(set (match_operand 3 "q_regs_operand" "")
                   (zero_extend (match_dup 1)))
              (clobber (reg:CC FLAGS_REG))])]
  "(peep2_reg_dead_p (3, operands[1])
    || operands_match_p (operands[1], operands[3]))
   && ! reg_overlap_mentioned_p (operands[3], operands[0])"
  [(set (match_dup 4) (match_dup 0))
   (set (strict_low_part (match_dup 5))
        (match_dup 2))]
Uros Bizjak May 25, 2011, 3:30 p.m. UTC | #3
On Wed, May 25, 2011 at 4:42 PM, H.J. Lu <hjl.tools@gmail.com> wrote:
> On Wed, May 25, 2011 at 7:00 AM, Uros Bizjak <ubizjak@gmail.com> wrote:
>> On Tue, May 24, 2011 at 5:54 PM, H.J. Lu <hongjiu.lu@intel.com> wrote:
>>> Hi,
>>>
>>> We are working on a new optimization, which turns off TARGET_MOVX.
>>> GCC generates:
>>>
>>> movb %ah, %dil
>>>
>>> But %ah can only be used with %[abcd][hl].  This patch adds QIreg_operand
>>> and uses it in *movqi_extv_1_rex64/*movqi_extzv_2_rex64.  OK for trunk
>>> if there is no regression? and Replace
       q_regs_operand with QIreg_operand.
       (
>>
>> If this is the case, then please change "q_regs_operand" predicate to
>> accept just QI_REG_P registers.
>>
>
> I thought about it.  It is a problem only with %[abcd]h.  I am not sure if
> changing q_regs_operand to  accept just QI_REG_P registers will negatively
> impact

I see. The patch is OK then, but for consistency, please change the
predicate of *movqi_extv_1*movqi_extzv_2 as well. Oh, and the
"register_operand" check in "type" calculation can be removed.

Thanks,
Uros.
diff mbox

Patch

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 6c158cf..b7f5866 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -2635,7 +2635,7 @@ 
 }
   [(set (attr "type")
      (if_then_else (and (match_operand:QI 0 "register_operand" "")
-			(ior (not (match_operand:QI 0 "q_regs_operand" ""))
+			(ior (not (match_operand:QI 0 "QIreg_operand" ""))
 			     (ne (symbol_ref "TARGET_MOVX")
 				 (const_int 0))))
 	(const_string "imovx")
@@ -2699,7 +2699,7 @@ 
     }
 }
   [(set (attr "type")
-     (if_then_else (ior (not (match_operand:QI 0 "q_regs_operand" ""))
+     (if_then_else (ior (not (match_operand:QI 0 "QIreg_operand" ""))
 			(ne (symbol_ref "TARGET_MOVX")
 			    (const_int 0)))
 	(const_string "imovx")
diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md
index 8a89f70..1471f5a 100644
--- a/gcc/config/i386/predicates.md
+++ b/gcc/config/i386/predicates.md
@@ -82,6 +82,10 @@ 
   (and (match_code "reg")
        (match_test "REGNO (op) == FLAGS_REG")))
 
+;; Return true if op is one of QImode registers: %[abcd][hl].
+(define_predicate "QIreg_operand"
+  (match_test "QI_REG_P (op)"))
+
 ;; Return true if op is a QImode register operand other than
 ;; %[abcd][hl].
 (define_predicate "ext_QIreg_operand"