===================================================================
@@ -2677,7 +2677,7 @@ Don't define this macro unless the targe
require the macro to do something nontrivial.
@end defmac
-@deftypefn {Target Hook} {enum reg_class} TARGET_SECONDARY_RELOAD (bool @var{in_p}, rtx @var{x}, enum reg_class @var{reload_class}, enum machine_mode @var{reload_mode}, secondary_reload_info *@var{sri})
+@deftypefn {Target Hook} {reg_class_t} TARGET_SECONDARY_RELOAD (bool @var{in_p}, rtx @var{x}, reg_class_t @var{reload_class}, enum machine_mode @var{reload_mode}, secondary_reload_info *@var{sri})
Many machines have some registers that cannot be copied directly to or
from memory or even from other types of registers. An example is the
@samp{MQ} register, which on most machines, can only be copied to or
@@ -2917,7 +2917,7 @@ as below:
@end smallexample
@end defmac
-@deftypefn {Target Hook} {const enum reg_class *} TARGET_IRA_COVER_CLASSES (void)
+@deftypefn {Target Hook} {const reg_class_t *} TARGET_IRA_COVER_CLASSES (void)
Return an array of cover classes for the Integrated Register Allocator
(@acronym{IRA}). Cover classes are a set of non-intersecting register
classes covering all hard registers used for register allocation
@@ -6177,7 +6177,7 @@ These macros are obsolete, new ports sho
@code{TARGET_MEMORY_MOVE_COST} instead.
@end defmac
-@deftypefn {Target Hook} int TARGET_MEMORY_MOVE_COST (enum machine_mode @var{mode}, enum reg_class @var{regclass}, bool @var{in})
+@deftypefn {Target Hook} int TARGET_MEMORY_MOVE_COST (enum machine_mode @var{mode}, reg_class_t @var{regclass}, bool @var{in})
This target hook should return the cost of moving data of mode @var{mode}
between a register of class @var{class} and memory; @var{in} is @code{false}
if the value is to be written to memory, @code{true} if it is to be read in.
@@ -10949,7 +10949,7 @@ cannot_modify_jumps_past_reload_p ()
@end smallexample
@end deftypefn
-@deftypefn {Target Hook} {enum reg_class} TARGET_BRANCH_TARGET_REGISTER_CLASS (void)
+@deftypefn {Target Hook} {reg_class_t} TARGET_BRANCH_TARGET_REGISTER_CLASS (void)
This target hook returns a register class for which branch target register
optimizations should be applied. All registers in this class should be
usable interchangeably. After reload, registers in this class will be
===================================================================
@@ -756,28 +756,29 @@ default_trampoline_init (rtx ARG_UNUSED
sorry ("nested function trampolines not supported on this target");
}
-enum reg_class
+reg_class_t
default_branch_target_register_class (void)
{
return NO_REGS;
}
#ifdef IRA_COVER_CLASSES
-const enum reg_class *
+const reg_class_t *
default_ira_cover_classes (void)
{
- static enum reg_class classes[] = IRA_COVER_CLASSES;
+ static reg_class_t classes[] = IRA_COVER_CLASSES;
return classes;
}
#endif
-enum reg_class
+reg_class_t
default_secondary_reload (bool in_p ATTRIBUTE_UNUSED, rtx x ATTRIBUTE_UNUSED,
- enum reg_class reload_class ATTRIBUTE_UNUSED,
+ reg_class_t reload_class_i ATTRIBUTE_UNUSED,
enum machine_mode reload_mode ATTRIBUTE_UNUSED,
secondary_reload_info *sri)
{
enum reg_class rclass = NO_REGS;
+ enum reg_class reload_class = (enum reg_class) reload_class_i;
if (sri->prev_sri && sri->prev_sri->t_icode != CODE_FOR_nothing)
{
@@ -1117,13 +1118,13 @@ default_have_conditional_execution (void
int
default_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
- enum reg_class rclass ATTRIBUTE_UNUSED,
+ reg_class_t rclass ATTRIBUTE_UNUSED,
bool in ATTRIBUTE_UNUSED)
{
#ifndef MEMORY_MOVE_COST
- return (4 + memory_move_secondary_cost (mode, rclass, in));
+ return (4 + memory_move_secondary_cost (mode, (enum reg_class) rclass, in));
#else
- return MEMORY_MOVE_COST (mode, rclass, in);
+ return MEMORY_MOVE_COST (mode, (enum reg_class) rclass, in);
#endif
}
===================================================================
@@ -108,13 +108,13 @@ extern bool default_function_value_regno
extern rtx default_internal_arg_pointer (void);
extern rtx default_static_chain (const_tree, bool);
extern void default_trampoline_init (rtx, tree, rtx);
-extern enum reg_class default_branch_target_register_class (void);
+extern reg_class_t default_branch_target_register_class (void);
#ifdef IRA_COVER_CLASSES
-extern const enum reg_class *default_ira_cover_classes (void);
+extern const reg_class_t *default_ira_cover_classes (void);
#endif
-extern enum reg_class default_secondary_reload (bool, rtx, enum reg_class,
- enum machine_mode,
- secondary_reload_info *);
+extern reg_class_t default_secondary_reload (bool, rtx, reg_class_t,
+ enum machine_mode,
+ secondary_reload_info *);
extern void hook_void_bitmap (bitmap);
extern bool default_handle_c_option (size_t, const char *, int);
extern int default_reloc_rw_mask (void);
@@ -139,4 +139,4 @@ extern bool default_addr_space_subset_p
extern rtx default_addr_space_convert (rtx, tree, tree);
extern unsigned int default_case_values_threshold (void);
extern bool default_have_conditional_execution (void);
-extern int default_memory_move_cost (enum machine_mode, enum reg_class, bool);
+extern int default_memory_move_cost (enum machine_mode, reg_class_t, bool);
===================================================================
@@ -363,7 +363,8 @@ push_secondary_reload (int in_p, rtx x,
sri.icode = CODE_FOR_nothing;
sri.prev_sri = prev_sri;
- rclass = targetm.secondary_reload (in_p, x, reload_class, reload_mode, &sri);
+ rclass = (enum reg_class) targetm.secondary_reload (in_p, x, reload_class,
+ reload_mode, &sri);
icode = (enum insn_code) sri.icode;
/* If we don't need any secondary registers, done. */
@@ -526,7 +527,8 @@ secondary_reload_class (bool in_p, enum
sri.icode = CODE_FOR_nothing;
sri.prev_sri = NULL;
- rclass = targetm.secondary_reload (in_p, x, rclass, mode, &sri);
+ rclass
+ = (enum reg_class) targetm.secondary_reload (in_p, x, rclass, mode, &sri);
icode = (enum insn_code) sri.icode;
/* If there are no secondary reloads at all, we return NO_REGS.
===================================================================
@@ -675,7 +675,7 @@ struct gcc_target
/* Return a register class for which branch target register
optimizations should be applied. */
- enum reg_class (* branch_target_register_class) (void);
+ reg_class_t (* branch_target_register_class) (void);
/* Return true if branch target register optimizations should include
callee-saved registers that are not already live during the current
@@ -813,7 +813,7 @@ struct gcc_target
bool (* vector_mode_supported_p) (enum machine_mode mode);
/* Compute cost of moving registers to/from memory. */
- int (* memory_move_cost) (enum machine_mode, enum reg_class, bool);
+ int (* memory_move_cost) (enum machine_mode, reg_class_t, bool);
/* True for MODE if the target expects that registers in this mode will
be allocated to registers in a small register class. The compiler is
@@ -1092,12 +1092,11 @@ struct gcc_target
tree (*convert_to_type) (tree type, tree expr);
/* Return the array of IRA cover classes for the current target. */
- const enum reg_class *(*ira_cover_classes) (void);
+ const reg_class_t *(*ira_cover_classes) (void);
/* Return the class for a secondary reload, and fill in extra information. */
- enum reg_class (*secondary_reload) (bool, rtx, enum reg_class,
- enum machine_mode,
- secondary_reload_info *);
+ reg_class_t (*secondary_reload) (bool, rtx, reg_class_t, enum machine_mode,
+ secondary_reload_info *);
/* This target hook allows the backend to perform additional
processing while initializing for variable expansion. */
===================================================================
@@ -119,6 +119,11 @@ typedef const struct basic_block_def *co
obstack_chunk_alloc, \
obstack_chunk_free)
+/* enum reg_class is target specific, so it should not appear in
+ target-independent code or interfaces, like the target hook declarations
+ in target.h. */
+typedef int reg_class_t;
+
#else
struct _dont_use_rtx_here_;
===================================================================
@@ -1458,7 +1458,8 @@ migrate_btr_defs (enum reg_class btr_cla
static void
branch_target_load_optimize (bool after_prologue_epilogue_gen)
{
- enum reg_class klass = targetm.branch_target_register_class ();
+ enum reg_class klass
+ = (enum reg_class) targetm.branch_target_register_class ();
if (klass != NO_REGS)
{
/* Initialize issue_rate. */
===================================================================
@@ -743,7 +743,7 @@ setup_cover_and_important_classes (void)
{
int i, j, n, cl;
bool set_p;
- const enum reg_class *cover_classes;
+ const reg_class_t *cover_classes;
HARD_REG_SET temp_hard_regset2;
static enum reg_class classes[LIM_REG_CLASSES + 1];
===================================================================
@@ -156,7 +156,8 @@ copy_cost (rtx x, enum machine_mode mode
copy it. */
sri.prev_sri = prev_sri;
sri.extra_cost = 0;
- secondary_class = targetm.secondary_reload (to_p, x, rclass, mode, &sri);
+ secondary_class
+ = (enum reg_class) targetm.secondary_reload (to_p, x, rclass, mode, &sri);
if (secondary_class != NO_REGS)
{
===================================================================
@@ -1569,10 +1569,12 @@ alpha_preferred_reload_class(rtx x, enum
RCLASS requires an extra scratch or immediate register. Return the class
needed for the immediate register. */
-static enum reg_class
-alpha_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
+static reg_class_t
+alpha_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
enum machine_mode mode, secondary_reload_info *sri)
{
+ enum reg_class rclass = (enum reg_class) rclass_i;
+
/* Loading and storing HImode or QImode values to and from memory
usually requires a scratch register. */
if (!TARGET_BWX && (mode == QImode || mode == HImode || mode == CQImode))
===================================================================
@@ -1,5 +1,5 @@
/* Copyright (C) 1997, 1998, 1999, 2000, 2001, 2003, 2004, 2005, 2006, 2007,
- 2008, 2009 Free Software Foundation, Inc.
+ 2008, 2009, 2010 Free Software Foundation, Inc.
Contributed by Red Hat, Inc.
This file is part of GCC.
@@ -384,7 +384,7 @@ static int frv_arg_partial_bytes (CUMULA
tree, bool);
static void frv_output_dwarf_dtprel (FILE *, int, rtx)
ATTRIBUTE_UNUSED;
-static bool frv_secondary_reload (bool, rtx, enum reg_class,
+static reg_class_t frv_secondary_reload (bool, rtx, reg_class_t,
enum machine_mode,
secondary_reload_info *);
static bool frv_frame_pointer_required (void);
@@ -6492,12 +6492,13 @@ frv_secondary_reload_class (enum reg_cla
called from init_reg_autoinc() in regclass.c - before the reload optabs
have been initialised. */
-static bool
-frv_secondary_reload (bool in_p, rtx x, enum reg_class reload_class,
+static reg_class_t
+frv_secondary_reload (bool in_p, rtx x, reg_class_t reload_class_i,
enum machine_mode reload_mode,
secondary_reload_info * sri)
{
enum reg_class rclass = NO_REGS;
+ enum reg_class reload_class = (enum reg_class) reload_class_i;
if (sri->prev_sri && sri->prev_sri->t_icode != CODE_FOR_nothing)
{
===================================================================
@@ -2957,10 +2957,12 @@ s390_reload_symref_address (rtx reg, rtx
RCLASS requires an extra scratch or immediate register. Return the class
needed for the immediate register. */
-static enum reg_class
-s390_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
+static reg_class_t
+s390_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
enum machine_mode mode, secondary_reload_info *sri)
{
+ enum reg_class rclass = (enum reg_class) rclass_i;
+
/* Intermediate register needed. */
if (reg_classes_intersect_p (CC_REGS, rclass))
return GENERAL_REGS;
===================================================================
@@ -25245,13 +25245,13 @@ ix86_free_from_memory (enum machine_mode
/* Implement TARGET_IRA_COVER_CLASSES. If -mfpmath=sse, we prefer
SSE_REGS to FLOAT_REGS if their costs for a pseudo are the
same. */
-static const enum reg_class *
+static const reg_class_t *
i386_ira_cover_classes (void)
{
- static const enum reg_class sse_fpmath_classes[] = {
+ static const reg_class_t sse_fpmath_classes[] = {
GENERAL_REGS, SSE_REGS, MMX_REGS, FLOAT_REGS, LIM_REG_CLASSES
};
- static const enum reg_class no_sse_fpmath_classes[] = {
+ static const reg_class_t no_sse_fpmath_classes[] = {
GENERAL_REGS, FLOAT_REGS, MMX_REGS, SSE_REGS, LIM_REG_CLASSES
};
@@ -25361,8 +25361,8 @@ ix86_preferred_output_reload_class (rtx
return regclass;
}
-static enum reg_class
-ix86_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
+static reg_class_t
+ix86_secondary_reload (bool in_p, rtx x, reg_class_t rclass,
enum machine_mode mode,
secondary_reload_info *sri ATTRIBUTE_UNUSED)
{
@@ -25615,10 +25615,10 @@ inline_memory_move_cost (enum machine_mo
}
static int
-ix86_memory_move_cost (enum machine_mode mode, enum reg_class regclass,
+ix86_memory_move_cost (enum machine_mode mode, reg_class_t regclass,
bool in)
{
- return inline_memory_move_cost (mode, regclass, in ? 1 : 0);
+ return inline_memory_move_cost (mode, (enum reg_class) regclass, in ? 1 : 0);
}
===================================================================
@@ -173,9 +173,9 @@ extern int sh_contains_memref_p (rtx);
extern int sh_loads_bankedreg_p (rtx);
extern rtx shmedia_prepare_call_address (rtx fnaddr, int is_sibcall);
struct secondary_reload_info;
-extern enum reg_class sh_secondary_reload (bool, rtx, enum reg_class,
- enum machine_mode,
- struct secondary_reload_info *);
+extern reg_class_t sh_secondary_reload (bool, rtx, reg_class_t,
+ enum machine_mode,
+ struct secondary_reload_info *);
extern int sh2a_get_function_vector_number (rtx);
extern int sh2a_is_function_vector_call (rtx);
extern void sh_fix_range (const char *);
===================================================================
@@ -225,7 +225,7 @@ static int sh_variable_issue (FILE *, in
static bool sh_function_ok_for_sibcall (tree, tree);
static bool sh_cannot_modify_jumps_p (void);
-static enum reg_class sh_target_reg_class (void);
+static reg_class_t sh_target_reg_class (void);
static bool sh_optimize_target_register_callee_saved (bool);
static bool sh_ms_bitfield_layout_p (const_tree);
@@ -10519,7 +10519,7 @@ sh_cannot_modify_jumps_p (void)
return (TARGET_SHMEDIA && (reload_in_progress || reload_completed));
}
-static enum reg_class
+static reg_class_t
sh_target_reg_class (void)
{
return TARGET_SHMEDIA ? TARGET_REGS : NO_REGS;
@@ -12158,10 +12158,12 @@ shmedia_prepare_call_address (rtx fnaddr
return fnaddr;
}
-enum reg_class
-sh_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
+reg_class_t
+sh_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
enum machine_mode mode, secondary_reload_info *sri)
{
+ enum reg_class rclass = (enum reg_class) rclass_i;
+
if (in_p)
{
if (REGCLASS_HAS_FP_REG (rclass)
===================================================================
@@ -1,5 +1,5 @@
/* Subroutines for insn-output.c for Tensilica's Xtensa architecture.
- Copyright 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
+ Copyright 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
Free Software Foundation, Inc.
Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
@@ -3089,8 +3089,8 @@ xtensa_preferred_reload_class (rtx x, en
}
-enum reg_class
-xtensa_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
+reg_class_t
+xtensa_secondary_reload (bool in_p, rtx x, reg_class_t rclass,
enum machine_mode mode, secondary_reload_info *sri)
{
int regno;
===================================================================
@@ -67,9 +67,9 @@ extern void xtensa_output_literal (FILE
extern rtx xtensa_return_addr (int, rtx);
extern enum reg_class xtensa_preferred_reload_class (rtx, enum reg_class, int);
struct secondary_reload_info;
-extern enum reg_class xtensa_secondary_reload (bool, rtx, enum reg_class,
- enum machine_mode,
- struct secondary_reload_info *);
+extern reg_class_t xtensa_secondary_reload (bool, rtx, reg_class_t,
+ enum machine_mode,
+ struct secondary_reload_info *);
#endif /* RTX_CODE */
#ifdef TREE_CODE
===================================================================
@@ -1221,11 +1221,11 @@ bool (*rs6000_cannot_change_mode_class_p
enum reg_class)
= rs6000_cannot_change_mode_class;
-static enum reg_class rs6000_secondary_reload (bool, rtx, enum reg_class,
- enum machine_mode,
- struct secondary_reload_info *);
+static reg_class_t rs6000_secondary_reload (bool, rtx, reg_class_t,
+ enum machine_mode,
+ struct secondary_reload_info *);
-static const enum reg_class *rs6000_ira_cover_classes (void);
+static const reg_class_t *rs6000_ira_cover_classes (void);
const int INSN_NOT_AVAILABLE = -1;
static enum machine_mode rs6000_eh_return_filter_mode (void);
@@ -13732,14 +13732,15 @@ rs6000_reload_register_type (enum reg_cl
For VSX and Altivec, we may need a register to convert sp+offset into
reg+sp. */
-static enum reg_class
+static reg_class_t
rs6000_secondary_reload (bool in_p,
rtx x,
- enum reg_class rclass,
+ reg_class_t rclass_i,
enum machine_mode mode,
secondary_reload_info *sri)
{
- enum reg_class ret = ALL_REGS;
+ enum reg_class rclass = (enum reg_class) rclass_i;
+ reg_class_t ret = ALL_REGS;
enum insn_code icode;
bool default_p = false;
@@ -14131,11 +14132,11 @@ rs6000_secondary_reload_inner (rtx reg,
account for the Altivec and Floating registers being subsets of the VSX
register set under VSX, but distinct register sets on pre-VSX machines. */
-static const enum reg_class *
+static const reg_class_t *
rs6000_ira_cover_classes (void)
{
- static const enum reg_class cover_pre_vsx[] = IRA_COVER_CLASSES_PRE_VSX;
- static const enum reg_class cover_vsx[] = IRA_COVER_CLASSES_VSX;
+ static const reg_class_t cover_pre_vsx[] = IRA_COVER_CLASSES_PRE_VSX;
+ static const reg_class_t cover_vsx[] = IRA_COVER_CLASSES_VSX;
return (TARGET_VSX) ? cover_vsx : cover_pre_vsx;
}
===================================================================
@@ -1,5 +1,5 @@
/* Subroutines used for code generation on picoChip processors.
- Copyright (C) 2001,2008, 2009 Free Software Foundation, Inc.
+ Copyright (C) 2001, 2008, 2009, 2010 Free Software Foundation, Inc.
Contributed by picoChip Designs Ltd. (http://www.picochip.com)
Maintained by Daniel Towner (daniel.towner@picochip.com) and
Hariharan Sandanagobalane (hariharan@picochip.com)
@@ -103,12 +103,12 @@ int picochip_legitimize_reload_address (
rtx picochip_struct_value_rtx(tree fntype ATTRIBUTE_UNUSED, int incoming ATTRIBUTE_UNUSED);
rtx picochip_function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED,
bool outgoing ATTRIBUTE_UNUSED);
-enum reg_class
+reg_class_t
picochip_secondary_reload (bool in_p,
- rtx x ATTRIBUTE_UNUSED,
- enum reg_class cla ATTRIBUTE_UNUSED,
- enum machine_mode mode,
- secondary_reload_info *sri);
+ rtx x ATTRIBUTE_UNUSED,
+ reg_class_t cla ATTRIBUTE_UNUSED,
+ enum machine_mode mode,
+ secondary_reload_info *sri);
void
picochip_asm_named_section (const char *name,
unsigned int flags ATTRIBUTE_UNUSED,
@@ -4363,12 +4363,12 @@ picochip_get_high_const (rtx value)
choice of two registers to choose from, so that we a guaranteed to
get at least one register which is different to the output
register. This trick is taken from the alpha implementation. */
-enum reg_class
+reg_class_t
picochip_secondary_reload (bool in_p,
- rtx x ATTRIBUTE_UNUSED,
- enum reg_class cla ATTRIBUTE_UNUSED,
- enum machine_mode mode,
- secondary_reload_info *sri)
+ rtx x ATTRIBUTE_UNUSED,
+ reg_class_t cla ATTRIBUTE_UNUSED,
+ enum machine_mode mode,
+ secondary_reload_info *sri)
{
if (mode == QImode && !TARGET_HAS_BYTE_ACCESS)
{
===================================================================
@@ -73,9 +73,9 @@ extern int picochip_symbol_offset (rtx o
extern int picochip_get_function_arg_boundary (enum machine_mode mode);
-extern enum reg_class picochip_secondary_reload(bool in_p,
+extern reg_class_t picochip_secondary_reload(bool in_p,
rtx x,
- enum reg_class cla,
+ reg_class_t cla,
enum machine_mode mode,
secondary_reload_info *sri);
===================================================================
@@ -155,9 +155,9 @@ static bool pa_pass_by_reference (CUMULA
static int pa_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
tree, bool);
static struct machine_function * pa_init_machine_status (void);
-static enum reg_class pa_secondary_reload (bool, rtx, enum reg_class,
- enum machine_mode,
- secondary_reload_info *);
+static reg_class_t pa_secondary_reload (bool, rtx, reg_class_t,
+ enum machine_mode,
+ secondary_reload_info *);
static void pa_extra_live_on_entry (bitmap);
static enum machine_mode pa_promote_function_mode (const_tree,
enum machine_mode, int *,
@@ -5688,11 +5688,12 @@ output_arg_descriptor (rtx call_insn)
fputc ('\n', asm_out_file);
}
-static enum reg_class
-pa_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
+static reg_class_t
+pa_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
enum machine_mode mode, secondary_reload_info *sri)
{
int is_symbolic, regno;
+ enum reg_class rclass = (enum reg_class) rclass_i;
/* Handle the easy stuff first. */
if (rclass == R1_REGS)
===================================================================
@@ -10929,14 +10929,14 @@ mips_register_move_cost (enum machine_mo
/* Implement TARGET_IRA_COVER_CLASSES. */
-static const enum reg_class *
+static const reg_class_t *
mips_ira_cover_classes (void)
{
- static const enum reg_class acc_classes[] = {
+ static const reg_class_t acc_classes[] = {
GR_AND_ACC_REGS, FP_REGS, COP0_REGS, COP2_REGS, COP3_REGS,
ST_REGS, LIM_REG_CLASSES
};
- static const enum reg_class no_acc_classes[] = {
+ static const reg_class_t no_acc_classes[] = {
GR_REGS, FP_REGS, COP0_REGS, COP2_REGS, COP3_REGS,
ST_REGS, LIM_REG_CLASSES
};
===================================================================
@@ -2458,8 +2458,8 @@ bfin_memory_move_cost (enum machine_mode
RCLASS requires an extra scratch register. Return the class needed for the
scratch register. */
-static enum reg_class
-bfin_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
+static reg_class_t
+bfin_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
enum machine_mode mode, secondary_reload_info *sri)
{
/* If we have HImode or QImode, we can only use DREGS as secondary registers;
@@ -2467,6 +2467,7 @@ bfin_secondary_reload (bool in_p, rtx x,
enum reg_class default_class = GET_MODE_SIZE (mode) >= 4 ? DPREGS : DREGS;
enum reg_class x_class = NO_REGS;
enum rtx_code code = GET_CODE (x);
+ enum reg_class rclass = (enum reg_class) rclass_i;
if (code == SUBREG)
x = SUBREG_REG (x), code = GET_CODE (x);
===================================================================
@@ -7507,8 +7507,10 @@ emit_input_reload_insns (struct insn_cha
sri.icode = CODE_FOR_nothing;
sri.prev_sri = NULL;
- new_class = targetm.secondary_reload (1, real_oldequiv, rl->rclass,
- mode, &sri);
+ new_class
+ = (enum reg_class) targetm.secondary_reload (1, real_oldequiv,
+ rl->rclass, mode,
+ &sri);
if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
second_reload_reg = 0;
@@ -7534,8 +7536,10 @@ emit_input_reload_insns (struct insn_cha
{
sri2.icode = CODE_FOR_nothing;
sri2.prev_sri = &sri;
- new_t_class = targetm.secondary_reload (1, real_oldequiv,
- new_class, mode, &sri);
+ new_t_class
+ = (enum reg_class) targetm.secondary_reload (1, real_oldequiv,
+ new_class, mode,
+ &sri);
if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
{
if (reload_adjust_reg_for_temp (&second_reload_reg,