RISC-V: Introduce -mrvv-allow-misalign.

Hi,

this patch changes the default from always enabling movmisalign to
disabling it.  It adds an option to override the default and adds
generic-ooo to the uarchs that support misaligned vector access.

It also adds a check_effective_target_riscv_v_misalign_ok to the
testsuite which enables or disables the vector misalignment tests
depending on whether the target under test can execute a misaligned
vle32.  I haven't actually tested it on a target that does not
support misaligned vector loads, though.

Regtested on rv64gcv_zvfh_zvbb.  There are a few additional
failures in the rvv testsuite.  They are caused by us overwriting
the default vectorizer flags rather than appending.  I'm going to
fix them in a subsequent patch but for now I'd rather get things
rolling.

Regards
 Robin

gcc/ChangeLog:

	* config/riscv/riscv-opts.h (TARGET_VECTOR_MISALIGN_SUPPORTED):
	Move from here...
	* config/riscv/riscv.h (TARGET_VECTOR_MISALIGN_SUPPORTED):
	...to here and make dependent on uarch and rvv_allow_misalign.
	* config/riscv/riscv.opt: Add -mrvv-allow-unaligned.

gcc/testsuite/ChangeLog:

	* lib/target-supports.exp: Add
	check_effective_target_riscv_v_misalign_ok.
---
 gcc/config/riscv/riscv-opts.h         |  3 ---
 gcc/config/riscv/riscv.h              |  5 ++++
 gcc/config/riscv/riscv.opt            |  5 ++++
 gcc/testsuite/lib/target-supports.exp | 34 +++++++++++++++++++++++++--
 4 files changed, 42 insertions(+), 5 deletions(-)

On Fri, 24 May 2024 07:30:20 PDT (-0700), Robin Dapp wrote:
> Hi,
>
> this patch changes the default from always enabling movmisalign to
> disabling it.  It adds an option to override the default and adds
> generic-ooo to the uarchs that support misaligned vector access.
>
> It also adds a check_effective_target_riscv_v_misalign_ok to the
> testsuite which enables or disables the vector misalignment tests
> depending on whether the target under test can execute a misaligned
> vle32.  I haven't actually tested it on a target that does not
> support misaligned vector loads, though.
>
> Regtested on rv64gcv_zvfh_zvbb.  There are a few additional
> failures in the rvv testsuite.  They are caused by us overwriting
> the default vectorizer flags rather than appending.  I'm going to
> fix them in a subsequent patch but for now I'd rather get things
> rolling.
>
> Regards
>  Robin
>
> gcc/ChangeLog:
>
> 	* config/riscv/riscv-opts.h (TARGET_VECTOR_MISALIGN_SUPPORTED):
> 	Move from here...
> 	* config/riscv/riscv.h (TARGET_VECTOR_MISALIGN_SUPPORTED):
> 	...to here and make dependent on uarch and rvv_allow_misalign.
> 	* config/riscv/riscv.opt: Add -mrvv-allow-unaligned.

We should have something in doc/invoke too, this one is going to be 
tricky for users.  We'll also have to define how this interacts with the 
existing -mstrict-align.

> gcc/testsuite/ChangeLog:
>
> 	* lib/target-supports.exp: Add
> 	check_effective_target_riscv_v_misalign_ok.
> ---
>  gcc/config/riscv/riscv-opts.h         |  3 ---
>  gcc/config/riscv/riscv.h              |  5 ++++
>  gcc/config/riscv/riscv.opt            |  5 ++++
>  gcc/testsuite/lib/target-supports.exp | 34 +++++++++++++++++++++++++--
>  4 files changed, 42 insertions(+), 5 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
> index 1b2dd5757a8..f58a07abffc 100644
> --- a/gcc/config/riscv/riscv-opts.h
> +++ b/gcc/config/riscv/riscv-opts.h
> @@ -147,9 +147,6 @@ enum rvv_vector_bits_enum {
>       ? 0                                                                       \
>       : 32 << (__builtin_popcount (opts->x_riscv_zvl_flags) - 1))
>
> -/* TODO: Enable RVV movmisalign by default for now.  */
> -#define TARGET_VECTOR_MISALIGN_SUPPORTED 1
> -
>  /* The maximmum LMUL according to user configuration.  */
>  #define TARGET_MAX_LMUL                                                        \
>    (int) (rvv_max_lmul == RVV_DYNAMIC ? RVV_M8 : rvv_max_lmul)
> diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
> index d6b14c4d620..8434e5677b6 100644
> --- a/gcc/config/riscv/riscv.h
> +++ b/gcc/config/riscv/riscv.h
> @@ -934,6 +934,11 @@ extern enum riscv_cc get_riscv_cc (const rtx use);
>    || (riscv_microarchitecture == sifive_p400) \
>    || (riscv_microarchitecture == sifive_p600))
>
> +/* True if the target supports misaligned vector loads and stores.  */
> +#define TARGET_VECTOR_MISALIGN_SUPPORTED \
> +  (rvv_allow_misalign == 1 \
> +   || riscv_microarchitecture == generic_ooo)

We should probably just stick it in a tune struct instead?  That seems 
cleaner than matching on the exact uarch.

> +
>  #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
>
>  /* Control the assembler format that we output.  */
> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
> index 87f58332016..cff34eee8c9 100644
> --- a/gcc/config/riscv/riscv.opt
> +++ b/gcc/config/riscv/riscv.opt
> @@ -628,3 +628,8 @@ Specify TLS dialect.
>  mfence-tso
>  Target Var(TARGET_FENCE_TSO) Init(1)
>  Specifies whether the fence.tso instruction should be used.
> +
> +mrvv-allow-misalign
> +Target Var(rvv_allow_misalign) Init(0)
> +Allow the creation of misaligned vector loads and stores irrespective of the
> +current uarch. The default is off.

IMO we should be explicit here about these being element-misaligned 
accesses, not register-misaligned accesses.  I don't want to get roped 
into handling register-misaligned accesses under the same flag, that 
would be a whole different flavor of codegen.

> diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
> index f0f6da52275..ebb908f5c8f 100644
> --- a/gcc/testsuite/lib/target-supports.exp
> +++ b/gcc/testsuite/lib/target-supports.exp
> @@ -2034,7 +2034,7 @@ proc check_effective_target_riscv_zvfh_ok { } {
>      # check if we can execute vector insns with the given hardware or
>      # simulator
>      set gcc_march [regsub {[[:alnum:]]*} [riscv_get_arch] &v]
> -    if { [check_runtime ${gcc_march}_exec {
> +    if { [check_runtime ${gcc_march}_zvfh_exec {
>  	int main()
>  	{
>  	    asm ("vsetivli zero,8,e16,m1,ta,ma");
> @@ -2047,6 +2047,29 @@ proc check_effective_target_riscv_zvfh_ok { } {
>      return 0
>  }
>
> +# Return 1 if we can load a vector from a 1-byte aligned address.
> +
> +proc check_effective_target_riscv_v_misalign_ok { } {
> +
> +    if { ![check_effective_target_riscv_v_ok] } {
> +	return 0
> +    }
> +
> +    set gcc_march [riscv_get_arch]
> +    if { [check_runtime ${gcc_march}_misalign_exec {
> +	  int main() {
> +	      unsigned char a[16]
> +		= {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15};
> +	      asm ("vsetivli zero,7,e8,m1,ta,ma");
> +	      asm ("addi a7,%0,1" : : "r" (a) : "a7" );
> +	      asm ("vle8.v v8,0(a7)" : : : "v8");
> +	      return 0; } } "-march=${gcc_march}"] } {
> +	return 1
> +    }
> +
> +    return 0
> +}
> +
>  proc riscv_get_arch { } {
>      set gcc_march ""
>      # ??? do we neeed to add more extensions to the list below?
> @@ -8139,7 +8162,6 @@ proc check_effective_target_vect_hw_misalign { } {
>  	     || ([istarget mips*-*-*] && [et-is-effective-target mips_msa])
>  	     || ([istarget s390*-*-*]
>  		 && [check_effective_target_s390_vx])
> -	     || ([istarget riscv*-*-*])
>  	     || ([istarget loongarch*-*-*])
>  	     || [istarget amdgcn*-*-*] } {
>  	  return 1
> @@ -8148,6 +8170,11 @@ proc check_effective_target_vect_hw_misalign { } {
>  	     && ![check_effective_target_arm_vect_no_misalign] } {
>  	  return 1
>  	}
> +	if { [istarget riscv*-*-*]
> +	     && [check_effective_target_riscv_v_misalign_ok] } {
> +	    return 1
> +	}
> +
>          return 0
>      }]
>  }
> @@ -11565,6 +11592,9 @@ proc check_vect_support_and_set_flags { } {
>      } elseif [istarget riscv*-*-*] {
>  	if [check_effective_target_riscv_v] {
>  	    set dg-do-what-default run
> +	    if [check_effective_target_riscv_v_misalign_ok] {
> +		lappend DEFAULT_VECTCFLAGS "-mrvv-allow-misalign"
> +	    }
>  	} else {
>  	    foreach item [add_options_for_riscv_v ""] {
>  		lappend DEFAULT_VECTCFLAGS $item