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Mon, 20 Mar 2023 06:31:54 +0000 Received: from smtpav06.fra02v.mail.ibm.com (smtpav06.fra02v.mail.ibm.com [10.20.54.105]) by smtprelay03.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 32K6VqlB5374480 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 20 Mar 2023 06:31:52 GMT Received: from smtpav06.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6DFBA2004B; Mon, 20 Mar 2023 06:31:52 +0000 (GMT) Received: from smtpav06.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B2A2C20040; Mon, 20 Mar 2023 06:31:50 +0000 (GMT) Received: from [9.177.11.227] (unknown [9.177.11.227]) by smtpav06.fra02v.mail.ibm.com (Postfix) with ESMTP; Mon, 20 Mar 2023 06:31:50 +0000 (GMT) Message-ID: <1efed6ac-e280-2f1c-15a5-9f13fcb8d6fa@linux.ibm.com> Date: Mon, 20 Mar 2023 14:31:49 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:91.0) Gecko/20100101 Thunderbird/91.6.1 Content-Language: en-US Subject: [PATCH] rs6000: Ensure vec_sld shift count in allowable range [PR109082] To: GCC Patches Cc: Segher Boessenkool , David Edelsohn , Peter Bergner X-TM-AS-GCONF: 00 X-Proofpoint-GUID: p8Ah6kv878gVQ5aQlyiXkGuNQ5uNyUD6 X-Proofpoint-ORIG-GUID: gX5xjLVpRtlne5MBdDlC1JMDkTAr6-i8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-20_03,2023-03-16_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 priorityscore=1501 malwarescore=0 clxscore=1015 impostorscore=0 mlxscore=0 spamscore=0 bulkscore=0 mlxlogscore=923 lowpriorityscore=0 adultscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303150002 definitions=main-2303200053 X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "Kewen.Lin via Gcc-patches" From: "Kewen.Lin" Reply-To: "Kewen.Lin" Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Hi, As PR109082 shows, some uses of vec_sld in emmintrin.h don't strictly guarantee the given shift count is in the range 0-15 (inclusive). This patch is to make the argument range constraint honored for those uses. Bootstrapped and regtested on powerpc64-linux-gnu P8 and powerpc64le-linux-gnu P9 and P10. I'm going to push this soon if no objections. BR, Kewen ----- PR target/109082 gcc/ChangeLog: * config/rs6000/emmintrin.h (_mm_bslli_si128): Check __N is not less than zero when calling vec_sld. (_mm_bsrli_si128): Return __A if __N is zero, check __N is bigger than zero when calling vec_sld. (_mm_slli_si128): Return __A if _imm5 is zero, check _imm5 is bigger than zero when calling vec_sld. gcc/testsuite/ChangeLog: * gcc.target/powerpc/pr109082.c: New test. --- gcc/config/rs6000/emmintrin.h | 10 +++++++--- gcc/testsuite/gcc.target/powerpc/pr109082.c | 14 ++++++++++++++ 2 files changed, 21 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/pr109082.c -- 2.31.1 diff --git a/gcc/config/rs6000/emmintrin.h b/gcc/config/rs6000/emmintrin.h index f6a6dbf399a..bfff7ff6fea 100644 --- a/gcc/config/rs6000/emmintrin.h +++ b/gcc/config/rs6000/emmintrin.h @@ -1601,7 +1601,7 @@ _mm_bslli_si128 (__m128i __A, const int __N) __v16qu __result; const __v16qu __zeros = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; - if (__N < 16) + if (__N >= 0 && __N < 16) __result = vec_sld ((__v16qu) __A, __zeros, __N); else __result = __zeros; @@ -1615,7 +1615,9 @@ _mm_bsrli_si128 (__m128i __A, const int __N) __v16qu __result; const __v16qu __zeros = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; - if (__N < 16) + if (__N == 0) + return __A; + else if (__N > 0 && __N < 16) #ifdef __LITTLE_ENDIAN__ if (__builtin_constant_p(__N)) /* Would like to use Vector Shift Left Double by Octet @@ -1650,7 +1652,9 @@ _mm_slli_si128 (__m128i __A, const int _imm5) __v16qu __result; const __v16qu __zeros = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; - if (_imm5 < 16) + if (_imm5 == 0) + return __A; + else if (_imm5 > 0 && _imm5 < 16) #ifdef __LITTLE_ENDIAN__ __result = vec_sld ((__v16qu) __A, __zeros, _imm5); #else diff --git a/gcc/testsuite/gcc.target/powerpc/pr109082.c b/gcc/testsuite/gcc.target/powerpc/pr109082.c new file mode 100644 index 00000000000..98da22c386b --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr109082.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mvsx" } */ + +/* Verify there is no warning message. */ + +#define NO_WARN_X86_INTRINSICS 1 +#include + +__m128i +foo (__m128i A) +{ + return _mm_bsrli_si128 (A, 0); +}