diff mbox series

[2/9] arm: MVE: Cleanup vcmpne/vcmpeq builtins

Message ID 1619791790-628-2-git-send-email-christophe.lyon@linaro.org
State New
Headers show
Series [1/9] arm: MVE: Convert vcmp[eq|ne]* in arm_mve.h to use only 's' builtin version | expand

Commit Message

Christophe Lyon April 30, 2021, 2:09 p.m. UTC 
After the previous patch, we no longer need to emit the unsigned
variants of vcmpneq/vcmpeqq. This patch removes them as well as the
corresponding iterator entries.

2021-03-01  Christophe Lyon  <christophe.lyon@linaro.org>

	gcc/
	* config/arm/arm_mve_builtins.def (vcmpneq_u): Remove.
	(vcmpneq_n_u): Likewise.
	(vcmpeqq_u,): Likewise.
	(vcmpeqq_n_u): Likewise.
	* config/arm/iterators.md (supf): Remove VCMPNEQ_U, VCMPEQQ_U,
	VCMPEQQ_N_U and VCMPNEQ_N_U.
	* config/arm/mve.md (mve_vcmpneq): Remove <supf> iteration.
	(mve_vcmpeqq_n): Likewise.
	(mve_vcmpeqq): Likewise.
	(mve_vcmpneq_n): Likewise.

arm_mve_builtins.def: Remove vcmpneq_u, vcmpneq_n_u, vcmpeqq_u, vcmpeqq_n_u.
iterators.md: Update VCMPNEQ VCMPEQQ VCMPEQQ_N VCMPNEQ_N
mve.md: Remove vcmpneq_s vcmpeqq_n_u vcmpeqq_u, vcmpneq_n_u,
---
 gcc/config/arm/arm_mve_builtins.def |  4 ----
 gcc/config/arm/iterators.md         | 15 +++++++--------
 gcc/config/arm/mve.md               | 16 ++++++++--------
 3 files changed, 15 insertions(+), 20 deletions(-)

Comments

Kyrylo Tkachov May 10, 2021, 11:57 a.m. UTC | #1 
> -----Original Message-----
> From: Gcc-patches <gcc-patches-bounces@gcc.gnu.org> On Behalf Of
> Christophe Lyon via Gcc-patches
> Sent: 30 April 2021 15:10
> To: gcc-patches@gcc.gnu.org
> Subject: [PATCH 2/9] arm: MVE: Cleanup vcmpne/vcmpeq builtins
> 
> After the previous patch, we no longer need to emit the unsigned
> variants of vcmpneq/vcmpeqq. This patch removes them as well as the
> corresponding iterator entries.

Ok.
Thanks,
Kyrill

> 
> 2021-03-01  Christophe Lyon  <christophe.lyon@linaro.org>
> 
> 	gcc/
> 	* config/arm/arm_mve_builtins.def (vcmpneq_u): Remove.
> 	(vcmpneq_n_u): Likewise.
> 	(vcmpeqq_u,): Likewise.
> 	(vcmpeqq_n_u): Likewise.
> 	* config/arm/iterators.md (supf): Remove VCMPNEQ_U,
> VCMPEQQ_U,
> 	VCMPEQQ_N_U and VCMPNEQ_N_U.
> 	* config/arm/mve.md (mve_vcmpneq): Remove <supf> iteration.
> 	(mve_vcmpeqq_n): Likewise.
> 	(mve_vcmpeqq): Likewise.
> 	(mve_vcmpneq_n): Likewise.
> 
> arm_mve_builtins.def: Remove vcmpneq_u, vcmpneq_n_u, vcmpeqq_u,
> vcmpeqq_n_u.
> iterators.md: Update VCMPNEQ VCMPEQQ VCMPEQQ_N VCMPNEQ_N
> mve.md: Remove vcmpneq_s vcmpeqq_n_u vcmpeqq_u, vcmpneq_n_u,
> ---
>  gcc/config/arm/arm_mve_builtins.def |  4 ----
>  gcc/config/arm/iterators.md         | 15 +++++++--------
>  gcc/config/arm/mve.md               | 16 ++++++++--------
>  3 files changed, 15 insertions(+), 20 deletions(-)
> 
> diff --git a/gcc/config/arm/arm_mve_builtins.def
> b/gcc/config/arm/arm_mve_builtins.def
> index 460f6ba..ee34fd1 100644
> --- a/gcc/config/arm/arm_mve_builtins.def
> +++ b/gcc/config/arm/arm_mve_builtins.def
> @@ -90,7 +90,6 @@ VAR3 (BINOP_NONE_NONE_IMM, vshrq_n_s, v16qi,
> v8hi, v4si)
>  VAR1 (BINOP_NONE_NONE_UNONE, vaddlvq_p_s, v4si)
>  VAR1 (BINOP_UNONE_UNONE_UNONE, vaddlvq_p_u, v4si)
>  VAR3 (BINOP_UNONE_NONE_NONE, vcmpneq_s, v16qi, v8hi, v4si)
> -VAR3 (BINOP_UNONE_UNONE_UNONE, vcmpneq_u, v16qi, v8hi, v4si)
>  VAR3 (BINOP_NONE_NONE_NONE, vshlq_s, v16qi, v8hi, v4si)
>  VAR3 (BINOP_UNONE_UNONE_NONE, vshlq_u, v16qi, v8hi, v4si)
>  VAR3 (BINOP_UNONE_UNONE_UNONE, vsubq_u, v16qi, v8hi, v4si)
> @@ -118,11 +117,8 @@ VAR3 (BINOP_UNONE_UNONE_UNONE,
> vhsubq_n_u, v16qi, v8hi, v4si)
>  VAR3 (BINOP_UNONE_UNONE_UNONE, vhaddq_u, v16qi, v8hi, v4si)
>  VAR3 (BINOP_UNONE_UNONE_UNONE, vhaddq_n_u, v16qi, v8hi, v4si)
>  VAR3 (BINOP_UNONE_UNONE_UNONE, veorq_u, v16qi, v8hi, v4si)
> -VAR3 (BINOP_UNONE_UNONE_UNONE, vcmpneq_n_u, v16qi, v8hi, v4si)
>  VAR3 (BINOP_UNONE_UNONE_UNONE, vcmphiq_u, v16qi, v8hi, v4si)
>  VAR3 (BINOP_UNONE_UNONE_UNONE, vcmphiq_n_u, v16qi, v8hi, v4si)
> -VAR3 (BINOP_UNONE_UNONE_UNONE, vcmpeqq_u, v16qi, v8hi, v4si)
> -VAR3 (BINOP_UNONE_UNONE_UNONE, vcmpeqq_n_u, v16qi, v8hi, v4si)
>  VAR3 (BINOP_UNONE_UNONE_UNONE, vcmpcsq_u, v16qi, v8hi, v4si)
>  VAR3 (BINOP_UNONE_UNONE_UNONE, vcmpcsq_n_u, v16qi, v8hi, v4si)
>  VAR3 (BINOP_UNONE_UNONE_UNONE, vbicq_u, v16qi, v8hi, v4si)
> diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
> index 8fb723e..0aba93f 100644
> --- a/gcc/config/arm/iterators.md
> +++ b/gcc/config/arm/iterators.md
> @@ -1279,13 +1279,12 @@ (define_int_attr supf [(VCVTQ_TO_F_S "s")
> (VCVTQ_TO_F_U "u") (VREV16Q_S "s")
>  		       (VCREATEQ_U "u") (VCREATEQ_S "s") (VSHRQ_N_S "s")
>  		       (VSHRQ_N_U "u") (VCVTQ_N_FROM_F_S "s") (VSHLQ_U
> "u")
>  		       (VCVTQ_N_FROM_F_U "u") (VADDLVQ_P_S "s")
> (VSHLQ_S "s")
> -		       (VADDLVQ_P_U "u") (VCMPNEQ_U "u") (VCMPNEQ_S "s")
> +		       (VADDLVQ_P_U "u") (VCMPNEQ_S "s")
>  		       (VABDQ_M_S "s") (VABDQ_M_U "u") (VABDQ_S "s")
>  		       (VABDQ_U "u") (VADDQ_N_S "s") (VADDQ_N_U "u")
>  		       (VADDVQ_P_S "s")	(VADDVQ_P_U "u") (VBRSRQ_N_S "s")
> -		       (VBRSRQ_N_U "u") (VCMPEQQ_S "s") (VCMPEQQ_U "u")
> -		       (VCMPEQQ_N_S "s") (VCMPEQQ_N_U "u")
> (VCMPNEQ_N_S "s")
> -		       (VCMPNEQ_N_U "u")
> +		       (VBRSRQ_N_U "u") (VCMPEQQ_S "s")
> +		       (VCMPEQQ_N_S "s") (VCMPNEQ_N_S "s")
>  		       (VHADDQ_N_S "s") (VHADDQ_N_U "u") (VHADDQ_S "s")
>  		       (VHADDQ_U "u") (VHSUBQ_N_S "s")
> 	(VHSUBQ_N_U "u")
>  		       (VHSUBQ_S "s") (VMAXQ_S "s") (VMAXQ_U "u")
> (VHSUBQ_U "u")
> @@ -1541,16 +1540,16 @@ (define_int_iterator VCREATEQ [VCREATEQ_U
> VCREATEQ_S])
>  (define_int_iterator VSHRQ_N [VSHRQ_N_S VSHRQ_N_U])
>  (define_int_iterator VCVTQ_N_FROM_F [VCVTQ_N_FROM_F_S
> VCVTQ_N_FROM_F_U])
>  (define_int_iterator VADDLVQ_P [VADDLVQ_P_S VADDLVQ_P_U])
> -(define_int_iterator VCMPNEQ [VCMPNEQ_U VCMPNEQ_S])
> +(define_int_iterator VCMPNEQ [VCMPNEQ_S])
>  (define_int_iterator VSHLQ [VSHLQ_S VSHLQ_U])
>  (define_int_iterator VABDQ [VABDQ_S VABDQ_U])
>  (define_int_iterator VADDQ_N [VADDQ_N_S VADDQ_N_U])
>  (define_int_iterator VADDVAQ [VADDVAQ_S VADDVAQ_U])
>  (define_int_iterator VADDVQ_P [VADDVQ_P_U VADDVQ_P_S])
>  (define_int_iterator VBRSRQ_N [VBRSRQ_N_U VBRSRQ_N_S])
> -(define_int_iterator VCMPEQQ [VCMPEQQ_U VCMPEQQ_S])
> -(define_int_iterator VCMPEQQ_N [VCMPEQQ_N_S VCMPEQQ_N_U])
> -(define_int_iterator VCMPNEQ_N [VCMPNEQ_N_U VCMPNEQ_N_S])
> +(define_int_iterator VCMPEQQ [VCMPEQQ_S])
> +(define_int_iterator VCMPEQQ_N [VCMPEQQ_N_S])
> +(define_int_iterator VCMPNEQ_N [VCMPNEQ_N_S])
>  (define_int_iterator VHADDQ [VHADDQ_S VHADDQ_U])
>  (define_int_iterator VHADDQ_N [VHADDQ_N_U VHADDQ_N_S])
>  (define_int_iterator VHSUBQ [VHSUBQ_S VHSUBQ_U])
> diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
> index 7467d5f..b04c22b 100644
> --- a/gcc/config/arm/mve.md
> +++ b/gcc/config/arm/mve.md
> @@ -836,9 +836,9 @@ (define_insn "mve_vaddlvq_p_<supf>v4si"
>     (set_attr "length""8")])
> 
>  ;;
> -;; [vcmpneq_u, vcmpneq_s])
> +;; [vcmpneq_s])
>  ;;
> -(define_insn "mve_vcmpneq_<supf><mode>"
> +(define_insn "mve_vcmpneq_s<mode>"
>    [
>     (set (match_operand:HI 0 "vpr_register_operand" "=Up")
>  	(unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
> @@ -1035,9 +1035,9 @@ (define_insn "mve_vcmpcsq_u<mode>"
>  ])
> 
>  ;;
> -;; [vcmpeqq_n_s, vcmpeqq_n_u])
> +;; [vcmpeqq_n_s])
>  ;;
> -(define_insn "mve_vcmpeqq_n_<supf><mode>"
> +(define_insn "mve_vcmpeqq_n_s<mode>"
>    [
>     (set (match_operand:HI 0 "vpr_register_operand" "=Up")
>  	(unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
> @@ -1050,9 +1050,9 @@ (define_insn "mve_vcmpeqq_n_<supf><mode>"
>  ])
> 
>  ;;
> -;; [vcmpeqq_u, vcmpeqq_s])
> +;; [vcmpeqq_s])
>  ;;
> -(define_insn "mve_vcmpeqq_<supf><mode>"
> +(define_insn "mve_vcmpeqq_s<mode>"
>    [
>     (set (match_operand:HI 0 "vpr_register_operand" "=Up")
>  	(unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
> @@ -1215,9 +1215,9 @@ (define_insn "mve_vcmpltq_s<mode>"
>  ])
> 
>  ;;
> -;; [vcmpneq_n_u, vcmpneq_n_s])
> +;; [vcmpneq_n_s])
>  ;;
> -(define_insn "mve_vcmpneq_n_<supf><mode>"
> +(define_insn "mve_vcmpneq_n_s<mode>"
>    [
>     (set (match_operand:HI 0 "vpr_register_operand" "=Up")
>  	(unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
> --
> 2.7.4
diff mbox series

Patch

diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def
index 460f6ba..ee34fd1 100644
--- a/gcc/config/arm/arm_mve_builtins.def
+++ b/gcc/config/arm/arm_mve_builtins.def
@@ -90,7 +90,6 @@  VAR3 (BINOP_NONE_NONE_IMM, vshrq_n_s, v16qi, v8hi, v4si)
 VAR1 (BINOP_NONE_NONE_UNONE, vaddlvq_p_s, v4si)
 VAR1 (BINOP_UNONE_UNONE_UNONE, vaddlvq_p_u, v4si)
 VAR3 (BINOP_UNONE_NONE_NONE, vcmpneq_s, v16qi, v8hi, v4si)
-VAR3 (BINOP_UNONE_UNONE_UNONE, vcmpneq_u, v16qi, v8hi, v4si)
 VAR3 (BINOP_NONE_NONE_NONE, vshlq_s, v16qi, v8hi, v4si)
 VAR3 (BINOP_UNONE_UNONE_NONE, vshlq_u, v16qi, v8hi, v4si)
 VAR3 (BINOP_UNONE_UNONE_UNONE, vsubq_u, v16qi, v8hi, v4si)
@@ -118,11 +117,8 @@  VAR3 (BINOP_UNONE_UNONE_UNONE, vhsubq_n_u, v16qi, v8hi, v4si)
 VAR3 (BINOP_UNONE_UNONE_UNONE, vhaddq_u, v16qi, v8hi, v4si)
 VAR3 (BINOP_UNONE_UNONE_UNONE, vhaddq_n_u, v16qi, v8hi, v4si)
 VAR3 (BINOP_UNONE_UNONE_UNONE, veorq_u, v16qi, v8hi, v4si)
-VAR3 (BINOP_UNONE_UNONE_UNONE, vcmpneq_n_u, v16qi, v8hi, v4si)
 VAR3 (BINOP_UNONE_UNONE_UNONE, vcmphiq_u, v16qi, v8hi, v4si)
 VAR3 (BINOP_UNONE_UNONE_UNONE, vcmphiq_n_u, v16qi, v8hi, v4si)
-VAR3 (BINOP_UNONE_UNONE_UNONE, vcmpeqq_u, v16qi, v8hi, v4si)
-VAR3 (BINOP_UNONE_UNONE_UNONE, vcmpeqq_n_u, v16qi, v8hi, v4si)
 VAR3 (BINOP_UNONE_UNONE_UNONE, vcmpcsq_u, v16qi, v8hi, v4si)
 VAR3 (BINOP_UNONE_UNONE_UNONE, vcmpcsq_n_u, v16qi, v8hi, v4si)
 VAR3 (BINOP_UNONE_UNONE_UNONE, vbicq_u, v16qi, v8hi, v4si)
diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index 8fb723e..0aba93f 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -1279,13 +1279,12 @@  (define_int_attr supf [(VCVTQ_TO_F_S "s") (VCVTQ_TO_F_U "u") (VREV16Q_S "s")
 		       (VCREATEQ_U "u") (VCREATEQ_S "s") (VSHRQ_N_S "s")
 		       (VSHRQ_N_U "u") (VCVTQ_N_FROM_F_S "s") (VSHLQ_U "u")
 		       (VCVTQ_N_FROM_F_U "u") (VADDLVQ_P_S "s") (VSHLQ_S "s")
-		       (VADDLVQ_P_U "u") (VCMPNEQ_U "u") (VCMPNEQ_S "s")
+		       (VADDLVQ_P_U "u") (VCMPNEQ_S "s")
 		       (VABDQ_M_S "s") (VABDQ_M_U "u") (VABDQ_S "s")
 		       (VABDQ_U "u") (VADDQ_N_S "s") (VADDQ_N_U "u")
 		       (VADDVQ_P_S "s")	(VADDVQ_P_U "u") (VBRSRQ_N_S "s")
-		       (VBRSRQ_N_U "u") (VCMPEQQ_S "s") (VCMPEQQ_U "u")
-		       (VCMPEQQ_N_S "s") (VCMPEQQ_N_U "u") (VCMPNEQ_N_S "s")
-		       (VCMPNEQ_N_U "u")
+		       (VBRSRQ_N_U "u") (VCMPEQQ_S "s")
+		       (VCMPEQQ_N_S "s") (VCMPNEQ_N_S "s")
 		       (VHADDQ_N_S "s") (VHADDQ_N_U "u") (VHADDQ_S "s")
 		       (VHADDQ_U "u") (VHSUBQ_N_S "s")	(VHSUBQ_N_U "u")
 		       (VHSUBQ_S "s") (VMAXQ_S "s") (VMAXQ_U "u") (VHSUBQ_U "u")
@@ -1541,16 +1540,16 @@  (define_int_iterator VCREATEQ [VCREATEQ_U VCREATEQ_S])
 (define_int_iterator VSHRQ_N [VSHRQ_N_S VSHRQ_N_U])
 (define_int_iterator VCVTQ_N_FROM_F [VCVTQ_N_FROM_F_S VCVTQ_N_FROM_F_U])
 (define_int_iterator VADDLVQ_P [VADDLVQ_P_S VADDLVQ_P_U])
-(define_int_iterator VCMPNEQ [VCMPNEQ_U VCMPNEQ_S])
+(define_int_iterator VCMPNEQ [VCMPNEQ_S])
 (define_int_iterator VSHLQ [VSHLQ_S VSHLQ_U])
 (define_int_iterator VABDQ [VABDQ_S VABDQ_U])
 (define_int_iterator VADDQ_N [VADDQ_N_S VADDQ_N_U])
 (define_int_iterator VADDVAQ [VADDVAQ_S VADDVAQ_U])
 (define_int_iterator VADDVQ_P [VADDVQ_P_U VADDVQ_P_S])
 (define_int_iterator VBRSRQ_N [VBRSRQ_N_U VBRSRQ_N_S])
-(define_int_iterator VCMPEQQ [VCMPEQQ_U VCMPEQQ_S])
-(define_int_iterator VCMPEQQ_N [VCMPEQQ_N_S VCMPEQQ_N_U])
-(define_int_iterator VCMPNEQ_N [VCMPNEQ_N_U VCMPNEQ_N_S])
+(define_int_iterator VCMPEQQ [VCMPEQQ_S])
+(define_int_iterator VCMPEQQ_N [VCMPEQQ_N_S])
+(define_int_iterator VCMPNEQ_N [VCMPNEQ_N_S])
 (define_int_iterator VHADDQ [VHADDQ_S VHADDQ_U])
 (define_int_iterator VHADDQ_N [VHADDQ_N_U VHADDQ_N_S])
 (define_int_iterator VHSUBQ [VHSUBQ_S VHSUBQ_U])
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 7467d5f..b04c22b 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -836,9 +836,9 @@  (define_insn "mve_vaddlvq_p_<supf>v4si"
    (set_attr "length""8")])
 
 ;;
-;; [vcmpneq_u, vcmpneq_s])
+;; [vcmpneq_s])
 ;;
-(define_insn "mve_vcmpneq_<supf><mode>"
+(define_insn "mve_vcmpneq_s<mode>"
   [
    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
 	(unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
@@ -1035,9 +1035,9 @@  (define_insn "mve_vcmpcsq_u<mode>"
 ])
 
 ;;
-;; [vcmpeqq_n_s, vcmpeqq_n_u])
+;; [vcmpeqq_n_s])
 ;;
-(define_insn "mve_vcmpeqq_n_<supf><mode>"
+(define_insn "mve_vcmpeqq_n_s<mode>"
   [
    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
 	(unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
@@ -1050,9 +1050,9 @@  (define_insn "mve_vcmpeqq_n_<supf><mode>"
 ])
 
 ;;
-;; [vcmpeqq_u, vcmpeqq_s])
+;; [vcmpeqq_s])
 ;;
-(define_insn "mve_vcmpeqq_<supf><mode>"
+(define_insn "mve_vcmpeqq_s<mode>"
   [
    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
 	(unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
@@ -1215,9 +1215,9 @@  (define_insn "mve_vcmpltq_s<mode>"
 ])
 
 ;;
-;; [vcmpneq_n_u, vcmpneq_n_s])
+;; [vcmpneq_n_s])
 ;;
-(define_insn "mve_vcmpneq_n_<supf><mode>"
+(define_insn "mve_vcmpneq_n_s<mode>"
   [
    (set (match_operand:HI 0 "vpr_register_operand" "=Up")
 	(unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")