From patchwork Thu Nov 8 17:03:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Renlin Li X-Patchwork-Id: 995034 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-489422-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=foss.arm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="Dm/zSKS/"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42rV4B5mJ1z9sBN for ; Fri, 9 Nov 2018 04:03:53 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :subject:to:message-id:date:mime-version:content-type; q=dns; s= default; b=aMylq+EJs4P5dAUPXn21Zys6pVubj/UjOvUjqp7GemYyr/d6qtYVM 0YBUdVSxkl6gNIf4wtdSApAhPZFFoEbf65uiSLbmsx+nJ67eHuU36SWDRfw2Mh/H aztKEy9fwfhI1oRHYQ1OH5f5c9cfHzYK8i6135PO1us/TMhruo707o= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :subject:to:message-id:date:mime-version:content-type; s= default; bh=84pJ+ejRKT2kdsy6ZK+7aD3DN4s=; b=Dm/zSKS/Jk3ETrEDoPoU GLPjaGSCaY50eamV84T6NbqNMUC/kHhtYSQRbOhUSU1diQ6rSy16xAkYqlgNObUs 67jtp2YZuzwvruJUlqN+HsVb8OAVs7GvfEgqDYDJn+MxUp2n98Y4tjw9EokwALOD vNvSEgjxZLY0ObKd2ucMHDs= Received: (qmail 116951 invoked by alias); 8 Nov 2018 17:03:46 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 116937 invoked by uid 89); 8 Nov 2018 17:03:45 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-24.8 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, KAM_LAZY_DOMAIN_SECURITY, KAM_LOTSOFHASH, KAM_SHORT autolearn=ham version=3.3.2 spammy= X-HELO: foss.arm.com Received: from usa-sjc-mx-foss1.foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 08 Nov 2018 17:03:44 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 708201596; Thu, 8 Nov 2018 09:03:42 -0800 (PST) Received: from [10.2.206.82] (e109742-lin.cambridge.arm.com [10.2.206.82]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 81F553F5CF; Thu, 8 Nov 2018 09:03:41 -0800 (PST) From: Renlin Li Subject: [AARCH64][SVE]Add extract_last for mask/predicates mode register To: "gcc-patches@gcc.gnu.org" , Richard Sandiford , James Greenhalgh , Ramana Radhakrishnan , "law@redhat.com" Message-ID: <153133c9-4e28-8cfc-9eb7-38568ffed7ab@foss.arm.com> Date: Thu, 8 Nov 2018 17:03:39 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 MIME-Version: 1.0 X-IsSubscribed: yes Hi all, As a follow up patch described here: https://gcc.gnu.org/ml/gcc-patches/2018-10/msg02016.html Mask/predicate type of data could be used as general data. In sve ISA, we don't have operations which could directly extract element from a predicate. The default code-gen for such use is in-efficient, it use memory to reload the predicate into a scalar GPR. Here, an EXTRACT_LAST pattern is added to support mask mode. So that, EXTRACT_LAST (mask_1, mask_2) will expands to is: mov Z0, mask_2, 1 lastb W0, mask_1, Z0 aarch64-sve test Okay. Okay to commit? There might be more cases need to be discovered/fixed. Regards, Renlin gcc/ChangeLog: 2018-11-08 Renlin Li * config/aarch64/aarch64-sve.md (extract_last): Add new modes. * config/aarch64/iterators.md (PREDV): predicate mode to vector mode mapping. (predv): Likewise, lower case. gcc/testsuite/ChangeLog: 2018-11-08 Renlin Li * gcc.target/aarch64/sve/pr87815.c: Update. diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index 5cd591b94335cde2230decf632f65c0faf33c4de..0550a2bd4b1b552159fad298342876afdd34303b 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -615,6 +615,28 @@ lastb\t%0, %1, %2." ) +(define_insn_and_split "extract_last_" + [(set (match_operand: 0 "register_operand" "=r") + (unspec: + [(match_operand:PRED_ALL 1 "register_operand" "Upl") + (match_operand:PRED_ALL 2 "register_operand" "Upl")] + UNSPEC_LASTB)) + (clobber (match_scratch: 3 "=w"))] + "TARGET_SVE" + "#" + "&& true" + [(const_int 0)] + { + if (GET_CODE (operands[3]) == SCRATCH) + operands[3] = gen_reg_rtx (mode); + emit_insn (gen_aarch64_sve_dup_const (operands[3], operands[2], + CONST1_RTX (mode), + CONST0_RTX (mode))); + emit_insn (gen_extract_last_ (operands[0], operands[1], operands[3])); + DONE; + } +) + (define_expand "vec_duplicate" [(parallel [(set (match_operand:SVE_ALL 0 "register_operand") diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index a43956054e82aaf651fb45d0ff254b248c02c644..3f01c0f611173f9cdfcc150fc6c88141e7b7ebf8 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -698,8 +698,10 @@ (V4HF "HF") (V8HF "HF") (VNx8HF "HF") (V2SF "SF") (V4SF "SF") (VNx4SF "SF") (DF "DF") (V2DF "DF") (VNx2DF "DF") - (SI "SI") (HI "HI") - (QI "QI")]) + (SI "SI") (VNx16BI "QI") + (HI "HI") (VNx8BI "HI") + (QI "QI") (VNx4BI "SI") + (VNx2BI "DI")]) ;; Define element mode for each vector mode (lower case). (define_mode_attr Vel [(V8QI "qi") (V16QI "qi") (VNx16QI "qi") @@ -1134,6 +1136,12 @@ (VNx16SI "vnx4bi") (VNx16SF "vnx4bi") (VNx8DI "vnx2bi") (VNx8DF "vnx2bi")]) +(define_mode_attr PREDV [(VNx16BI "VNx16QI") (VNx8BI "VNx8HI") + (VNx4BI "VNx4SI") (VNx2BI "VNx2DI")]) + +(define_mode_attr predv [(VNx16BI "vnx16qi") (VNx8BI "vnx8hi") + (VNx4BI "vnx4si") (VNx2BI "vnx2di")]) + ;; ------------------------------------------------------------------- ;; Code Iterators ;; ------------------------------------------------------------------- diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr87815.c b/gcc/testsuite/gcc.target/aarch64/sve/pr87815.c index 628cedb2acce82a86b61944eb6184d7fdbb2d656..82e73a8211a1f84d799be6f3f9137e296c59792c 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pr87815.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pr87815.c @@ -1,5 +1,5 @@ -/* { dg-do compile { target aarch64_asm_sve_ok } } */ -/* { dg-options "-O3" } */ +/* { dg-do compile } */ +/* { dg-options "-O3 -fdump-tree-vect" } */ int a, b, d; short e; @@ -11,3 +11,6 @@ void f () d = e && b; } } + +/* { dg-final { scan-tree-dump-times "EXTRACT_LAST" 1 "vect" } } */ +/* { dg-final { scan-assembler-times {lastb} 1 } } */