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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Thu, 7 Jun 2018 17:10:10 -0600 Received: from b03ledav005.gho.boulder.ibm.com (b03ledav005.gho.boulder.ibm.com [9.17.130.236]) by b03cxnp08025.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w57NA9ho37093622 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 7 Jun 2018 16:10:09 -0700 Received: from b03ledav005.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8ECBFBE04F; Thu, 7 Jun 2018 17:10:09 -0600 (MDT) Received: from b03ledav005.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 1D08CBE053; Thu, 7 Jun 2018 17:10:09 -0600 (MDT) Received: from oc3304648336.ibm.com (unknown [9.70.82.186]) by b03ledav005.gho.boulder.ibm.com (Postfix) with ESMTP; Thu, 7 Jun 2018 17:10:08 -0600 (MDT) Subject: [PATCH, rs6000] Cleanup vsx-vector-6 test files. From: Carl Love To: Segher Boessenkool , gcc-patches@gcc.gnu.org, David Edelsohn Cc: Bill Schmidt , cel@us.ibm.com, seurer@linux.vnet.ibm.com Date: Thu, 07 Jun 2018 16:10:08 -0700 Mime-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 18060723-8235-0000-0000-00000DB270D2 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00009148; HX=3.00000241; KW=3.00000007; PH=3.00000004; SC=3.00000265; SDB=6.01043701; UDB=6.00534412; IPR=6.00822781; MB=3.00021521; MTD=3.00000008; XFM=3.00000015; UTC=2018-06-07 23:10:12 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18060723-8236-0000-0000-00004168593B Message-Id: <1528413008.4981.33.camel@us.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-06-07_11:, , signatures=0 X-IsSubscribed: yes GCC Maintainers: The test files gcc/testsuite/gcc.target/powerpc/vsx-vector- 6[be|le].[p7|p8|p9].c cover testing for LE and BE for the various processors. These were setup before we had the le and be targets. Given that we now have the be and le targets the test files can be combined into a single file with the be and le qualifiers attached to the various instruction count checks. This reduces the number of files that need to be maintained. This patch removes the endian specific string in the test file name and combines the BE and LE versions for Power 8 into a single file. The patch was retested on:     powerpc64le-unknown-linux-gnu (Power 8 LE)        powerpc64le-unknown-linux-gnu (Power 9 LE)     powerpc64-unknown-linux-gnu (Power 8 BE) With no regressions. Please let me know if the patch looks OK for GCC mainline.                          Carl Love ------------------------------------------------------------- gcc/testsuite/ChangeLog: 2018-06-07 Carl Love * gcc.target/powerpc/vsx-vector-6-be.p7.c: Rename vsx-vector-6.p7.c. * gcc.target/powerpc/vsx-vector-6-le.p9.c: Rename vsx-vector-6.p9.c. * gcc.target/powerpc/vsx-vector-6-be.p8.c: Delete file. * gcc.target/powerpc/vsx-vector-6-le.c: Rename vsx-vector-6.p8.c. Add le and be qualifiers for instruction counts. --- .../gcc.target/powerpc/vsx-vector-6-be.p7.c | 43 ----------------- .../gcc.target/powerpc/vsx-vector-6-be.p8.c | 43 ----------------- gcc/testsuite/gcc.target/powerpc/vsx-vector-6-le.c | 47 ------------------ .../gcc.target/powerpc/vsx-vector-6-le.p9.c | 37 --------------- gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p7.c | 50 ++++++++++++++++++++ gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p8.c | 55 ++++++++++++++++++++++ gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p9.c | 39 +++++++++++++++ 7 files changed, 144 insertions(+), 170 deletions(-) delete mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6-be.p7.c delete mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6-be.p8.c delete mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6-le.c delete mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6-le.p9.c create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p7.c create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p8.c create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p9.c diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-be.p7.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-be.p7.c deleted file mode 100644 index 835b24f..0000000 --- a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-be.p7.c +++ /dev/null @@ -1,43 +0,0 @@ -/* { dg-do compile { target { powerpc64-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_vsx_ok } */ -/* { dg-options "-mvsx -O2 -mcpu=power7" } */ -/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ - - -/* Expected instruction counts for Big Endian */ - -/* { dg-final { scan-assembler-times "xvabsdp" 1 } } */ -/* { dg-final { scan-assembler-times "xvadddp" 1 } } */ -/* { dg-final { scan-assembler-times "xxlnor" 7 } } */ -/* { dg-final { scan-assembler-times "xvcmpeqdp" 6 } } */ -/* { dg-final { scan-assembler-times "xvcmpeqdp." 6 } } */ -/* { dg-final { scan-assembler-times "xvcmpgtdp" 8 } } */ -/* { dg-final { scan-assembler-times "xvcmpgtdp." 8 } } */ -/* { dg-final { scan-assembler-times "xvcmpgedp" 7 } } */ -/* { dg-final { scan-assembler-times "xvcmpgedp." 7 } } */ -/* { dg-final { scan-assembler-times "xvrdpim" 1 } } */ -/* { dg-final { scan-assembler-times "xvmaddadp" 1 } } */ -/* { dg-final { scan-assembler-times "xvmsubadp" 1 } } */ -/* { dg-final { scan-assembler-times "xvsubdp" 1 } } */ -/* { dg-final { scan-assembler-times "xvmaxdp" 1 } } */ -/* { dg-final { scan-assembler-times "xvmindp" 1 } } */ -/* { dg-final { scan-assembler-times "xvmuldp" 1 } } */ -/* { dg-final { scan-assembler-times "vperm" 1 } } */ -/* { dg-final { scan-assembler-times "xvrdpic" 1 } } */ -/* { dg-final { scan-assembler-times "xvsqrtdp" 1 } } */ -/* { dg-final { scan-assembler-times "xvrdpiz" 1 } } */ -/* { dg-final { scan-assembler-times "xvmsubasp" 1 } } */ -/* { dg-final { scan-assembler-times "xvnmaddasp" 1 } } */ -/* { dg-final { scan-assembler-times "xvnmaddadp" 1 } } */ -/* { dg-final { scan-assembler-times "xvnmsubadp" 1 } } */ -/* { dg-final { scan-assembler-times "vmsumshs" 1 } } */ -/* { dg-final { scan-assembler-times "xxland" 13 } } */ -/* { dg-final { scan-assembler-times "xxlxor" 2 } } */ -/* { dg-final { scan-assembler-times "xxsel" 2 } } */ -/* { dg-final { scan-assembler-times "xvrdpip" 1 } } */ -/* { dg-final { scan-assembler-times "xvdivdp" 1 } } */ -/* { dg-final { scan-assembler-times "xvrdpi" 5 } } */ - -/* Source code for the test in vsx-vector-6.h */ -#include "vsx-vector-6.h" diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-be.p8.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-be.p8.c deleted file mode 100644 index 3b81df8..0000000 --- a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-be.p8.c +++ /dev/null @@ -1,43 +0,0 @@ -/* { dg-do compile { target { powerpc64-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_vsx_ok } */ -/* { dg-options "-mvsx -O2 -mcpu=power8" } */ -/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ - - -/* Expected instruction counts for Big Endian */ - -/* { dg-final { scan-assembler-times "xvabsdp" 1 } } */ -/* { dg-final { scan-assembler-times "xvadddp" 1 } } */ -/* { dg-final { scan-assembler-times "xxlnor" 7 } } */ -/* { dg-final { scan-assembler-times "xvcmpeqdp" 6 } } */ -/* { dg-final { scan-assembler-times "xvcmpeqdp." 6 } } */ -/* { dg-final { scan-assembler-times "xvcmpgtdp" 8 } } */ -/* { dg-final { scan-assembler-times "xvcmpgtdp." 8 } } */ -/* { dg-final { scan-assembler-times "xvcmpgedp" 7 } } */ -/* { dg-final { scan-assembler-times "xvcmpgedp." 7 } } */ -/* { dg-final { scan-assembler-times "xvrdpim" 1 } } */ -/* { dg-final { scan-assembler-times "xvmaddadp" 1 } } */ -/* { dg-final { scan-assembler-times "xvmsubadp" 1 } } */ -/* { dg-final { scan-assembler-times "xvsubdp" 1 } } */ -/* { dg-final { scan-assembler-times "xvmaxdp" 1 } } */ -/* { dg-final { scan-assembler-times "xvmindp" 1 } } */ -/* { dg-final { scan-assembler-times "xvmuldp" 1 } } */ -/* { dg-final { scan-assembler-times "vperm" 1 } } */ -/* { dg-final { scan-assembler-times "xvrdpic" 1 } } */ -/* { dg-final { scan-assembler-times "xvsqrtdp" 1 } } */ -/* { dg-final { scan-assembler-times "xvrdpiz" 1 } } */ -/* { dg-final { scan-assembler-times "xvmsubasp" 1 } } */ -/* { dg-final { scan-assembler-times "xvnmaddasp" 1 } } */ -/* { dg-final { scan-assembler-times "xvnmaddadp" 1 } } */ -/* { dg-final { scan-assembler-times "xvnmsubadp" 1 } } */ -/* { dg-final { scan-assembler-times "vmsumshs" 1 } } */ -/* { dg-final { scan-assembler-times "xxland" 13 } } */ -/* { dg-final { scan-assembler-times "xxlxor" 2 } } */ -/* { dg-final { scan-assembler-times "xxsel" 2 } } */ -/* { dg-final { scan-assembler-times "xvrdpip" 1 } } */ -/* { dg-final { scan-assembler-times "xvdivdp" 1 } } */ -/* { dg-final { scan-assembler-times "xvrdpi" 5 } } */ - -/* Source code for the test in vsx-vector-6.h */ -#include "vsx-vector-6.h" diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-le.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-le.c deleted file mode 100644 index be5b972..0000000 --- a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-le.c +++ /dev/null @@ -1,47 +0,0 @@ -/* { dg-do compile { target { powerpc64le-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_vsx_ok } */ -/* { dg-options "-mvsx -O2 -mcpu=power8" } */ -/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ - -/* Expected instruction counts for Little Endian targeting Power8. */ - -/* { dg-final { scan-assembler-times "xvabsdp" 1 } } */ -/* { dg-final { scan-assembler-times "xvadddp" 1 } } */ -/* { dg-final { scan-assembler-times "xxlnor" 8 } } */ -/* We generate xxlor instructions for many reasons other than or'ing vector - operands or calling __builtin_vec_or(), which means we cannot rely on - their usage counts being stable. Therefore, we just ensure at least one - xxlor instruction was generated. */ -/* { dg-final { scan-assembler "xxlor" } } */ -/* { dg-final { scan-assembler-times "xvcmpeqdp" 4 } } */ -/* { dg-final { scan-assembler-times "xvcmpeqdp." 4 } } */ -/* { dg-final { scan-assembler-times "xvcmpgtdp" 7 } } */ -/* { dg-final { scan-assembler-times "xvcmpgtdp." 7 } } */ -/* { dg-final { scan-assembler-times "xvcmpgedp" 7 } } */ -/* { dg-final { scan-assembler-times "xvcmpgedp." 7 } } */ -/* { dg-final { scan-assembler-times "xvrdpim" 1 } } */ -/* { dg-final { scan-assembler-times "xvmaddadp" 1 } } */ -/* { dg-final { scan-assembler-times "xvmsubadp" 1 } } */ -/* { dg-final { scan-assembler-times "xvsubdp" 1 } } */ -/* { dg-final { scan-assembler-times "xvmaxdp" 1 } } */ -/* { dg-final { scan-assembler-times "xvmindp" 1 } } */ -/* { dg-final { scan-assembler-times "xvmuldp" 1 } } */ -/* { dg-final { scan-assembler-times "vperm" 1 } } */ -/* { dg-final { scan-assembler-times "xvrdpic" 1 } } */ -/* { dg-final { scan-assembler-times "xvsqrtdp" 1 } } */ -/* { dg-final { scan-assembler-times "xvrdpiz" 1 } } */ -/* { dg-final { scan-assembler-times "xvmsubasp" 1 } } */ -/* { dg-final { scan-assembler-times "xvnmaddasp" 1 } } */ -/* { dg-final { scan-assembler-times "xvnmaddadp" 1 } } */ -/* { dg-final { scan-assembler-times "xvnmsubadp" 1 } } */ -/* { dg-final { scan-assembler-times "vmsumshs" 1 } } */ -/* { dg-final { scan-assembler-times "xxland" 13 } } */ -/* { dg-final { scan-assembler-times "xxlxor" 2 } } */ -/* { dg-final { scan-assembler-times "xxsel" 2 } } */ -/* { dg-final { scan-assembler-times "xvrdpip" 1 } } */ -/* { dg-final { scan-assembler-times "xvdivdp" 1 } } */ -/* { dg-final { scan-assembler-times "xvrdpi" 5 } } */ - -/* Source code for the test in vsx-vector-6.h */ -#include "vsx-vector-6.h" diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-le.p9.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-le.p9.c deleted file mode 100644 index c2427b8..0000000 --- a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-le.p9.c +++ /dev/null @@ -1,37 +0,0 @@ -/* { dg-do compile { target { powerpc64le-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mvsx -O2 -mcpu=power9" } */ -/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ - -/* Expected instruction counts for Little Endian targeting Power9. */ - -/* { dg-final { scan-assembler-times "xvabsdp" 1 } } */ -/* { dg-final { scan-assembler-times "xvadddp" 1 } } */ -/* { dg-final { scan-assembler-times "xxlnor" 7 } } */ -/* We generate xxlor instructions for many reasons other than or'ing vector - operands or calling __builtin_vec_or(), which means we cannot rely on - their usage counts being stable. Therefore, we just ensure at least one - xxlor instruction was generated. */ -/* { dg-final { scan-assembler "xxlor" } } */ -/* { dg-final { scan-assembler-times "xvcmpeqdp" 5 } } */ -/* { dg-final { scan-assembler-times "xvcmpgtdp" 8 } } */ -/* { dg-final { scan-assembler-times "xvcmpgedp" 8 } } */ -/* { dg-final { scan-assembler-times "xvrdpim" 1 } } */ -/* { dg-final { scan-assembler-times "xvmaddadp" 1 } } */ -/* { dg-final { scan-assembler-times "xvmsubadp" 1 } } */ -/* { dg-final { scan-assembler-times "xvsubdp" 1 } } */ -/* { dg-final { scan-assembler-times "xvmaxdp" 1 } } */ -/* { dg-final { scan-assembler-times "xvmindp" 1 } } */ -/* { dg-final { scan-assembler-times "xvmuldp" 1 } } */ -/* { dg-final { scan-assembler-times "vperm" 1 } } */ -/* { dg-final { scan-assembler-times "xvrdpic" 1 } } */ -/* { dg-final { scan-assembler-times "xvsqrtdp" 1 } } */ -/* { dg-final { scan-assembler-times "xvrdpiz" 1 } } */ -/* { dg-final { scan-assembler-times "xvmsubasp" 1 } } */ -/* { dg-final { scan-assembler-times "xvnmaddasp" 1 } } */ -/* { dg-final { scan-assembler-times "vmsumshs" 1 } } */ -/* { dg-final { scan-assembler-times "xxland" 13 } } */ - -/* Source code for the test in vsx-vector-6.h */ -#include "vsx-vector-6.h" diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p7.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p7.c new file mode 100644 index 0000000..66ec064 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p7.c @@ -0,0 +1,50 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2 -mcpu=power7" } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ + + +/* Expected instruction counts for Power 7 */ + +/* { dg-final { scan-assembler-times "xvabsdp" 1 } } */ +/* { dg-final { scan-assembler-times "xvadddp" 1 } } */ +/* { dg-final { scan-assembler-times "xxlnor" 8 { target le } } } */ +/* { dg-final { scan-assembler-times "xxlnor" 8 { target be } } } */ +/* { dg-final { scan-assembler-times "xvcmpeqdp" 5 { target le } } } */ +/* { dg-final { scan-assembler-times "xvcmpeqdp" 6 { target be }} } */ +/* { dg-final { scan-assembler-times "xvcmpeqdp." 5 { target le } } } */ +/* { dg-final { scan-assembler-times "xvcmpeqdp." 6 { target be } } } */ +/* { dg-final { scan-assembler-times "xvcmpgtdp" 9 { target le } } } */ +/* { dg-final { scan-assembler-times "xvcmpgtdp" 8 { target be } } } */ +/* { dg-final { scan-assembler-times "xvcmpgtdp." 9 { target le } } } */ +/* { dg-final { scan-assembler-times "xvcmpgtdp." 8 { target be } } } */ +/* { dg-final { scan-assembler-times "xvcmpgedp" 6 { target le } } } */ +/* { dg-final { scan-assembler-times "xvcmpgedp" 7 { target be } } } */ +/* { dg-final { scan-assembler-times "xvcmpgedp." 6 { target le } } } */ +/* { dg-final { scan-assembler-times "xvcmpgedp." 7 { target be } } } */ +/* { dg-final { scan-assembler-times "xvrdpim" 1 } } */ +/* { dg-final { scan-assembler-times "xvmaddadp" 1 } } */ +/* { dg-final { scan-assembler-times "xvmsubadp" 1 } } */ +/* { dg-final { scan-assembler-times "xvsubdp" 1 } } */ +/* { dg-final { scan-assembler-times "xvmaxdp" 1 } } */ +/* { dg-final { scan-assembler-times "xvmindp" 1 } } */ +/* { dg-final { scan-assembler-times "xvmuldp" 1 } } */ +/* { dg-final { scan-assembler-times "vperm" 1 } } */ +/* { dg-final { scan-assembler-times "xvrdpic" 1 } } */ +/* { dg-final { scan-assembler-times "xvsqrtdp" 1 } } */ +/* { dg-final { scan-assembler-times "xvrdpiz" 1 } } */ +/* { dg-final { scan-assembler-times "xvmsubasp" 1 } } */ +/* { dg-final { scan-assembler-times "xvnmaddasp" 1 } } */ +/* { dg-final { scan-assembler-times "xvnmaddadp" 1 } } */ +/* { dg-final { scan-assembler-times "xvnmsubadp" 1 } } */ +/* { dg-final { scan-assembler-times "vmsumshs" 1 } } */ +/* { dg-final { scan-assembler-times "xxland" 13 } } */ +/* { dg-final { scan-assembler-times "xxlxor" 2 } } */ +/* { dg-final { scan-assembler-times "xxsel" 2 } } */ +/* { dg-final { scan-assembler-times "xvrdpip" 1 } } */ +/* { dg-final { scan-assembler-times "xvdivdp" 1 } } */ +/* { dg-final { scan-assembler-times "xvrdpi" 5 } } */ + +/* Source code for the test in vsx-vector-6.h */ +#include "vsx-vector-6.h" diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p8.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p8.c new file mode 100644 index 0000000..82fd45e --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p8.c @@ -0,0 +1,55 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2 -mcpu=power8" } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ + + +/* Expected instruction counts for Power 8. */ + +/* { dg-final { scan-assembler-times "xvabsdp" 1 } } */ +/* { dg-final { scan-assembler-times "xvadddp" 1 } } */ +/* { dg-final { scan-assembler-times "xxlnor" 8 { target le } } } */ +/* { dg-final { scan-assembler-times "xxlnor" 7 { target be } } } */ + +/* We generate xxlor instructions for many reasons other than or'ing vector + operands or calling __builtin_vec_or(), which means we cannot rely on + their usage counts being stable. Therefore, we just ensure at least one + xxlor instruction was generated. */ +/* { dg-final { scan-assembler "xxlor" } } */ + +/* { dg-final { scan-assembler-times "xvcmpeqdp" 4 { target le } } } */ +/* { dg-final { scan-assembler-times "xvcmpeqdp" 6 { target be } } } */ +/* { dg-final { scan-assembler-times "xvcmpeqdp." 4 { target le } } } */ +/* { dg-final { scan-assembler-times "xvcmpeqdp." 6 { target be } } } */ +/* { dg-final { scan-assembler-times "xvcmpgtdp" 7 { target le } } } */ +/* { dg-final { scan-assembler-times "xvcmpgtdp" 8 { target be } } } */ +/* { dg-final { scan-assembler-times "xvcmpgtdp." 7 { target le } } } */ +/* { dg-final { scan-assembler-times "xvcmpgtdp." 8 { target be } } } */ +/* { dg-final { scan-assembler-times "xvcmpgedp" 7 } } */ +/* { dg-final { scan-assembler-times "xvcmpgedp." 7 } } */ +/* { dg-final { scan-assembler-times "xvrdpim" 1 } } */ +/* { dg-final { scan-assembler-times "xvmaddadp" 1 } } */ +/* { dg-final { scan-assembler-times "xvmsubadp" 1 } } */ +/* { dg-final { scan-assembler-times "xvsubdp" 1 } } */ +/* { dg-final { scan-assembler-times "xvmaxdp" 1 } } */ +/* { dg-final { scan-assembler-times "xvmindp" 1 } } */ +/* { dg-final { scan-assembler-times "xvmuldp" 1 } } */ +/* { dg-final { scan-assembler-times "vperm" 1 } } */ +/* { dg-final { scan-assembler-times "xvrdpic" 1 } } */ +/* { dg-final { scan-assembler-times "xvsqrtdp" 1 } } */ +/* { dg-final { scan-assembler-times "xvrdpiz" 1 } } */ +/* { dg-final { scan-assembler-times "xvmsubasp" 1 } } */ +/* { dg-final { scan-assembler-times "xvnmaddasp" 1 } } */ +/* { dg-final { scan-assembler-times "xvnmaddadp" 1 } } */ +/* { dg-final { scan-assembler-times "xvnmsubadp" 1 } } */ +/* { dg-final { scan-assembler-times "vmsumshs" 1 } } */ +/* { dg-final { scan-assembler-times "xxland" 13 } } */ +/* { dg-final { scan-assembler-times "xxlxor" 2 } } */ +/* { dg-final { scan-assembler-times "xxsel" 2 } } */ +/* { dg-final { scan-assembler-times "xvrdpip" 1 } } */ +/* { dg-final { scan-assembler-times "xvdivdp" 1 } } */ +/* { dg-final { scan-assembler-times "xvrdpi" 5 } } */ + +/* Source code for the test in vsx-vector-6.h */ +#include "vsx-vector-6.h" diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p9.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p9.c new file mode 100644 index 0000000..0fcd153 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p9.c @@ -0,0 +1,39 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mvsx -O2 -mcpu=power9" } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ + +/* Expected instruction counts for Power9. */ + +/* { dg-final { scan-assembler-times "xvabsdp" 1 } } */ +/* { dg-final { scan-assembler-times "xvadddp" 1 } } */ +/* { dg-final { scan-assembler-times "xxlnor" 7 } } */ + +/* We generate xxlor instructions for many reasons other than or'ing vector + operands or calling __builtin_vec_or(), which means we cannot rely on + their usage counts being stable. Therefore, we just ensure at least one + xxlor instruction was generated. */ +/* { dg-final { scan-assembler "xxlor" } } */ + +/* { dg-final { scan-assembler-times "xvcmpeqdp" 5 } } */ +/* { dg-final { scan-assembler-times "xvcmpgtdp" 8 } } */ +/* { dg-final { scan-assembler-times "xvcmpgedp" 8 } } */ +/* { dg-final { scan-assembler-times "xvrdpim" 1 } } */ +/* { dg-final { scan-assembler-times "xvmaddadp" 1 } } */ +/* { dg-final { scan-assembler-times "xvmsubadp" 1 } } */ +/* { dg-final { scan-assembler-times "xvsubdp" 1 } } */ +/* { dg-final { scan-assembler-times "xvmaxdp" 1 } } */ +/* { dg-final { scan-assembler-times "xvmindp" 1 } } */ +/* { dg-final { scan-assembler-times "xvmuldp" 1 } } */ +/* { dg-final { scan-assembler-times "vperm" 1 } } */ +/* { dg-final { scan-assembler-times "xvrdpic" 1 } } */ +/* { dg-final { scan-assembler-times "xvsqrtdp" 1 } } */ +/* { dg-final { scan-assembler-times "xvrdpiz" 1 } } */ +/* { dg-final { scan-assembler-times "xvmsubasp" 1 } } */ +/* { dg-final { scan-assembler-times "xvnmaddasp" 1 } } */ +/* { dg-final { scan-assembler-times "vmsumshs" 1 } } */ +/* { dg-final { scan-assembler-times "xxland" 13 } } */ + +/* Source code for the test in vsx-vector-6.h */ +#include "vsx-vector-6.h"