From patchwork Wed Sep 6 15:22:03 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Carl Love X-Patchwork-Id: 810673 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-461621-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="Yl3qksA8"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3xnS4j1C3dz9t2R for ; Thu, 7 Sep 2017 01:22:27 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:from:to:cc:date:content-type:mime-version :content-transfer-encoding:message-id; q=dns; s=default; b=inKAL SxjbfjOGYYv+Tm9oQfMFigwkJA+YjMx892+Eu5WoGFH58Zl8fviGVHgLDbCwDBOr zOFgX60qbDauXWyuKyWk9jYFymdnNN81wC5+OX+TyALeK4NJkzEm4AVNUKOfiv5H K4fzoSBVCauEI5Y9J/zpVZN1jV6jxpCLPrw5No= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:from:to:cc:date:content-type:mime-version :content-transfer-encoding:message-id; s=default; bh=fGG5vOp+ksy jjPv+XvTBm6ReXHQ=; b=Yl3qksA8aTYyTtLYUHL+PKIlo7QwOMpYJTE4Ms0t4j+ UpRLOCvyz2oL3DkR/grb9jgA6jVkmlcfDAQ4T6OzKDcFLz8E8YJp39GoScHItIIl HSGdYz5V3paSwZUER16jhv1QlvDnjj2Hu9COauMm93ZMMiTMnrXw1dcuxlhz50E8 = Received: (qmail 48172 invoked by alias); 6 Sep 2017 15:22:17 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 48147 invoked by uid 89); 6 Sep 2017 15:22:17 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-26.8 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 spammy=Love X-HELO: mx0a-001b2d01.pphosted.com Received: from mx0b-001b2d01.pphosted.com (HELO mx0a-001b2d01.pphosted.com) (148.163.158.5) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 06 Sep 2017 15:22:09 +0000 Received: from pps.filterd (m0098416.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id v86FL0bB176075 for ; Wed, 6 Sep 2017 11:22:08 -0400 Received: from e34.co.us.ibm.com (e34.co.us.ibm.com [32.97.110.152]) by mx0b-001b2d01.pphosted.com with ESMTP id 2ctfxvphmr-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Wed, 06 Sep 2017 11:22:07 -0400 Received: from localhost by e34.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Wed, 6 Sep 2017 09:22:04 -0600 Received: from b03ledav006.gho.boulder.ibm.com (b03ledav006.gho.boulder.ibm.com [9.17.130.237]) by b03cxnp08026.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v86FM4fN65208496; Wed, 6 Sep 2017 08:22:04 -0700 Received: from b03ledav006.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 59322C604C; Wed, 6 Sep 2017 09:22:04 -0600 (MDT) Received: from oc3304648336.ibm.com (unknown [9.70.82.190]) by b03ledav006.gho.boulder.ibm.com (Postfix) with ESMTP id DF99DC603C; Wed, 6 Sep 2017 09:22:03 -0600 (MDT) Subject: [PATCH, rs6000] Add support for vec_xst_len_r() and vec_xl_len_r() builtins From: Carl Love To: gcc-patches@gcc.gnu.org, David Edelsohn , Segher Boessenkool Cc: Bill Schmidt , cel@us.ibm.com Date: Wed, 06 Sep 2017 08:22:03 -0700 Mime-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 17090615-0016-0000-0000-000007797121 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00007677; HX=3.00000241; KW=3.00000007; PH=3.00000004; SC=3.00000226; SDB=6.00913125; UDB=6.00458264; IPR=6.00693387; BA=6.00005574; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009; ZB=6.00000000; ZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00017034; XFM=3.00000015; UTC=2017-09-06 15:22:05 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17090615-0017-0000-0000-00003B5B9FE2 Message-Id: <1504711323.18797.5.camel@us.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-09-06_05:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1707230000 definitions=main-1709060214 X-IsSubscribed: yes GCC Maintainers: The following patch adds support for the vec_xst_len_r() and vec_xl_len_r() Powerr 9 builtins. The patch has been run on powerpc64le-unknown-linux-gnu (Power 9 LE). No regressions were found but it does seem to "fix" a couple of existing tests. 136a137 > FAIL: TestCgoCallbackGC 139c140,141 < # of expected passes 350 --- > # of expected passes 349 > # of unexpected failures 1 141c143 < /home/carll/GCC/build/gcc-builtin-pre-commit/./gcc/gccgo version 8.0.0 20170905 (experimental) (GCC) --- > /home/carll/GCC/build/gcc-base/./gcc/gccgo version 8.0.0 20170905 (experimental) (GCC) 163a166 > FAIL: html/template 167,168c170,172 < # of expected passes 146 < /home/carll/GCC/build/gcc-builtin-pre-commit/./gcc/gccgo version 8.0.0 20170905 (experimental) (GCC) --- > # of expected passes 145 > # of unexpected failures 1 > /home/carll/GCC/build/gcc-base/./gcc/gccgo version 8.0.0 20170905 (experimental) (GCC) Please let me know if the following patch is acceptable. Thanks. Carl Love ------------------------------------------------------------------------ gcc/ChangeLog: 2017-09-06 Carl Love * config/rs6000/rs6000-c.c (P9V_BUILTIN_VEC_XL_LEN_R, P9V_BUILTIN_VEC_XST_LEN_R): Add support for builtins vector unsigned char vec_xl_len_r (unsigned char *, size_t); void vec_xst_len_r (vector unsigned char, unsigned char *, size_t); * config/rs6000/altivec.h (vec_xl_len_r, vec_xst_len_r): Add defines. * config/rs6000/rs6000-builtin.def (XL_LEN_R, XST_LEN_R): Add definitions and overloading. * config/rs6000/rs6000.c (altivec_expand_builtin): Add case statement for P9V_BUILTIN_XST_LEN_R. (altivec_init_builtins): Add def_builtin for P9V_BUILTIN_STXVLL. * config/rs6000/vsx.md (addi_neg16, lxvll, stxvll, altivec_lvsl_reg, altivec_lvsr_reg, xl_len_r, xst_len_r): Add define_expand and define_insn for the instructions and builtins. (define_insn "*stxvl"): add missing argument to the sldi instruction. * doc/extend.texi: Update the built-in documenation file for the new built-in functions. gcc/testsuite/ChangeLog: 2017-09-06 Carl Love * gcc.target/powerpc/builtins-5-p9-runnable.c: Add new runable test file for the new built-ins and the existing built-ins. --- gcc/config/rs6000/altivec.h | 2 + gcc/config/rs6000/rs6000-builtin.def | 4 + gcc/config/rs6000/rs6000-c.c | 8 + gcc/config/rs6000/rs6000.c | 7 +- gcc/config/rs6000/vsx.md | 133 ++++++++- gcc/doc/extend.texi | 4 + .../gcc.target/powerpc/builtins-5-p9-runnable.c | 309 +++++++++++++++++++++ 7 files changed, 465 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/builtins-5-p9-runnable.c diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h index c8e508c..94a4db2 100644 --- a/gcc/config/rs6000/altivec.h +++ b/gcc/config/rs6000/altivec.h @@ -467,6 +467,8 @@ #ifdef _ARCH_PPC64 #define vec_xl_len __builtin_vec_lxvl #define vec_xst_len __builtin_vec_stxvl +#define vec_xl_len_r __builtin_vec_xl_len_r +#define vec_xst_len_r __builtin_vec_xst_len_r #endif #define vec_cmpnez __builtin_vec_vcmpnez diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def index 850164a..8f87cce 100644 --- a/gcc/config/rs6000/rs6000-builtin.def +++ b/gcc/config/rs6000/rs6000-builtin.def @@ -2125,6 +2125,7 @@ BU_P9V_OVERLOAD_2 (VIESP, "insert_exp_sp") /* 2 argument vector functions added in ISA 3.0 (power9). */ BU_P9V_64BIT_VSX_2 (LXVL, "lxvl", CONST, lxvl) +BU_P9V_64BIT_VSX_2 (XL_LEN_R, "xl_len_r", CONST, xl_len_r) BU_P9V_AV_2 (VEXTUBLX, "vextublx", CONST, vextublx) BU_P9V_AV_2 (VEXTUBRX, "vextubrx", CONST, vextubrx) @@ -2141,6 +2142,7 @@ BU_P9V_VSX_3 (VINSERT4B_DI, "vinsert4b_di", CONST, vinsert4b_di) /* 3 argument vector functions returning void, treated as SPECIAL, added in ISA 3.0 (power9). */ BU_P9V_64BIT_AV_X (STXVL, "stxvl", MISC) +BU_P9V_64BIT_AV_X (XST_LEN_R, "xst_len_r", MISC) /* 1 argument vector functions added in ISA 3.0 (power9). */ BU_P9V_AV_1 (VCLZLSBB, "vclzlsbb", CONST, vclzlsbb) @@ -2182,12 +2184,14 @@ BU_P9V_AV_P (VCMPNEZW_P, "vcmpnezw_p", CONST, vector_nez_v4si_p) /* ISA 3.0 Vector scalar overloaded 2 argument functions */ BU_P9V_OVERLOAD_2 (LXVL, "lxvl") +BU_P9V_OVERLOAD_2 (XL_LEN_R, "xl_len_r") BU_P9V_OVERLOAD_2 (VEXTULX, "vextulx") BU_P9V_OVERLOAD_2 (VEXTURX, "vexturx") BU_P9V_OVERLOAD_2 (VEXTRACT4B, "vextract4b") /* ISA 3.0 Vector scalar overloaded 3 argument functions */ BU_P9V_OVERLOAD_3 (STXVL, "stxvl") +BU_P9V_OVERLOAD_3 (XST_LEN_R, "xst_len_r") BU_P9V_OVERLOAD_3 (VINSERT4B, "vinsert4b") /* Overloaded CMPNE support was implemented prior to Power 9, diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c index 897306c..15f0406 100644 --- a/gcc/config/rs6000/rs6000-c.c +++ b/gcc/config/rs6000/rs6000-c.c @@ -4787,6 +4787,10 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { P9V_BUILTIN_VEC_VSCEDPUO, P9V_BUILTIN_VSCEDPUO, RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 }, + { P9V_BUILTIN_VEC_XL_LEN_R, P9V_BUILTIN_XL_LEN_R, + RS6000_BTI_unsigned_V16QI, ~RS6000_BTI_UINTQI, + RS6000_BTI_unsigned_long_long, 0 }, + { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL, RS6000_BTI_V16QI, ~RS6000_BTI_INTQI, RS6000_BTI_unsigned_long_long, 0 }, @@ -4831,6 +4835,10 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { /* At an appropriate future time, add support for the RS6000_BTI_Float16 (exact name to be determined) type here. */ + { P9V_BUILTIN_VEC_XST_LEN_R, P9V_BUILTIN_XST_LEN_R, + RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, + ~RS6000_BTI_UINTQI, RS6000_BTI_unsigned_long_long}, + { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL, RS6000_BTI_void, RS6000_BTI_V16QI, ~RS6000_BTI_INTQI, RS6000_BTI_unsigned_long_long }, diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 6d613c3..6df2d79 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -15580,6 +15580,8 @@ altivec_expand_builtin (tree exp, rtx target, bool *expandedp) case P9V_BUILTIN_STXVL: return altivec_expand_stxvl_builtin (CODE_FOR_stxvl, exp); + case P9V_BUILTIN_XST_LEN_R: + return altivec_expand_stxvl_builtin (CODE_FOR_xst_len_r, exp); case VSX_BUILTIN_STXVD2X_V1TI: return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v1ti, exp); case VSX_BUILTIN_STXVD2X_V2DF: @@ -17534,9 +17536,12 @@ altivec_init_builtins (void) def_builtin ("__builtin_vec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRX); def_builtin ("__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRXL); - if (TARGET_P9_VECTOR) + if (TARGET_P9_VECTOR) { def_builtin ("__builtin_altivec_stxvl", void_ftype_v16qi_pvoid_long, P9V_BUILTIN_STXVL); + def_builtin ("__builtin_xst_len_r", void_ftype_v16qi_pvoid_long, + P9V_BUILTIN_XST_LEN_R); + } /* Add the DST variants. */ d = bdesc_dst; diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index b47eeac..b9c7343 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -382,8 +382,17 @@ UNSPEC_VSX_VTSTDC UNSPEC_VSX_VEC_INIT UNSPEC_VSX_VSIGNED2 + + UNSPEC_ADDI_NEG16 UNSPEC_LXVL + UNSPEC_LXVLL + UNSPEC_LVSL_REG + UNSPEC_LVSR_REG UNSPEC_STXVL + UNSPEC_STXVLL + UNSPEC_XL_LEN_R + UNSPEC_XST_LEN_R + UNSPEC_VCLZLSBB UNSPEC_VCTZLSBB UNSPEC_VEXTUBLX @@ -4352,6 +4361,106 @@ [(set_attr "length" "8") (set_attr "type" "vecload")]) +(define_insn "addi_neg16" + [(set (match_operand:DI 0 "vsx_register_operand" "=r") + (unspec:DI + [(match_operand:DI 1 "gpc_reg_operand" "r")] + UNSPEC_ADDI_NEG16))] + "" + "addi %0,%1,-16" +) + +;; Load VSX Vector with Length, right justified +(define_expand "lxvll" + [(set (match_dup 3) + (match_operand:DI 2 "register_operand")) + (set (match_operand:V16QI 0 "vsx_register_operand") + (unspec:V16QI + [(match_operand:DI 1 "gpc_reg_operand") + (match_dup 3)] + UNSPEC_LXVLL))] + "TARGET_P9_VECTOR && TARGET_64BIT" +{ + operands[3] = gen_reg_rtx (DImode); +}) + +(define_insn "*lxvll" + [(set (match_operand:V16QI 0 "vsx_register_operand" "=wa") + (unspec:V16QI + [(match_operand:DI 1 "gpc_reg_operand" "b") + (match_operand:DI 2 "register_operand" "+r")] + UNSPEC_LXVLL))] + "TARGET_P9_VECTOR && TARGET_64BIT" +;; "lxvll %x0,%1,%2;" + "sldi %2,%2, 56\; lxvll %x0,%1,%2;" + [(set_attr "length" "8") + (set_attr "type" "vecload")]) + +(define_insn "altivec_lvsl_reg" + [(set (match_operand:V16QI 0 "vsx_register_operand" "=v") + (unspec:V16QI + [(match_operand:DI 1 "gpc_reg_operand" "b")] + UNSPEC_LVSL_REG))] + "TARGET_ALTIVEC" + "lvsl %0,0,%1" + [(set_attr "type" "vecload")]) + +(define_insn "altivec_lvsr_reg" + [(set (match_operand:V16QI 0 "vsx_register_operand" "=v") + (unspec:V16QI + [(match_operand:DI 1 "gpc_reg_operand" "b")] + UNSPEC_LVSR_REG))] + "TARGET_ALTIVEC" + "lvsr %0,0,%1" + [(set_attr "type" "vecload")]) + +;; Expand for builtin xl_len_r +(define_expand "xl_len_r" + [(match_operand:V16QI 0 "vsx_register_operand" "=v") + (match_operand:DI 1 "register_operand" "r") + (match_operand:DI 2 "register_operand" "r")] + "UNSPEC_XL_LEN_R" +{ + rtx shift_mask = gen_reg_rtx (V16QImode); + rtx rtx_vtmp = gen_reg_rtx (V16QImode); + rtx tmp = gen_reg_rtx (DImode); + +/* Setup permute vector to shift right by operands[2] bytes. + Note: addi operands[2], -16 is negative so we actually need to + shift left to get a right shift. */ + emit_insn (gen_addi_neg16 (tmp, operands[2])); + emit_insn (gen_altivec_lvsl_reg (shift_mask, tmp)); + emit_insn (gen_lxvll (rtx_vtmp, operands[1], operands[2])); + emit_insn (gen_altivec_vperm_v8hiv16qi (operands[0], rtx_vtmp, + rtx_vtmp, shift_mask)); + DONE; +}) + +;; Store VSX Vector with Length, right justified +(define_expand "stxvll" + [(set (match_dup 3) + (match_operand:DI 2 "register_operand")) + (set (mem:V16QI (match_operand:DI 1 "gpc_reg_operand")) + (unspec:V16QI + [(match_operand:V16QI 0 "vsx_register_operand") + (match_dup 3)] + UNSPEC_STXVLL))] + "TARGET_P9_VECTOR && TARGET_64BIT" +{ + operands[3] = gen_reg_rtx (DImode); +}) + +(define_insn "*stxvll" + [(set (mem:V16QI (match_operand:DI 1 "gpc_reg_operand" "b")) + (unspec:V16QI + [(match_operand:V16QI 0 "vsx_register_operand" "wa") + (match_operand:DI 2 "register_operand" "+r")] + UNSPEC_STXVLL))] + "TARGET_P9_VECTOR && TARGET_64BIT" + "sldi %2,%2,56\;stxvll %x0,%1,%2" + [(set_attr "length" "8") + (set_attr "type" "vecstore")]) + ;; Store VSX Vector with Length (define_expand "stxvl" [(set (match_dup 3) @@ -4373,10 +4482,32 @@ (match_operand:DI 2 "register_operand" "+r")] UNSPEC_STXVL))] "TARGET_P9_VECTOR && TARGET_64BIT" - "sldi %2,%2\;stxvl %x0,%1,%2" + "sldi %2,%2,56\;stxvl %x0,%1,%2" [(set_attr "length" "8") (set_attr "type" "vecstore")]) +;; Expand for builtin xst_len_r +(define_expand "xst_len_r" + [(match_operand:V16QI 0 "vsx_register_operand" "=v") + (match_operand:DI 1 "register_operand" "r") + (match_operand:DI 2 "register_operand" "r")] + "UNSPEC_XST_LEN_R" +{ + rtx shift_mask = gen_reg_rtx (V16QImode); + rtx rtx_vtmp = gen_reg_rtx (V16QImode); + rtx tmp = gen_reg_rtx (DImode); + +/* Setup permute vector to shift left by operands[2] bytes. + Note: addi operands[2], -16 is negative so we actually need to + shift right to get a left shift. */ + emit_insn (gen_addi_neg16 (tmp, operands[2])); + emit_insn (gen_altivec_lvsr_reg (shift_mask, tmp)); + emit_insn (gen_altivec_vperm_v8hiv16qi (rtx_vtmp, operands[0], + operands[0], shift_mask)); + emit_insn (gen_stxvll (rtx_vtmp, operands[1], operands[2])); + DONE; +}) + ;; Vector Compare Not Equal Byte (define_insn "vcmpneb" [(set (match_operand:V16QI 0 "altivec_register_operand" "=v") diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 649be01..37fd769 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -15631,6 +15631,8 @@ vector unsigned short vec_xl_len (unsigned short *addr, size_t len); vector double vec_xl_len (double *addr, size_t len); vector float vec_xl_len (float *addr, size_t len); +vector unsigned char vec_xl_len_r (unsigned char *addr, size_t len); + void vec_xst_len (vector signed char data, signed char *addr, size_t len); void vec_xst_len (vector unsigned char data, unsigned char *addr, size_t len); void vec_xst_len (vector signed int data, signed int *addr, size_t len); @@ -15644,6 +15646,8 @@ void vec_xst_len (vector signed __int128 data, signed __int128 *addr, size_t len void vec_xst_len (vector double data, double *addr, size_t len); void vec_xst_len (vector float data, float *addr, size_t len); +void vec_xst_len_r (vector unsigned char data, unsigned char *addr, size_t len); + signed char vec_xlx (unsigned int index, vector signed char data); unsigned char vec_xlx (unsigned int index, vector unsigned char data); signed short vec_xlx (unsigned int index, vector signed short data); diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-5-p9-runnable.c b/gcc/testsuite/gcc.target/powerpc/builtins-5-p9-runnable.c new file mode 100644 index 0000000..448e974 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/builtins-5-p9-runnable.c @@ -0,0 +1,309 @@ +/* { dg-do run { target { powerpc64*-*-* && { p9vector_hw } } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-options "-mcpu=power9 -O2" } */ + +#include +#include +#include +#include // vector + +#define TRUE 1 +#define FALSE 0 + +#ifdef DEBUG +#include +#endif + +void abort (void); + +int result_wrong(vector unsigned char vec_expected, + vector unsigned char vec_actual) +{ + int i; + + for (i=0; i<16; i++) + if (vec_expected[i] != vec_actual[i]) + return TRUE; + + return FALSE; +} + +int main() { + int i, j; + size_t size; + unsigned char data_uc[100]; + vector unsigned char store_data_uc; + unsigned char *address; + vector unsigned char *datap; + + vector unsigned char vec_uc_expected1, vec_uc_expected2, + vec_uc_result1, vec_uc_result2; + vector int data_int; + + for (i=0; i<100; i++) + data_uc[i] = i+1; + + + /* VEC_XL_LEN */ + + size = 8; + vec_uc_result1 = vec_xl_len (data_uc, size); + + vec_uc_expected1 = (vector unsigned char){ 1, 2, 3, 4, 5, 6, 7, 8, + 0, 0, 0, 0, 0, 0, 0, 0}; + + if (result_wrong (vec_uc_expected1, vec_uc_result1)) + { +#ifdef DEBUG + printf("Error: result does not match expected result\n"); + printf("vec_xl_len (%d): vec_uc_expected1[0] to vec_uc_expected1[15]\n", + size); + + for (i=0; i<16; i++) + printf(" %d,",vec_uc_expected1[i]); + + printf("\nvec_xl_len (%d): vec_uc_result1[0] to vec_uc_result1[15]\n", + size); + + for (i=0; i<16; i++) + printf(" %d,", vec_uc_result1[i]); + + printf("\n\n"); +#else + abort(); +#endif + } + + + /* VEC_XL_LEN_R */ + size = 8; + vec_uc_result2 = vec_xl_len_r(data_uc, size); + + vec_uc_expected2 = (vector unsigned char){8, 7, 6, 5, 4, 3, 2, 1, + 0, 0, 0, 0, 0, 0, 0, 0,}; + + if (result_wrong (vec_uc_expected2, vec_uc_result2)) + { +#ifdef DEBUG + printf("Error: result does not match expected result\n"); + printf("vec_xl_len_r(%d): vec_uc_expected2[0] to vec_uc_expected2[15]\n", + size); + + for (i=0; i<16; i++) + printf(" %d,", vec_uc_expected2[i]); + + printf("\nvec_xl_len_r(%d): vec_uc_result2[0] to vec_uc_result2[15]\n", + size); + + for (i=0; i<16; i++) + printf(" %d,", vec_uc_result2[i]); + + printf("\n\n"); +#else + abort(); +#endif + } + + + size = 4; + vec_uc_result2 = vec_xl_len_r(data_uc, size); + + vec_uc_expected2 = (vector unsigned char){ 4, 3, 2, 1, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }; + + if (result_wrong (vec_uc_expected2, vec_uc_result2)) + { +#ifdef DEBUG + printf("Error: result does not match expected result\n"); + printf("vec_xl_len_r(%d): vec_uc_expected2[0] to vec_uc_expected2[15]\n", + size); + + for (i=0; i<16; i++) + printf(" %d,", vec_uc_expected2[i]); + + printf("\nvec_xl_len_r(%d): vec_uc_result2[0] to vec_uc_result2[15]\n", + size); + + for (i=0; i<16; i++) + printf(" %d,", vec_uc_result2[i]); + + printf("\n\n"); +#else + abort(); +#endif + } + + size = 2; + vec_uc_result2 = vec_xl_len_r(data_uc, size); + + vec_uc_expected2 = (vector unsigned char){ 2, 1, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }; + + if (result_wrong (vec_uc_expected2, vec_uc_result2)) + { +#ifdef DEBUG + printf("Error: result does not match expected result\n"); + printf("vec_xl_len_r(%d): vec_uc_expected2[0] to vec_uc_expected2[15]\n", + size); + for (i=0; i<16; i++) + printf(" %d,", vec_uc_expected2[i]); + + printf("\nvec_xl_len_r(%d) vec_uc_result2[0] to vec_uc_result2[15]\n", + size); + + for (i=0; i<16; i++) + printf(" %d,", vec_uc_result2[i]); + + printf("\n\n"); +#else + abort(); +#endif + } + + + /* VEC_XST_LEN */ + vec_uc_expected2 = (vector unsigned char){ 1, 2, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }; + store_data_uc = (vector unsigned char){ 1, 2, 3, 4, 5, 6, 7, 8, + 9, 10, 11, 12, 13, 14, 15, 16 }; + size = 2; + + for (i=0; i<16; i++) + vec_uc_result2[i] = 0; + + address = &vec_uc_result2[0]; + vec_xst_len (store_data_uc, address, size); + + if (result_wrong (vec_uc_expected2, vec_uc_result2)) + { +#ifdef DEBUG + printf("Error: result does not match expected result\n"); + printf("vec_xst_len (%d) vec_uc_result2[0] to vec_uc_result2[15]\n", + size); + + for (i=0; i<16; i++) + printf(" %d,", vec_uc_expected2[i]); + + printf("\nvec_xst_len (%d) store_data_uc[0] to store_data_uc[15]\n", + size); + + for (i=0; i<16; i++) + printf(" %d,", vec_uc_result2[i]); + + printf("\n\n"); +#else + abort(); +#endif + } + + vec_uc_expected2 = (vector unsigned char){ 1, 2, 3, 4, 5, 6, 7, 8, + 9, 10, 11, 12, 13, 14, 0, 0 }; + store_data_uc = (vector unsigned char){ 1, 2, 3, 4, 5, 6, 7, 8, + 9, 10, 11, 12, 13, 14, 15, 16 }; + size = 14; + + for (i=0; i<16; i++) + vec_uc_result2[i] = 0; + + address = &vec_uc_result2[0]; + + vec_xst_len (store_data_uc, address, size); + + if (result_wrong (vec_uc_expected2, vec_uc_result2)) + { +#ifdef DEBUG + printf("Error: result does not match expected result\n"); + printf("vec_xst_len (%d) vec_uc_result2[0] to vec_uc_result2[15]\n", + size); + + for (i=0; i<16; i++) + printf(" %d,", vec_uc_expected2[i]); + + printf("\nvec_xst_len (%d) store_data_uc[0] to store_data_uc[15]\n", + size); + + for (i=0; i<16; i++) + printf(" %d,", vec_uc_result2[i]); + + printf("\n\n"); +#else + abort(); +#endif + } + + /* VEC_XST_LEN_R */ + vec_uc_expected1 = (vector unsigned char){ 2, 1, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }; + store_data_uc = (vector unsigned char){ 1, 2, 3, 4, 5, 6, 7, 8, + 9, 10, 11, 12, 13, 14, 15, 16 }; + vec_uc_result1 = (vector unsigned char){ 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }; + + size = 2; + + for (i=0; i<16; i++) + vec_uc_result1[i] = 0; + + address = &vec_uc_result1[0]; + + vec_xst_len_r(store_data_uc, address, size); + + if (result_wrong (vec_uc_expected1, vec_uc_result1)) + { +#ifdef DEBUG + printf("Error: result does not match expected result\n"); + printf("vec_xst_len_r(%d) vec_uc_expected1[0] to vec_uc_expected1[15]\n", + size); + + for (i=0; i<16; i++) + printf(" %d,", vec_uc_expected1[i]); + + printf("\nvec_xst_len_r(%d) result[0] to result[15]\n", size); + + for (i=0; i<16; i++) + printf(" %d,", vec_uc_result1[i]); + + printf("\n\n"); +#else + abort(); +#endif + } + + + vec_uc_expected1 = (vector unsigned char){ 14, 13, 12, 11, 10, 9, 8, 7, + 6, 5, 4, 3, 2, 1, 0, 0 }; + store_data_uc = (vector unsigned char){ 1, 2, 3, 4, 5, 6, 7, 8, + 9, 10, 11, 12, 13, 14, 15, 16 }; + vec_uc_result1 = (vector unsigned char){ 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }; + + size = 14; + + for (i=0; i<16; i++) + vec_uc_result1[i] = 0; + + address = &vec_uc_result1[0]; + + vec_xst_len_r(store_data_uc, address, size); + + if (result_wrong (vec_uc_expected1, vec_uc_result1)) + { +#ifdef DEBUG + printf("Error: result does not match expected result\n"); + printf("vec_xst_len_r(%d) vec_uc_expected2[0] to vec_uc_expected2[15]\n", + size); + + for (i=0; i<16; i++) + printf(" %d,", vec_uc_expected2[i]); + + printf("\nvec_xst_len_r(%d) result[0] to result[15]\n", size); + + for (i=0; i<16; i++) + printf(" %d,", vec_uc_result1[i]); + + printf("\n\n"); +#else + abort(); +#endif + } +}