From patchwork Tue Jul 1 10:05:55 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Lyon X-Patchwork-Id: 366003 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id E00CD140081 for ; Tue, 1 Jul 2014 20:07:42 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:in-reply-to:references; q=dns; s= default; b=AmYPJVrOpccRz2dD060dPTh96niSU8q3MHFrSn5xpcNUOTDrJQMkF aplRLh4BXXsb0Whv9AOmbCgLR2riHI/bQ2sO/U3ii+pYW17gOFxkxM5eW+HeK6HU 70iYw3fHVrJMXZjhxxlFv7vkR+8eV60EaUmWOwKBN6ANFr5e1Lup20= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:in-reply-to:references; s=default; bh=TPP/Mc6WZZ7tONxcFY1sXkS4RaE=; b=coVFg3C4zrb8hp3CnO+qtNaPksOF vB1H96ctzJztqw3WPk9WlTLLCCIJhXpGPLxi5JIBHVnW3rbqwjVOuTDCmccJe4OK 6lheOlX5dQLPu4GEmx6vYeMFiEI4HUqaQUQo/L70PEOl+ImJlN/jT0zZOxFGc1Q9 WHq9lGTMnJ8S3bc= Received: (qmail 2078 invoked by alias); 1 Jul 2014 10:07:14 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 2048 invoked by uid 89); 1 Jul 2014 10:07:12 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-we0-f171.google.com Received: from mail-we0-f171.google.com (HELO mail-we0-f171.google.com) (74.125.82.171) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Tue, 01 Jul 2014 10:07:08 +0000 Received: by mail-we0-f171.google.com with SMTP id q58so9519565wes.30 for ; Tue, 01 Jul 2014 03:07:05 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=/FpeZiRCwfGq5E2qCLHR64+4QwGo1URY+Nd6Wf4L5F4=; b=OTPJgSC2su/U+tgASugB4QEGI1wGsWhl979iulDQ/zOVnLtl95amY2K1WSJuLmi66/ dYmEQADToIJ3UCN6KpXJfepVHQlJ+6+yTq8F8j/DTsiuLxPWEQMyyu49ZVQf1mpa6Ucw JIgKo+miJea4YUqfjtM70oYzVDulzrNYYsZuKrXb/xxJtPjFX7oqv8yRTt0/w9YlzxfY /OrUDptkkwqK6iFBT5OqrO+4+gWhSSoUYHArVM+GOMGlPC6R2WiC0IaCCPevo6OffdtC lpcqhLlrgkaj2jRPcAF7sGj1lUbLRElO6o5exNacZmIJqIA7zgYc/UyRDC42g16HBaF6 y2Ow== X-Gm-Message-State: ALoCoQm9H6G2XIAt5fCEm16rTRiaimWo5pxoyKuLq3cqZymjKqUPAJoIG0LFFqEzdUx5Irrd1Yln X-Received: by 10.194.120.129 with SMTP id lc1mr15810579wjb.16.1404209225051; Tue, 01 Jul 2014 03:07:05 -0700 (PDT) Received: from gnx2647.cec-lab.gnb.st.com ([2a01:e35:2e1d:eaf0:210:75ff:fe1a:c986]) by mx.google.com with ESMTPSA id kr6sm47178017wjb.16.2014.07.01.03.07.03 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 01 Jul 2014 03:07:04 -0700 (PDT) From: Christophe Lyon To: gcc-patches@gcc.gnu.org Subject: [Patch ARM-AArch64/testsuite v2 02/21] Add unary operators: vabs and vneg. Date: Tue, 1 Jul 2014 12:05:55 +0200 Message-Id: <1404209174-25364-3-git-send-email-christophe.lyon@linaro.org> In-Reply-To: <1404209174-25364-1-git-send-email-christophe.lyon@linaro.org> References: <1404209174-25364-1-git-send-email-christophe.lyon@linaro.org> X-IsSubscribed: yes diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 3a0f99b..44c4990 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,11 @@ 2014-06-30 Christophe Lyon + * gcc.target/aarch64/neon-intrinsics/unary_op.inc: New file. + * gcc.target/aarch64/neon-intrinsics/vabs.c: Likewise. + * gcc.target/aarch64/neon-intrinsics/vneg.c: Likewise. + +2014-06-30 Christophe Lyon + * gcc.target/arm/README.neon-intrinsics: New file. * gcc.target/aarch64/neon-intrinsics/README: Likewise. * gcc.target/aarch64/neon-intrinsics/arm-neon-ref.h: Likewise. diff --git a/gcc/testsuite/gcc.target/aarch64/neon-intrinsics/unary_op.inc b/gcc/testsuite/gcc.target/aarch64/neon-intrinsics/unary_op.inc new file mode 100644 index 0000000..33f9b5f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/neon-intrinsics/unary_op.inc @@ -0,0 +1,72 @@ +/* Template file for unary operator validation. + + This file is meant to be included by the relevant test files, which + have to define the intrinsic family to test. If a given intrinsic + supports variants which are not supported by all the other unary + operators, these can be tested by providing a definition for + EXTRA_TESTS. */ + +#include +#include "arm-neon-ref.h" +#include "compute-ref-data.h" + +#define FNNAME1(NAME) exec_ ## NAME +#define FNNAME(NAME) FNNAME1(NAME) + +void FNNAME (INSN_NAME) (void) +{ + /* Basic test: y=OP(x), then store the result. */ +#define TEST_UNARY_OP1(INSN, Q, T1, T2, W, N) \ + VECT_VAR(vector_res, T1, W, N) = \ + INSN##Q##_##T2##W(VECT_VAR(vector, T1, W, N)); \ + vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vector_res, T1, W, N)) + +#define TEST_UNARY_OP(INSN, Q, T1, T2, W, N) \ + TEST_UNARY_OP1(INSN, Q, T1, T2, W, N) \ + + /* No need for 64 bits variants in the general case. */ + DECL_VARIABLE(vector, int, 8, 8); + DECL_VARIABLE(vector, int, 16, 4); + DECL_VARIABLE(vector, int, 32, 2); + DECL_VARIABLE(vector, int, 8, 16); + DECL_VARIABLE(vector, int, 16, 8); + DECL_VARIABLE(vector, int, 32, 4); + + DECL_VARIABLE(vector_res, int, 8, 8); + DECL_VARIABLE(vector_res, int, 16, 4); + DECL_VARIABLE(vector_res, int, 32, 2); + DECL_VARIABLE(vector_res, int, 8, 16); + DECL_VARIABLE(vector_res, int, 16, 8); + DECL_VARIABLE(vector_res, int, 32, 4); + + clean_results (); + + /* Initialize input "vector" from "buffer". */ + VLOAD(vector, buffer, , int, s, 8, 8); + VLOAD(vector, buffer, , int, s, 16, 4); + VLOAD(vector, buffer, , int, s, 32, 2); + VLOAD(vector, buffer, q, int, s, 8, 16); + VLOAD(vector, buffer, q, int, s, 16, 8); + VLOAD(vector, buffer, q, int, s, 32, 4); + + /* Apply a unary operator named INSN_NAME. */ + TEST_UNARY_OP(INSN_NAME, , int, s, 8, 8); + TEST_UNARY_OP(INSN_NAME, , int, s, 16, 4); + TEST_UNARY_OP(INSN_NAME, , int, s, 32, 2); + TEST_UNARY_OP(INSN_NAME, q, int, s, 8, 16); + TEST_UNARY_OP(INSN_NAME, q, int, s, 16, 8); + TEST_UNARY_OP(INSN_NAME, q, int, s, 32, 4); + + CHECK_RESULTS (TEST_MSG, ""); + +#ifdef EXTRA_TESTS + EXTRA_TESTS(); +#endif +} + +int main (void) +{ + FNNAME (INSN_NAME)(); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/neon-intrinsics/vabs.c b/gcc/testsuite/gcc.target/aarch64/neon-intrinsics/vabs.c new file mode 100644 index 0000000..ca3901a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/neon-intrinsics/vabs.c @@ -0,0 +1,74 @@ +#define INSN_NAME vabs +#define TEST_MSG "VABS/VABSQ" + +/* Extra tests for functions requiring floating-point types. */ +void exec_vabs_f32(void); +#define EXTRA_TESTS exec_vabs_f32 + +#include "unary_op.inc" + +/* Expected results. */ +VECT_VAR_DECL(expected,int,8,8) [] = { 0x10, 0xf, 0xe, 0xd, + 0xc, 0xb, 0xa, 0x9 }; +VECT_VAR_DECL(expected,int,16,4) [] = { 0x10, 0xf, 0xe, 0xd }; +VECT_VAR_DECL(expected,int,32,2) [] = { 0x10, 0xf }; +VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 }; +VECT_VAR_DECL(expected,uint,8,8) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,uint,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; +VECT_VAR_DECL(expected,uint,32,2) [] = { 0x33333333, 0x33333333 }; +VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 }; +VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 }; +VECT_VAR_DECL(expected,int,8,16) [] = { 0x10, 0xf, 0xe, 0xd, 0xc, 0xb, 0xa, 0x9, + 0x8, 0x7, 0x6, 0x5, 0x4, 0x3, 0x2, 0x1 }; +VECT_VAR_DECL(expected,int,16,8) [] = { 0x10, 0xf, 0xe, 0xd, + 0xc, 0xb, 0xa, 0x9 }; +VECT_VAR_DECL(expected,int,32,4) [] = { 0x10, 0xf, 0xe, 0xd }; +VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333, + 0x3333333333333333 }; +VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, + 0x3333, 0x3333, 0x3333, 0x3333 }; +VECT_VAR_DECL(expected,uint,32,4) [] = { 0x33333333, 0x33333333, + 0x33333333, 0x33333333 }; +VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333, + 0x3333333333333333 }; +VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, + 0x3333, 0x3333, 0x3333, 0x3333 }; +VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333, + 0x33333333, 0x33333333 }; + +/* Expected results for float32 variants. Needs to be separated since + the generic test function does not test floating-point + versions. */ +VECT_VAR_DECL(expected_float32,hfloat,32,2) [] = { 0x40133333, 0x40133333 }; +VECT_VAR_DECL(expected_float32,hfloat,32,4) [] = { 0x4059999a, 0x4059999a, + 0x4059999a, 0x4059999a }; + +void exec_vabs_f32(void) +{ + DECL_VARIABLE(vector, float, 32, 2); + DECL_VARIABLE(vector, float, 32, 4); + + DECL_VARIABLE(vector_res, float, 32, 2); + DECL_VARIABLE(vector_res, float, 32, 4); + + VDUP(vector, , float, f, 32, 2, -2.3f); + VDUP(vector, q, float, f, 32, 4, 3.4f); + + TEST_UNARY_OP(INSN_NAME, , float, f, 32, 2); + TEST_UNARY_OP(INSN_NAME, q, float, f, 32, 4); + + CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_float32, ""); + CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_float32, ""); +} diff --git a/gcc/testsuite/gcc.target/aarch64/neon-intrinsics/vneg.c b/gcc/testsuite/gcc.target/aarch64/neon-intrinsics/vneg.c new file mode 100644 index 0000000..c45492d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/neon-intrinsics/vneg.c @@ -0,0 +1,74 @@ +#define INSN_NAME vneg +#define TEST_MSG "VNEG/VNEGQ" + +/* Extra tests for functions requiring floating-point types. */ +void exec_vneg_f32(void); +#define EXTRA_TESTS exec_vneg_f32 + +#include "unary_op.inc" + +/* Expected results. */ +VECT_VAR_DECL(expected,int,8,8) [] = { 0x10, 0xf, 0xe, 0xd, + 0xc, 0xb, 0xa, 0x9 }; +VECT_VAR_DECL(expected,int,16,4) [] = { 0x10, 0xf, 0xe, 0xd }; +VECT_VAR_DECL(expected,int,32,2) [] = { 0x10, 0xf }; +VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 }; +VECT_VAR_DECL(expected,uint,8,8) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,uint,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; +VECT_VAR_DECL(expected,uint,32,2) [] = { 0x33333333, 0x33333333 }; +VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 }; +VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 }; +VECT_VAR_DECL(expected,int,8,16) [] = { 0x10, 0xf, 0xe, 0xd, 0xc, 0xb, 0xa, 0x9, + 0x8, 0x7, 0x6, 0x5, 0x4, 0x3, 0x2, 0x1 }; +VECT_VAR_DECL(expected,int,16,8) [] = { 0x10, 0xf, 0xe, 0xd, + 0xc, 0xb, 0xa, 0x9 }; +VECT_VAR_DECL(expected,int,32,4) [] = { 0x10, 0xf, 0xe, 0xd }; +VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333, + 0x3333333333333333 }; +VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, + 0x3333, 0x3333, 0x3333, 0x3333 }; +VECT_VAR_DECL(expected,uint,32,4) [] = { 0x33333333, 0x33333333, + 0x33333333, 0x33333333 }; +VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333, + 0x3333333333333333 }; +VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, + 0x3333, 0x3333, 0x3333, 0x3333 }; +VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333, + 0x33333333, 0x33333333 }; + +/* Expected results for float32 variants. Needs to be separated since + the generic test function does not test floating-point + versions. */ +VECT_VAR_DECL(expected_float32,hfloat,32,2) [] = { 0xc0133333, 0xc0133333 }; +VECT_VAR_DECL(expected_float32,hfloat,32,4) [] = { 0xc059999a, 0xc059999a, + 0xc059999a, 0xc059999a }; + +void exec_vneg_f32(void) +{ + DECL_VARIABLE(vector, float, 32, 2); + DECL_VARIABLE(vector, float, 32, 4); + + DECL_VARIABLE(vector_res, float, 32, 2); + DECL_VARIABLE(vector_res, float, 32, 4); + + VDUP(vector, , float, f, 32, 2, 2.3f); + VDUP(vector, q, float, f, 32, 4, 3.4f); + + TEST_UNARY_OP(INSN_NAME, , float, f, 32, 2); + TEST_UNARY_OP(INSN_NAME, q, float, f, 32, 4); + + CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_float32, ""); + CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_float32, ""); +}