From patchwork Thu Apr 25 10:36:36 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Greenhalgh X-Patchwork-Id: 239481 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "localhost", Issuer "www.qmailtoaster.com" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 746BF2C00BC for ; Thu, 25 Apr 2013 20:36:55 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type; q=dns; s=default; b=SvNAk9qlSYvn7edrYVw4L4S7ZHbZJUflKVYhXkYaCun079ZfYa 7AQdkFH4kGOxR1aLSPdPAsJs9Xt7CjWmfPKy+Na46vDGd/2ZqNe6Z8c/XsA0unVP Fu9OufDwwPU8APtcGMpsycsT3wwW3OLdYa4Ygj4i6NQo2rWWT/VEHWeuU= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type; s= default; bh=4N8aayWV7XMZNlL8Emto5O3DTv4=; b=eYhMQolrMGVNzA3ci/aq /kZqrWyUa/DgZdrUNyEQhlxqwOlWh1TECzfwbhIYmALW9hiB/wcEeyssyWOvq8/G XwzqYknc8Rze6+Z7g3pXTO00ZoMsK871XwgyABHx2SIjkOsbeBLowx4aM44uGl0c zEQecBncGnqOBBpdS0g+eqI= Received: (qmail 9339 invoked by alias); 25 Apr 2013 10:36:47 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 9329 invoked by uid 89); 25 Apr 2013 10:36:46 -0000 X-Spam-SWARE-Status: No, score=-2.6 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.1 Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.84/v0.84-167-ge50287c) with ESMTP; Thu, 25 Apr 2013 10:36:46 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Thu, 25 Apr 2013 11:36:43 +0100 Received: from e106375-lin.cambridge.arm.com ([10.1.255.212]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 25 Apr 2013 11:36:41 +0100 From: James Greenhalgh To: gcc-patches@gcc.gnu.org Cc: marcus/shawcroft@arm.com Subject: [AArch64] Describe the 'BSL' RTL pattern more accurately. Date: Thu, 25 Apr 2013 11:36:36 +0100 Message-Id: <1366886196-6752-1-git-send-email-james.greenhalgh@arm.com> MIME-Version: 1.0 X-MC-Unique: 113042511364311301 X-Virus-Found: No Hi, The aarch64_simd_bsl pattern performs an operation which can be described in C as: (a & b) | (~a & c) Rewriting this in RTL rather than using an UNSPEC allows for better constant folding. Regression tested for aarch64-none-elf with no regressions. OK? Thanks, James --- gcc/ 2013-04-25 James Greenhalgh * config/aarch64/aarch64-simd.md (aarch64_simd_bsl_internal): Rewrite RTL to not use UNSPEC_BSL. (aarch64_simd_bsl): Likewise. * config/aarch64/iterators.md (unspec): Remove UNSPEC_BSL. diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 42c8d68..5862d26 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1509,21 +1509,33 @@ (set_attr "simd_mode" "V2SI")] ) -;; vbsl_* intrinsics may compile to any of bsl/bif/bit depending on register -;; allocation. For an intrinsic of form: -;; vD = bsl_* (vS, vN, vM) +;; aarch64_simd_bsl may compile to any of bsl/bif/bit depending on register +;; allocation. +;; Operand 1 is the mask, operands 2 and 3 are the bitfields from which +;; to select. +;; +;; Thus our BSL is of the form: +;; op0 = bsl (mask, op2, op3) ;; We can use any of: -;; bsl vS, vN, vM (if D = S) -;; bit vD, vN, vS (if D = M, so 1-bits in vS choose bits from vN, else vM) -;; bif vD, vM, vS (if D = N, so 0-bits in vS choose bits from vM, else vN) +;; +;; if (op0 = mask) +;; bsl mask, op1, op2 +;; if (op0 = op1) (so 1-bits in mask choose bits from op2, else op0) +;; bit op0, op2, mask +;; if (op0 = op2) (so 0-bits in mask choose bits from op1, else op0) +;; bif op0, op1, mask (define_insn "aarch64_simd_bsl_internal" [(set (match_operand:VALL 0 "register_operand" "=w,w,w") - (unspec:VALL - [(match_operand: 1 "register_operand" " 0,w,w") - (match_operand:VALL 2 "register_operand" " w,w,0") - (match_operand:VALL 3 "register_operand" " w,0,w")] - UNSPEC_BSL))] + (ior:VALL + (and:VALL + (match_operand: 1 "register_operand" " 0,w,w") + (match_operand:VALL 2 "register_operand" " w,w,0")) + (and:VALL + (not: + (match_dup: 1)) + (match_operand:VALL 3 "register_operand" " w,0,w")) + ))] "TARGET_SIMD" "@ bsl\\t%0., %2., %3. @@ -1532,15 +1544,17 @@ ) (define_expand "aarch64_simd_bsl" - [(set (match_operand:VALL 0 "register_operand") - (unspec:VALL [(match_operand: 1 "register_operand") - (match_operand:VALL 2 "register_operand") - (match_operand:VALL 3 "register_operand")] - UNSPEC_BSL))] - "TARGET_SIMD" + [(match_operand:VALL 0 "register_operand") + (match_operand: 1 "register_operand") + (match_operand:VALL 2 "register_operand") + (match_operand:VALL 3 "register_operand")] + "TARGET_SIMD" { /* We can't alias operands together if they have different modes. */ operands[1] = gen_lowpart (mode, operands[1]); + emit_insn (gen_aarch64_simd_bsl_internal (operands[0], operands[1], + operands[2], operands[3])); + DONE; }) (define_expand "aarch64_vcond_internal" diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 017e128..58a2a9e 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -230,7 +230,6 @@ UNSPEC_CMTST ; Used in aarch64-simd.md. UNSPEC_FMAX ; Used in aarch64-simd.md. UNSPEC_FMIN ; Used in aarch64-simd.md. - UNSPEC_BSL ; Used in aarch64-simd.md. UNSPEC_TBL ; Used in vector permute patterns. UNSPEC_CONCAT ; Used in vector permute patterns. UNSPEC_ZIP1 ; Used in vector permute patterns.