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[3/3] lt0_disi

Message ID 1286bfa08e97c91f44b81556a3d26d2100c76fc5.1437404024.git.segher@kernel.crashing.org
State New
Headers show

Commit Message

Segher Boessenkool July 20, 2015, 4:04 p.m. UTC 
After Kyrill's patch (r225996) (changing combine to do simplification
before doing some transformations) a shortcoming of the rs6000 backend
becomes obvious: we have no patterns to handle

	(set (reg:DI) (lt:DI (reg:SI) (const_int 0)))

although we can do that with a single rotate-and-mask instruction.
Previously, combine usually came up with a more complex pattern (that
we do implement), hiding the issue.

This patch adds a define_insn for the pattern.


2015-07-20  Segher Boessenkool  <segher@kernel.crashing.org>

	* config/rs6000/rs6000.md (*lt0_disi): New.

---
 gcc/config/rs6000/rs6000.md | 11 +++++++++++
 1 file changed, 11 insertions(+)

Comments

David Edelsohn July 20, 2015, 4:19 p.m. UTC | #1 
On Mon, Jul 20, 2015 at 12:04 PM, Segher Boessenkool
<segher@kernel.crashing.org> wrote:
> After Kyrill's patch (r225996) (changing combine to do simplification
> before doing some transformations) a shortcoming of the rs6000 backend
> becomes obvious: we have no patterns to handle
>
>         (set (reg:DI) (lt:DI (reg:SI) (const_int 0)))
>
> although we can do that with a single rotate-and-mask instruction.
> Previously, combine usually came up with a more complex pattern (that
> we do implement), hiding the issue.
>
> This patch adds a define_insn for the pattern.
>
>
> 2015-07-20  Segher Boessenkool  <segher@kernel.crashing.org>
>
>         * config/rs6000/rs6000.md (*lt0_disi): New.

This is okay.

Thanks, David
diff mbox

Patch

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 5727068..55ceb66 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -3475,6 +3475,17 @@  (define_insn_and_split "*rotl<mode>3_mask_dot2"
    (set_attr "dot" "yes")
    (set_attr "length" "4,8")])
 
+; Special case for less-than-0.  We can do it with just one machine
+; instruction, but the generic optimizers do not realise it is cheap.
+(define_insn "*lt0_disi"
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(lt:DI (match_operand:SI 1 "gpc_reg_operand" "r")
+	       (const_int 0)))]
+  "TARGET_POWERPC64"
+  "rlwinm %0,%1,1,31,31"
+  [(set_attr "type" "shift")])
+
+
 
 ; Two forms for insert (the two arms of the IOR are not canonicalized,
 ; both are an AND so are the same precedence).