From patchwork Wed Jun 18 14:14:01 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Segher Boessenkool X-Patchwork-Id: 361509 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 170A2140078 for ; Thu, 19 Jun 2014 00:17:32 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; q=dns; s=default; b=aEewYJtsuCyx cES5uW+5HnNpT63l0rRhT37IuxEk8DLvfqoWMzBpSJTf48qbtAP56ycOJ8l+/RPJ qOUHh27/5Mv7N9N2pWEdj/iNfdgeOEchQqya3h8v+T16AeEfpasdlGq3f4++unRi 34H6gK6mGyR6ZQeh1CV2Nsd+XqrOU7U= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; s=default; bh=c5DTLMFzTWSMt8iO7l 726wlsd68=; b=x8s2greLS28s0hLovuxwRHQMT3OK1PHtlT7M9yvOUyY+wW62Gu 3hYI0kA+RvSJHdbH3sLHEj1Qq7vfOKkpM4krh4ZuKIK6eP4K31PeAg/F4wNPmc5y S98+RwkOVu5iovqePld+AHaJb/mn3P0ePw8c6n4KUHuVh45F+NVQrgsXs= Received: (qmail 6233 invoked by alias); 18 Jun 2014 14:17:26 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 6219 invoked by uid 89); 18 Jun 2014 14:17:25 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=AWL, BAYES_00, T_RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: gcc1-power7.osuosl.org Received: from gcc1-power7.osuosl.org (HELO gcc1-power7.osuosl.org) (140.211.15.137) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-GCM-SHA384 encrypted) ESMTPS; Wed, 18 Jun 2014 14:17:23 +0000 Received: from gcc1-power7.osuosl.org (localhost [127.0.0.1]) by gcc1-power7.osuosl.org (8.14.6/8.14.6) with ESMTP id s5IEE7lb024167; Wed, 18 Jun 2014 07:14:07 -0700 Received: (from segher@localhost) by gcc1-power7.osuosl.org (8.14.6/8.14.6/Submit) id s5IEE5Tc023509; Wed, 18 Jun 2014 07:14:05 -0700 From: Segher Boessenkool To: gcc-patches@gcc.gnu.org Cc: dje.gcc@gmail.com, Segher Boessenkool Subject: [PATCH] rs6000: Make cr5 allocatable Date: Wed, 18 Jun 2014 07:14:01 -0700 Message-Id: <10adfaa86a60b1bc978aa12fa58023ad5a1c4ea3.1403098217.git.segher@kernel.crashing.org> X-IsSubscribed: yes A comment in rs6000.h says "cr5 is not supposed to be used". I checked all ABIs, going as far back as PowerOpen (1994), and found no mention of this. Also document cr6 is used by some vector instructions. Tested on powerpc64-linux, no regressions. Okay to apply? Segher 2014-06-18 Segher Boessenkool gcc/ * config/rs6000/rs6000.h (FIXED_REGISTERS): Update comment. Remove cr5. (REG_ALLOC_ORDER): Update comment. Move cr5 earlier. --- gcc/config/rs6000/rs6000.h | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 3bd0104..569ae2d 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -978,8 +978,6 @@ enum data_align { align_abi, align_opt, align_both }; On RS/6000, r1 is used for the stack. On Darwin, r2 is available as a local register; for all other OS's r2 is the TOC pointer. - cr5 is not supposed to be used. - On System V implementations, r13 is fixed and not available for use. */ #define FIXED_REGISTERS \ @@ -987,7 +985,7 @@ enum data_align { align_abi, align_opt, align_both }; 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, \ + 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ /* AltiVec registers. */ \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -1048,7 +1046,8 @@ enum data_align { align_abi, align_opt, align_both }; fp13 - fp2 (not saved; incoming fp arg registers) fp1 (not saved; return value) fp31 - fp14 (saved; order given to save least number) - cr7, cr6 (not saved or special) + cr7, cr5 (not saved or special) + cr6 (not saved, but used for vector operations) cr1 (not saved, but used for FP operations) cr0 (not saved, but used for arithmetic operations) cr4, cr3, cr2 (saved) @@ -1061,7 +1060,7 @@ enum data_align { align_abi, align_opt, align_both }; r12 (not saved; if used for DImode or DFmode would use r13) ctr (not saved; when we have the choice ctr is better) lr (saved) - cr5, r1, r2, ap, ca (fixed) + r1, r2, ap, ca (fixed) v0 - v1 (not saved or used for anything) v13 - v3 (not saved; incoming vector arg registers) v2 (not saved; incoming vector arg reg; return value) @@ -1099,14 +1098,14 @@ enum data_align { align_abi, align_opt, align_both }; 33, \ 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \ 50, 49, 48, 47, 46, \ - 75, 74, 69, 68, 72, 71, 70, \ + 75, 73, 74, 69, 68, 72, 71, 70, \ MAYBE_R2_AVAILABLE \ 9, 10, 8, 7, 6, 5, 4, \ 3, EARLY_R12 11, 0, \ 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \ 18, 17, 16, 15, 14, 13, LATE_R12 \ 66, 65, \ - 73, 1, MAYBE_R2_FIXED 67, 76, \ + 1, MAYBE_R2_FIXED 67, 76, \ /* AltiVec registers. */ \ 77, 78, \ 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \