From patchwork Wed Jun 14 11:24:16 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Botcazou X-Patchwork-Id: 775743 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3wnknX6c3Sz9s3s for ; Wed, 14 Jun 2017 21:25:04 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="KkOHHLnU"; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type :content-transfer-encoding; q=dns; s=default; b=cCfHEAivqO4VMt7r CE4UpP9rijnHEW60sCvxeRrZEpx5sEbMHaI0l9mbF1K7Q/flf7fyfhn+Yi5Ju+XX 6DTQlEkGIF6UwCmoUEQEnWALIWTx9vD1r0XC5+U7Y/ZNHjFRMsQNLi6T0+yKL6MX 3Y1i9cULb1CCbyeLlSfCf8kXjqw= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type :content-transfer-encoding; s=default; bh=ZPLSt8Zo+n9yblp9FHwRXP iqF4c=; b=KkOHHLnUfbPoZ09EsEMKMhdJJb6NJKQjiAO8ekjUpjDhbasg0EWDsI pP9rmnyjLVFzKpgHTmOqmzMM3q3f6a5/4XwwoAuxq/xAQs5fva8hPOoIRca2O8Lo rkdFv+ESXl5ZvrbskWlgNsY7vezjM9L631Em0K8iumgf9XMbuCkQQ= Received: (qmail 116042 invoked by alias); 14 Jun 2017 11:24:35 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 102085 invoked by uid 89); 14 Jun 2017 11:24:22 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-10.2 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: smtp.eu.adacore.com Received: from mel.act-europe.fr (HELO smtp.eu.adacore.com) (194.98.77.210) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 14 Jun 2017 11:24:20 +0000 Received: from localhost (localhost [127.0.0.1]) by filtered-smtp.eu.adacore.com (Postfix) with ESMTP id 8598A8144E for ; Wed, 14 Jun 2017 13:24:17 +0200 (CEST) Received: from smtp.eu.adacore.com ([127.0.0.1]) by localhost (smtp.eu.adacore.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id xDC3g-6E9Zwy for ; Wed, 14 Jun 2017 13:24:17 +0200 (CEST) Received: from polaris.localnet (bon31-6-88-161-99-133.fbx.proxad.net [88.161.99.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.eu.adacore.com (Postfix) with ESMTPSA id 5D53F8144C for ; Wed, 14 Jun 2017 13:24:17 +0200 (CEST) From: Eric Botcazou To: gcc-patches@gcc.gnu.org Subject: [SPARC] Do not let -mcpu override -mno-xxx switches Date: Wed, 14 Jun 2017 13:24:16 +0200 Message-ID: <10329374.8GVXEQPUUt@polaris> User-Agent: KMail/4.14.10 (Linux/3.16.7-53-desktop; KDE/4.14.9; x86_64; ; ) MIME-Version: 1.0 -mcpu automatically enables features that have a specific -mxxx switch, even if the corresponding -mno-xxx switch is specified. The only exception is the -mfpu/-mno-fpu switch. This patch adds more exceptions (-mhard-float, -mvis, -mvis2, -mvis3, -mvis4, -mcbcond, -mfmaf, -mpopc and -msubxc) and fixes gcc.target/sparc/overflow-4.c with -mcpu=niagara3 or later. Tested on SPARC64/Linux, applied on mainline and 7 branch. 2017-06-14 Eric Botcazou * config/sparc/sparc.h (MASK_ISA): Add MASK_LEON and MASK_LEON3. (MASK_FEATURES): New macro. * config/sparc/sparc.c (sparc_option_override): Remove the special handling of -mfpu and generalize it to all MASK_FEATURES switches. 2017-06-14 Eric Botcazou * gcc.target/sparc/overflow-4.c: Add -mno-vis3. Index: config/sparc/sparc.c =================================================================== --- config/sparc/sparc.c (revision 249091) +++ config/sparc/sparc.c (working copy) @@ -1341,7 +1341,6 @@ sparc_option_override (void) }; const struct cpu_table *cpu; unsigned int i; - int fpu; if (sparc_debug_string != NULL) { @@ -1433,8 +1432,6 @@ sparc_option_override (void) call_used_regs [i] = 1; } - fpu = target_flags & MASK_FPU; /* save current -mfpu status */ - /* Set the default CPU. */ if (!global_options_set.x_sparc_cpu_and_features) { @@ -1473,22 +1470,18 @@ sparc_option_override (void) #ifndef HAVE_AS_LEON & ~(MASK_LEON | MASK_LEON3) #endif + & ~(target_flags_explicit & MASK_FEATURES) ); - /* If -mfpu or -mno-fpu was explicitly used, don't override with - the processor default. */ - if (target_flags_explicit & MASK_FPU) - target_flags = (target_flags & ~MASK_FPU) | fpu; - - /* -mvis2 implies -mvis */ + /* -mvis2 implies -mvis. */ if (TARGET_VIS2) target_flags |= MASK_VIS; - /* -mvis3 implies -mvis2 and -mvis */ + /* -mvis3 implies -mvis2 and -mvis. */ if (TARGET_VIS3) target_flags |= MASK_VIS2 | MASK_VIS; - /* -mvis4 implies -mvis3, -mvis2 and -mvis */ + /* -mvis4 implies -mvis3, -mvis2 and -mvis. */ if (TARGET_VIS4) target_flags |= MASK_VIS3 | MASK_VIS2 | MASK_VIS; @@ -1499,15 +1492,14 @@ sparc_option_override (void) | MASK_FMAF); /* -mvis assumes UltraSPARC+, so we are sure v9 instructions - are available. - -m64 also implies v9. */ + are available; -m64 also implies v9. */ if (TARGET_VIS || TARGET_ARCH64) { target_flags |= MASK_V9; target_flags &= ~(MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE); } - /* -mvis also implies -mv8plus on 32-bit */ + /* -mvis also implies -mv8plus on 32-bit. */ if (TARGET_VIS && ! TARGET_ARCH64) target_flags |= MASK_V8PLUS; Index: config/sparc/sparc.h =================================================================== --- config/sparc/sparc.h (revision 249091) +++ config/sparc/sparc.h (working copy) @@ -423,10 +423,15 @@ extern enum cmodel sparc_cmodel; #define WCHAR_TYPE_SIZE 16 /* Mask of all CPU selection flags. */ -#define MASK_ISA \ - (MASK_SPARCLITE + MASK_SPARCLET \ +#define MASK_ISA \ + (MASK_SPARCLITE + MASK_SPARCLET + MASK_LEON + MASK_LEON3 \ + MASK_V8 + MASK_V9 + MASK_DEPRECATED_V8_INSNS) +/* Mask of all CPU feature flags. */ +#define MASK_FEATURES \ + (MASK_FPU + MASK_HARD_QUAD + MASK_VIS + MASK_VIS2 + MASK_VIS3 \ + + MASK_VIS4 + MASK_CBCOND + MASK_FMAF + MASK_POPC + MASK_SUBXC) + /* TARGET_HARD_MUL: Use 32-bit hardware multiply instructions but not %y. */ #define TARGET_HARD_MUL \ (TARGET_SPARCLITE || TARGET_SPARCLET \ Index: testsuite/gcc.target/sparc/overflow-4.c =================================================================== --- testsuite/gcc.target/sparc/overflow-4.c (revision 249091) +++ testsuite/gcc.target/sparc/overflow-4.c (working copy) @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O" } */ +/* { dg-options "-O -mno-vis3" } */ /* { dg-require-effective-target lp64 } */ #include