[rs6000] Don't set MMA prefixed instruction length to 8

Message ID	0fdb90a0-74c3-fa7a-4acb-da161fb03187@linux.ibm.com
State	New
Headers	show Return-Path: <gcc-patches-bounces@gcc.gnu.org> DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org AE7333858D29 To: GCC Patches <gcc-patches@gcc.gnu.org> Subject: [PATCH, rs6000] Don't set MMA prefixed instruction length to 8 Message-ID: <0fdb90a0-74c3-fa7a-4acb-da161fb03187@linux.ibm.com> Date: Mon, 14 Dec 2020 16:23:48 -0600 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.16; rv:78.0) Gecko/20100101 Thunderbird/78.5.0 MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="------------63AC20C91F9F7E0B6CAD0654" Content-Language: en-US Precedence: list From: Pat Haugen via Gcc-patches <gcc-patches@gcc.gnu.org> Reply-To: Pat Haugen <pthaugen@linux.ibm.com> Cc: Bill Schmidt <wschmidt@linux.ibm.com>, David Edelsohn <dje.gcc@gmail.com>, Segher Boessenkool <segher@kernel.crashing.org> Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" <gcc-patches-bounces@gcc.gnu.org>
Series	[rs6000] Don't set MMA prefixed instruction length to 8 \| expand [rs6000] Don't set MMA prefixed instruction length to 8

Message ID

0fdb90a0-74c3-fa7a-4acb-da161fb03187@linux.ibm.com

State

New

Headers

DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org AE7333858D29
To: GCC Patches <gcc-patches@gcc.gnu.org>
Subject: [PATCH, rs6000] Don't set MMA prefixed instruction length to 8
Message-ID: <0fdb90a0-74c3-fa7a-4acb-da161fb03187@linux.ibm.com>
Date: Mon, 14 Dec 2020 16:23:48 -0600
User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.16; rv:78.0)
 Gecko/20100101 Thunderbird/78.5.0
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Content-Type: multipart/mixed; boundary="------------63AC20C91F9F7E0B6CAD0654"
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Precedence: list
From: Pat Haugen via Gcc-patches <gcc-patches@gcc.gnu.org>
Reply-To: Pat Haugen <pthaugen@linux.ibm.com>
Cc: Bill Schmidt <wschmidt@linux.ibm.com>, David Edelsohn <dje.gcc@gmail.com>,
 Segher Boessenkool <segher@kernel.crashing.org>
Errors-To: gcc-patches-bounces@gcc.gnu.org
Sender: "Gcc-patches" <gcc-patches-bounces@gcc.gnu.org>

Series

[rs6000] Don't set MMA prefixed instruction length to 8 | expand

Commit Message

Pat Haugen Dec. 14, 2020, 10:23 p.m. UTC

Fix instruction length for MMA insns.


Prefixed instructions should not have their length explicitly set to '8'. The function get_attr_length() will adjust the length appropriately based on the value of the "prefixed" attribute.

Bootstrap/regtest on powerpc64le (Power8/Power10) with no new regressions. Ok for trunk?

-Pat


2020-12-14  Pat Haugen  <pthaugen@linux.ibm.com>

gcc/
	* config/rs6000/mma.md (*movxo, mma_<vvi4i4i8>, mma_<avvi4i4i8>,
	mma_<vvi4i4i2>, mma_<avvi4i4i2>, mma_<vvi4i4>, mma_<avvi4i4>,
	mma_<pvi4i2>, mma_<apvi4i2>, mma_<vvi4i4i4>, mma_<avvi4i4i4>):
	Remove explicit setting of length attribute.

Comments

Segher Boessenkool Dec. 16, 2020, 11:41 a.m. UTC | #1

On Mon, Dec 14, 2020 at 04:23:48PM -0600, Pat Haugen wrote:
> Prefixed instructions should not have their length explicitly set to '8'. The function get_attr_length() will adjust the length appropriately based on the value of the "prefixed" attribute.
> 
> Bootstrap/regtest on powerpc64le (Power8/Power10) with no new regressions. Ok for trunk?

Okay for trunk.  Thanks!


Segher

diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md
index 4d291c42f7a..ef4394416b6 100644
--- a/gcc/config/rs6000/mma.md
+++ b/gcc/config/rs6000/mma.md
@@ -318,7 +318,7 @@  (define_insn_and_split "*movxo"
   DONE;
 }
   [(set_attr "type" "vecload,vecstore,veclogical")
-   (set_attr "length" "8,8,16")
+   (set_attr "length" "*,*,16")
    (set_attr "max_prefixed_insns" "2,2,*")])
 
 (define_expand "mma_assemble_pair"
@@ -539,8 +539,7 @@  (define_insn "mma_<vvi4i4i8>"
 		    MMA_VVI4I4I8))]
   "TARGET_MMA"
   "<vvi4i4i8> %A0,%x1,%x2,%3,%4,%5"
-  [(set_attr "type" "mma")
-   (set_attr "length" "8")])
+  [(set_attr "type" "mma")])
 
 (define_insn "mma_<avvi4i4i8>"
   [(set (match_operand:XO 0 "fpr_reg_operand" "=&d")
@@ -553,8 +552,7 @@  (define_insn "mma_<avvi4i4i8>"
 		    MMA_AVVI4I4I8))]
   "TARGET_MMA"
   "<avvi4i4i8> %A0,%x2,%x3,%4,%5,%6"
-  [(set_attr "type" "mma")
-   (set_attr "length" "8")])
+  [(set_attr "type" "mma")])
 
 (define_insn "mma_<vvi4i4i2>"
   [(set (match_operand:XO 0 "fpr_reg_operand" "=&d")
@@ -566,8 +564,7 @@  (define_insn "mma_<vvi4i4i2>"
 		    MMA_VVI4I4I2))]
   "TARGET_MMA"
   "<vvi4i4i2> %A0,%x1,%x2,%3,%4,%5"
-  [(set_attr "type" "mma")
-   (set_attr "length" "8")])
+  [(set_attr "type" "mma")])
 
 (define_insn "mma_<avvi4i4i2>"
   [(set (match_operand:XO 0 "fpr_reg_operand" "=&d")
@@ -580,8 +577,7 @@  (define_insn "mma_<avvi4i4i2>"
 		    MMA_AVVI4I4I2))]
   "TARGET_MMA"
   "<avvi4i4i2> %A0,%x2,%x3,%4,%5,%6"
-  [(set_attr "type" "mma")
-   (set_attr "length" "8")])
+  [(set_attr "type" "mma")])
 
 (define_insn "mma_<vvi4i4>"
   [(set (match_operand:XO 0 "fpr_reg_operand" "=&d")
@@ -592,8 +588,7 @@  (define_insn "mma_<vvi4i4>"
 		    MMA_VVI4I4))]
   "TARGET_MMA"
   "<vvi4i4> %A0,%x1,%x2,%3,%4"
-  [(set_attr "type" "mma")
-   (set_attr "length" "8")])
+  [(set_attr "type" "mma")])
 
 (define_insn "mma_<avvi4i4>"
   [(set (match_operand:XO 0 "fpr_reg_operand" "=&d")
@@ -605,8 +600,7 @@  (define_insn "mma_<avvi4i4>"
 		    MMA_AVVI4I4))]
   "TARGET_MMA"
   "<avvi4i4> %A0,%x2,%x3,%4,%5"
-  [(set_attr "type" "mma")
-   (set_attr "length" "8")])
+  [(set_attr "type" "mma")])
 
 (define_insn "mma_<pvi4i2>"
   [(set (match_operand:XO 0 "fpr_reg_operand" "=&d")
@@ -617,8 +611,7 @@  (define_insn "mma_<pvi4i2>"
 		    MMA_PVI4I2))]
   "TARGET_MMA"
   "<pvi4i2> %A0,%x1,%x2,%3,%4"
-  [(set_attr "type" "mma")
-   (set_attr "length" "8")])
+  [(set_attr "type" "mma")])
 
 (define_insn "mma_<apvi4i2>"
   [(set (match_operand:XO 0 "fpr_reg_operand" "=&d")
@@ -630,8 +623,7 @@  (define_insn "mma_<apvi4i2>"
 		    MMA_APVI4I2))]
   "TARGET_MMA"
   "<apvi4i2> %A0,%x2,%x3,%4,%5"
-  [(set_attr "type" "mma")
-   (set_attr "length" "8")])
+  [(set_attr "type" "mma")])
 
 (define_insn "mma_<vvi4i4i4>"
   [(set (match_operand:XO 0 "fpr_reg_operand" "=&d")
@@ -643,8 +635,7 @@  (define_insn "mma_<vvi4i4i4>"
 		    MMA_VVI4I4I4))]
   "TARGET_MMA"
   "<vvi4i4i4> %A0,%x1,%x2,%3,%4,%5"
-  [(set_attr "type" "mma")
-   (set_attr "length" "8")])
+  [(set_attr "type" "mma")])
 
 (define_insn "mma_<avvi4i4i4>"
   [(set (match_operand:XO 0 "fpr_reg_operand" "=&d")
@@ -657,5 +648,4 @@  (define_insn "mma_<avvi4i4i4>"
 		    MMA_AVVI4I4I4))]
   "TARGET_MMA"
   "<avvi4i4i4> %A0,%x2,%x3,%4,%5,%6"
-  [(set_attr "type" "mma")
-   (set_attr "length" "8")])
+  [(set_attr "type" "mma")])