===================================================================
@@ -633,6 +633,9 @@ reset_float_format (const char *name, co
For now, we do not attempt to narrow down their bit sizes. */
#define PARTIAL_INT_MODE(M) \
make_partial_integer_mode (#M, "P" #M, -1U, __FILE__, __LINE__)
+/* Partial integer modes are specified by relation to a full integer mode. */
+#define PARTIAL_INT_MODE_N(M,PREC) \
+ make_partial_integer_mode (#M, "P" #PREC #M, PREC, __FILE__, __LINE__)
static void ATTRIBUTE_UNUSED
make_partial_integer_mode (const char *base, const char *name,
unsigned int precision,
@@ -669,7 +672,7 @@ make_vector_mode (enum mode_class bclass
struct mode_data *v;
enum mode_class vclass = vector_class (bclass);
struct mode_data *component = find_mode (base);
- char namebuf[8];
+ char namebuf[16];
if (vclass == MODE_RANDOM)
return;
@@ -917,7 +920,7 @@ enum machine_mode\n{");
end will try to use it for bitfields in structures and the
like, which we do not want. Only the target md file should
generate BImode widgets. */
- if (first && first->precision == 1)
+ if (first && first->precision == 1 && c == MODE_INT)
first = first->next;
if (first && last)
@@ -1187,7 +1190,7 @@ emit_class_narrowest_mode (void)
/* Bleah, all this to get the comment right for MIN_MODE_INT. */
tagged_printf ("MIN_%s", mode_class_names[c],
modes[c]
- ? (modes[c]->precision != 1
+ ? ((c != MODE_INT || modes[c]->precision != 1)
? modes[c]->name
: (modes[c]->next
? modes[c]->next->name
===================================================================
@@ -42,7 +42,7 @@ VECTOR_MODES (FLOAT, 8); /*
VECTOR_MODES (FLOAT, 16); /* V8HF V4SF V2DF */
VECTOR_MODES (FLOAT, 32); /* V16HF V8SF V4DF */
-/* Replacement for TImode that only is allowed in GPRs. We also use PTImode
- for quad memory atomic operations to force getting an even/odd register
- combination. */
-PARTIAL_INT_MODE (TI);
+/* Replacement for TImode that only is allowed in GPRs. We also use
+ P128TImode for quad memory atomic operations to force getting an
+ even/odd register combination. */
+PARTIAL_INT_MODE_N (TI, 128);
===================================================================
@@ -1613,11 +1613,12 @@ rs6000_hard_regno_mode_ok (int regno, en
{
int last_regno = regno + rs6000_hard_regno_nregs[mode][regno] - 1;
- /* PTImode can only go in GPRs. Quad word memory operations require even/odd
- register combinations, and use PTImode where we need to deal with quad
- word memory operations. Don't allow quad words in the argument or frame
- pointer registers, just registers 0..31. */
- if (mode == PTImode)
+ /* P128TImode can only go in GPRs. Quad word memory operations
+ require even/odd register combinations, and use P128TImode where
+ we need to deal with quad word memory operations. Don't allow
+ quad words in the argument or frame pointer registers, just
+ registers 0..31. */
+ if (mode == P128TImode)
return (IN_RANGE (regno, FIRST_GPR_REGNO, LAST_GPR_REGNO)
&& IN_RANGE (last_regno, FIRST_GPR_REGNO, LAST_GPR_REGNO)
&& ((regno & 1) == 0));
@@ -1678,8 +1679,9 @@ rs6000_hard_regno_mode_ok (int regno, en
if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
return 1;
- /* We cannot put non-VSX TImode or PTImode anywhere except general register
- and it must be able to fit within the register set. */
+ /* We cannot put non-VSX TImode or P128TImode anywhere except
+ general register and it must be able to fit within the register
+ set. */
return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
}
@@ -1807,7 +1809,7 @@ rs6000_debug_reg_global (void)
SImode,
DImode,
TImode,
- PTImode,
+ P128TImode,
SFmode,
DFmode,
TFmode,
@@ -5398,7 +5400,7 @@ invalid_e500_subreg (rtx op, enum machin
purpose. */
if (GET_CODE (op) == SUBREG
&& (mode == SImode || mode == DImode || mode == TImode
- || mode == DDmode || mode == TDmode || mode == PTImode)
+ || mode == DDmode || mode == TDmode || mode == P128TImode)
&& REG_P (SUBREG_REG (op))
&& (GET_MODE (SUBREG_REG (op)) == DFmode
|| GET_MODE (SUBREG_REG (op)) == TFmode))
@@ -5411,7 +5413,7 @@ invalid_e500_subreg (rtx op, enum machin
&& REG_P (SUBREG_REG (op))
&& (GET_MODE (SUBREG_REG (op)) == DImode
|| GET_MODE (SUBREG_REG (op)) == TImode
- || GET_MODE (SUBREG_REG (op)) == PTImode
+ || GET_MODE (SUBREG_REG (op)) == P128TImode
|| GET_MODE (SUBREG_REG (op)) == DDmode
|| GET_MODE (SUBREG_REG (op)) == TDmode))
return true;
@@ -6021,7 +6023,7 @@ rs6000_legitimate_offset_address_p (enum
case TFmode:
case TDmode:
case TImode:
- case PTImode:
+ case P128TImode:
if (TARGET_E500_DOUBLE)
return (SPE_CONST_OFFSET_OK (offset)
&& SPE_CONST_OFFSET_OK (offset + 8));
@@ -6198,12 +6200,12 @@ rs6000_legitimize_address (rtx x, rtx ol
case TFmode:
case TDmode:
case TImode:
- case PTImode:
+ case P128TImode:
/* As in legitimate_offset_address_p we do not assume
worst-case. The mode here is just a hint as to the registers
used. A TImode is usually in gprs, but may actually be in
fprs. Leave worst-case scenario for reload to handle via
- insn constraints. PTImode is only GPRs. */
+ insn constraints. P128TImode is only GPRs. */
extra = 8;
break;
default:
@@ -6989,7 +6991,7 @@ rs6000_legitimize_reload_address (rtx x,
&& mode != TFmode
&& mode != TDmode
&& (mode != TImode || !TARGET_VSX_TIMODE)
- && mode != PTImode
+ && mode != P128TImode
&& (mode != DImode || TARGET_POWERPC64)
&& ((mode != DFmode && mode != DDmode) || TARGET_POWERPC64
|| (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)))
@@ -7116,7 +7118,7 @@ rs6000_legitimate_address_p (enum machin
&& mode != TFmode
&& mode != TDmode
&& mode != TImode
- && mode != PTImode
+ && mode != P128TImode
/* Restrict addressing for DI because of our SUBREG hackery. */
&& !(TARGET_E500_DOUBLE
&& (mode == DFmode || mode == DDmode || mode == DImode))
@@ -7156,13 +7158,13 @@ rs6000_legitimate_address_p (enum machin
|| (TARGET_E500_DOUBLE && mode != DDmode))
&& (TARGET_POWERPC64 || mode != DImode)
&& (mode != TImode || VECTOR_MEM_VSX_P (TImode))
- && mode != PTImode
+ && mode != P128TImode
&& !avoiding_indexed_address_p (mode)
&& legitimate_indexed_address_p (x, reg_ok_strict))
return 1;
if (GET_CODE (x) == PRE_MODIFY
&& mode != TImode
- && mode != PTImode
+ && mode != P128TImode
&& mode != TFmode
&& mode != TDmode
&& ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
@@ -7584,8 +7586,8 @@ rs6000_emit_set_long_const (rtx dest, HO
return dest;
}
-/* Helper for the following. Get rid of [r+r] memory refs
- in cases where it won't work (TImode, TFmode, TDmode, PTImode). */
+/* Helper for the following. Get rid of [r+r] memory refs in cases
+ where it won't work (TImode, TFmode, TDmode, P128TImode). */
static void
rs6000_eliminate_indexed_memrefs (rtx operands[2])
@@ -7973,7 +7975,7 @@ rs6000_emit_move (rtx dest, rtx source,
rs6000_eliminate_indexed_memrefs (operands);
break;
- case PTImode:
+ case P128TImode:
rs6000_eliminate_indexed_memrefs (operands);
break;
@@ -14900,7 +14902,7 @@ rs6000_secondary_reload (bool in_p,
}
else if (!legitimate_indirect_address_p (addr, false)
- && !rs6000_legitimate_offset_address_p (PTImode, addr,
+ && !rs6000_legitimate_offset_address_p (P128TImode, addr,
false, true))
{
sri->icode = icode;
@@ -15184,7 +15186,7 @@ rs6000_secondary_reload_inner (rtx reg,
if (GET_CODE (addr) == PLUS
&& (and_op2 != NULL_RTX
- || !rs6000_legitimate_offset_address_p (PTImode, addr,
+ || !rs6000_legitimate_offset_address_p (P128TImode, addr,
false, true)))
{
addr_op1 = XEXP (addr, 0);
@@ -15218,7 +15220,7 @@ rs6000_secondary_reload_inner (rtx reg,
scratch_or_premodify = scratch;
}
else if (!legitimate_indirect_address_p (addr, false)
- && !rs6000_legitimate_offset_address_p (PTImode, addr,
+ && !rs6000_legitimate_offset_address_p (P128TImode, addr,
false, true))
{
if (TARGET_DEBUG_ADDR)
@@ -16682,7 +16684,7 @@ print_operand (FILE *file, rtx x, int co
return;
case 'Y':
- /* Like 'L', for third word of TImode/PTImode */
+ /* Like 'L', for third word of TImode/P128TImode */
if (REG_P (x))
fputs (reg_names[REGNO (x) + 2], file);
else if (MEM_P (x))
@@ -16727,7 +16729,7 @@ print_operand (FILE *file, rtx x, int co
return;
case 'Z':
- /* Like 'L', for last word of TImode/PTImode. */
+ /* Like 'L', for last word of TImode/P128TImode. */
if (REG_P (x))
fputs (reg_names[REGNO (x) + 3], file);
else if (MEM_P (x))
@@ -16759,7 +16761,7 @@ print_operand (FILE *file, rtx x, int co
&& (GET_MODE_SIZE (GET_MODE (x)) == 8
|| GET_MODE (x) == TFmode
|| GET_MODE (x) == TImode
- || GET_MODE (x) == PTImode))
+ || GET_MODE (x) == P128TImode))
{
/* Handle [reg]. */
if (REG_P (tmp))
===================================================================
@@ -1187,13 +1187,13 @@ enum data_align { align_abi, align_opt,
If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
for any hard reg, then this must be 0 for correct output.
- PTImode cannot tie with other modes because PTImode is restricted to even
- GPR registers, and TImode can go in any GPR as well as VSX registers (PR
- 57744). */
+ P128TImode cannot tie with other modes because P128TImode is
+ restricted to even GPR registers, and TImode can go in any GPR as
+ well as VSX registers (PR 57744). */
#define MODES_TIEABLE_P(MODE1, MODE2) \
- ((MODE1) == PTImode \
- ? (MODE2) == PTImode \
- : (MODE2) == PTImode \
+ ((MODE1) == P128TImode \
+ ? (MODE2) == P128TImode \
+ : (MODE2) == P128TImode \
? 0 \
: SCALAR_FLOAT_MODE_P (MODE1) \
? SCALAR_FLOAT_MODE_P (MODE2) \
@@ -1598,7 +1598,7 @@ extern enum reg_class rs6000_constraints
NONLOCAL needs twice Pmode to maintain both backchain and SP. */
#define STACK_SAVEAREA_MODE(LEVEL) \
(LEVEL == SAVE_FUNCTION ? VOIDmode \
- : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : PTImode) : Pmode)
+ : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : P128TImode) : Pmode)
/* Minimum and maximum general purpose registers used to hold arguments. */
#define GP_ARG_MIN_REG 3
===================================================================
@@ -204,7 +204,7 @@
"<QHI:larx> %0,%y1"
[(set_attr "type" "load_l")])
-;; Use PTImode to get even/odd register pairs
+;; Use P128TImode to get even/odd register pairs
(define_expand "load_lockedti"
[(use (match_operand:TI 0 "quad_int_reg_operand" ""))
(use (match_operand:TI 1 "memory_operand" ""))]
@@ -213,19 +213,19 @@
/* Use a temporary register to force getting an even register for the
lqarx/stqcrx. instructions. Normal optimizations will eliminate this
extra copy. */
- rtx pti = gen_reg_rtx (PTImode);
+ rtx pti = gen_reg_rtx (P128TImode);
emit_insn (gen_load_lockedpti (pti, operands[1]));
emit_move_insn (operands[0], gen_lowpart (TImode, pti));
DONE;
})
(define_insn "load_lockedpti"
- [(set (match_operand:PTI 0 "quad_int_reg_operand" "=&r")
- (unspec_volatile:PTI
+ [(set (match_operand:P128TI 0 "quad_int_reg_operand" "=&r")
+ (unspec_volatile:P128TI
[(match_operand:TI 1 "memory_operand" "Z")] UNSPECV_LL))]
"TARGET_SYNC_TI
&& !reg_mentioned_p (operands[0], operands[1])
- && quad_int_reg_operand (operands[0], PTImode)"
+ && quad_int_reg_operand (operands[0], P128TImode)"
"lqarx %0,%y1"
[(set_attr "type" "load_l")])
@@ -247,13 +247,13 @@
rtx op0 = operands[0];
rtx op1 = operands[1];
rtx op2 = operands[2];
- rtx pti_op1 = change_address (op1, PTImode, XEXP (op1, 0));
- rtx pti_op2 = gen_reg_rtx (PTImode);
+ rtx pti_op1 = change_address (op1, P128TImode, XEXP (op1, 0));
+ rtx pti_op2 = gen_reg_rtx (P128TImode);
/* Use a temporary register to force getting an even register for the
lqarx/stqcrx. instructions. Normal optimizations will eliminate this
extra copy. */
- emit_move_insn (pti_op2, gen_lowpart (PTImode, op2));
+ emit_move_insn (pti_op2, gen_lowpart (P128TImode, op2));
emit_insn (gen_store_conditionalpti (op0, pti_op1, pti_op2));
DONE;
})
@@ -261,9 +261,9 @@
(define_insn "store_conditionalpti"
[(set (match_operand:CC 0 "cc_reg_operand" "=x")
(unspec_volatile:CC [(const_int 0)] UNSPECV_SC))
- (set (match_operand:PTI 1 "memory_operand" "=Z")
- (match_operand:PTI 2 "quad_int_reg_operand" "r"))]
- "TARGET_SYNC_TI && quad_int_reg_operand (operands[2], PTImode)"
+ (set (match_operand:P128TI 1 "memory_operand" "=Z")
+ (match_operand:P128TI 2 "quad_int_reg_operand" "r"))]
+ "TARGET_SYNC_TI && quad_int_reg_operand (operands[2], P128TImode)"
"stqcx. %2,%y1"
[(set_attr "type" "store_c")])
===================================================================
@@ -234,7 +234,7 @@
(define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
; Any supported integer mode.
-(define_mode_iterator INT [QI HI SI DI TI PTI])
+(define_mode_iterator INT [QI HI SI DI TI P128TI])
; Any supported integer mode that fits in one register.
(define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
@@ -255,9 +255,9 @@
; (one with a '.') will compare; and the size used for arithmetic carries.
(define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
-; Iterator to add PTImode along with TImode (TImode can go in VSX registers,
-; PTImode is GPR only)
-(define_mode_iterator TI2 [TI PTI])
+; Iterator to add P128TImode along with TImode (TImode can go in VSX registers,
+; P128TImode is GPR only)
+(define_mode_iterator TI2 [TI P128TI])
; Any hardware-supported floating-point mode
(define_mode_iterator FP [
@@ -393,7 +393,7 @@
;; Mode iterator for logical operations on 128-bit types
(define_mode_iterator BOOL_128 [TI
- PTI
+ P128TI
(V16QI "TARGET_ALTIVEC")
(V8HI "TARGET_ALTIVEC")
(V4SI "TARGET_ALTIVEC")
@@ -409,7 +409,7 @@
;; Mode attribute for boolean operation register constraints for output
(define_mode_attr BOOL_REGS_OUTPUT [(TI "&r,r,r,wa,v")
- (PTI "&r,r,r")
+ (P128TI "&r,r,r")
(V16QI "wa,v,&?r,?r,?r")
(V8HI "wa,v,&?r,?r,?r")
(V4SI "wa,v,&?r,?r,?r")
@@ -419,7 +419,7 @@
;; Mode attribute for boolean operation register constraints for operand1
(define_mode_attr BOOL_REGS_OP1 [(TI "r,0,r,wa,v")
- (PTI "r,0,r")
+ (P128TI "r,0,r")
(V16QI "wa,v,r,0,r")
(V8HI "wa,v,r,0,r")
(V4SI "wa,v,r,0,r")
@@ -429,7 +429,7 @@
;; Mode attribute for boolean operation register constraints for operand2
(define_mode_attr BOOL_REGS_OP2 [(TI "r,r,0,wa,v")
- (PTI "r,r,0")
+ (P128TI "r,r,0")
(V16QI "wa,v,r,r,0")
(V8HI "wa,v,r,r,0")
(V4SI "wa,v,r,r,0")
@@ -441,7 +441,7 @@
;; for one_cmpl. To simplify things, we repeat the constraint where 0
;; is used for operand1 or operand2
(define_mode_attr BOOL_REGS_UNARY [(TI "r,0,0,wa,v")
- (PTI "r,0,0")
+ (P128TI "r,0,0")
(V16QI "wa,v,r,0,0")
(V8HI "wa,v,r,0,0")
(V4SI "wa,v,r,0,0")
@@ -453,7 +453,7 @@
;; For the 128-bit types, we never do AND immediate, but we need to
;; get the correct number of X's for the number of operands.
(define_mode_attr BOOL_REGS_AND_CR0 [(TI "X,X,X,X,X")
- (PTI "X,X,X")
+ (P128TI "X,X,X")
(V16QI "X,X,X,X,X")
(V8HI "X,X,X,X,X")
(V4SI "X,X,X,X,X")
@@ -8583,7 +8583,7 @@
(not:BOOL_128
(xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
(match_operand:BOOL_128 2 "vlogical_operand" ""))))]
- "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
+ "<MODE>mode == TImode || <MODE>mode == P128TImode || TARGET_P8_VECTOR"
"")
;; Rewrite nand into canonical form
@@ -8592,7 +8592,7 @@
(ior:BOOL_128
(not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" ""))
(not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))))]
- "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
+ "<MODE>mode == TImode || <MODE>mode == P128TImode || TARGET_P8_VECTOR"
"")
;; The canonical form is to have the negated element first, so we need to
@@ -8602,7 +8602,7 @@
(ior:BOOL_128
(not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))
(match_operand:BOOL_128 1 "vlogical_operand" "")))]
- "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
+ "<MODE>mode == TImode || <MODE>mode == P128TImode || TARGET_P8_VECTOR"
"")
;; 128-bit logical operations insns and split operations
@@ -10450,7 +10450,7 @@
FAIL;
}")
-;; TImode/PTImode is similar, except that we usually want to compute the
+;; TImode/P128TImode is similar, except that we usually want to compute the
;; address into a register and use lsi/stsi (the exception is during reload).
(define_insn "*mov<mode>_string"