From patchwork Thu Aug 22 19:20:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Segher Boessenkool X-Patchwork-Id: 1151767 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-507545-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="ZNRpGTk3"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46DvX34gNKz9sMr for ; Fri, 23 Aug 2019 05:21:04 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; q=dns; s=default; b=alLYWPntRhgJ yMIAcrrhEcdxljdisyrzH+6bfSkG4vgbeKyWP/OMe9paZ6esev08npWxEMGM1eHU vVVtlYG6riEcQDt5G2eLoSOGB8QF+ZTnRCgbKXP9d8Mvdib3g65/k+I4Pa5mBkF7 hCO3DupjPM0HavrFjDSi+YzRaswxCaY= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; s=default; bh=qIZi52Sv0cgQNzIN+c EHSviCYl4=; b=ZNRpGTk33UIjboPa51gh7X8gZzpAO2Qr+t+oE66A8EMzE7/Gk2 V+0e5X5lJURWtEhs/WBTp05+VIQZgAk7eK+oVx6BU/BS167OCKWOd9jD91su5G8I e6vxh013W/A2xxGVNOiFDKWFF7S7aiTykI91hxjpQZuXgRcqSsxuU5YaQ= Received: (qmail 77187 invoked by alias); 22 Aug 2019 19:20:56 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 77165 invoked by uid 89); 22 Aug 2019 19:20:55 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-14.9 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, MEDICAL_SUBJECT autolearn=ham version=3.3.1 spammy=membership, operates X-HELO: gcc1-power7.osuosl.org Received: from gcc1-power7.osuosl.org (HELO gcc1-power7.osuosl.org) (140.211.15.137) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 22 Aug 2019 19:20:52 +0000 Received: by gcc1-power7.osuosl.org (Postfix, from userid 10019) id A75C71240902; Thu, 22 Aug 2019 19:20:50 +0000 (UTC) From: Segher Boessenkool To: gcc-patches@gcc.gnu.org Cc: dje.gcc@gmail.com, Segher Boessenkool Subject: [PATCH 1/2] rs6000: Move various non-vector things out of altivec.md Date: Thu, 22 Aug 2019 19:20:47 +0000 Message-Id: <09c26a8006ac01916a17a5b6e7b50acf6497d5c4.1566482473.git.segher@kernel.crashing.org> X-IsSubscribed: yes Tested on powerpc64-linux {-m32,-m64}; committing to trunk. Segher 2019-08-22 Segher Boessenkool * config/rs6000/altivec.md (unspec): Delete UNSPEC_DARN, UNSPEC_DARN_32, UNSPEC_DARN_RAW, UNSPEC_CMPRB, UNSPEC_CMPRB2, UNSPEC_CMPEQB; move to... * config/rs6000/rs6000.md (unspec): ... here. * config/rs6000/altivec.md (darn_32, darn_raw, darn, cmprb, *cmprb_internal, setb_signed, setb_unsigned, cmprb2, *cmprb2_internal, cmpeqb, *cmpeqb_internal): Delete, move to... * config/rs6000/rs6000.md (darn_32, darn_raw, darn, cmprb, *cmprb_internal, setb_signed, setb_unsigned, cmprb2, *cmprb2_internal, cmpeqb, *cmpeqb_internal): ... here. --- gcc/config/rs6000/altivec.md | 223 ------------------------------------------ gcc/config/rs6000/rs6000.md | 224 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 224 insertions(+), 223 deletions(-) diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index 3a8cd76..6fa4d80 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -80,9 +80,6 @@ (define_c_enum "unspec" UNSPEC_VUPKHPX UNSPEC_VUPKLPX UNSPEC_CONVERT_4F32_8I16 - UNSPEC_DARN - UNSPEC_DARN_32 - UNSPEC_DARN_RAW UNSPEC_DST UNSPEC_DSTT UNSPEC_DSTST @@ -161,9 +158,6 @@ (define_c_enum "unspec" UNSPEC_BCDADD UNSPEC_BCDSUB UNSPEC_BCD_OVERFLOW - UNSPEC_CMPRB - UNSPEC_CMPRB2 - UNSPEC_CMPEQB UNSPEC_VRLMI UNSPEC_VRLNM ]) @@ -4107,223 +4101,6 @@ (define_insn "*bcd_test2" "bcd. %0,%1,%2,%3" [(set_attr "type" "vecsimple")]) -(define_insn "darn_32" - [(set (match_operand:SI 0 "register_operand" "=r") - (unspec:SI [(const_int 0)] UNSPEC_DARN_32))] - "TARGET_P9_MISC" - "darn %0,0" - [(set_attr "type" "integer")]) - -(define_insn "darn_raw" - [(set (match_operand:DI 0 "register_operand" "=r") - (unspec:DI [(const_int 0)] UNSPEC_DARN_RAW))] - "TARGET_P9_MISC && TARGET_64BIT" - "darn %0,2" - [(set_attr "type" "integer")]) - -(define_insn "darn" - [(set (match_operand:DI 0 "register_operand" "=r") - (unspec:DI [(const_int 0)] UNSPEC_DARN))] - "TARGET_P9_MISC && TARGET_64BIT" - "darn %0,1" - [(set_attr "type" "integer")]) - -;; Test byte within range. -;; -;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx -;; represents a byte whose value is ignored in this context and -;; vv, the least significant byte, holds the byte value that is to -;; be tested for membership within the range specified by operand 2. -;; The bytes of operand 2 are organized as xx:xx:hi:lo. -;; -;; Return in target register operand 0 a value of 1 if lo <= vv and -;; vv <= hi. Otherwise, set register operand 0 to 0. -;; -;; Though the instructions to which this expansion maps operate on -;; 64-bit registers, the current implementation only operates on -;; SI-mode operands as the high-order bits provide no information -;; that is not already available in the low-order bits. To avoid the -;; costs of data widening operations, future enhancements might allow -;; DI mode for operand 0 and/or might allow operand 1 to be QI mode. -(define_expand "cmprb" - [(set (match_dup 3) - (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") - (match_operand:SI 2 "gpc_reg_operand" "r")] - UNSPEC_CMPRB)) - (set (match_operand:SI 0 "gpc_reg_operand" "=r") - (if_then_else:SI (lt (match_dup 3) - (const_int 0)) - (const_int -1) - (if_then_else (gt (match_dup 3) - (const_int 0)) - (const_int 1) - (const_int 0))))] - "TARGET_P9_MISC" -{ - operands[3] = gen_reg_rtx (CCmode); -}) - -;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx -;; represents a byte whose value is ignored in this context and -;; vv, the least significant byte, holds the byte value that is to -;; be tested for membership within the range specified by operand 2. -;; The bytes of operand 2 are organized as xx:xx:hi:lo. -;; -;; Set bit 1 (the GT bit, 0x4) of CR register operand 0 to 1 if -;; lo <= vv and vv <= hi. Otherwise, set the GT bit to 0. The other -;; 3 bits of the target CR register are all set to 0. -(define_insn "*cmprb_internal" - [(set (match_operand:CC 0 "cc_reg_operand" "=y") - (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") - (match_operand:SI 2 "gpc_reg_operand" "r")] - UNSPEC_CMPRB))] - "TARGET_P9_MISC" - "cmprb %0,0,%1,%2" - [(set_attr "type" "logical")]) - -;; Set operand 0 register to -1 if the LT bit (0x8) of condition -;; register operand 1 is on. Otherwise, set operand 0 register to 1 -;; if the GT bit (0x4) of condition register operand 1 is on. -;; Otherwise, set operand 0 to 0. Note that the result stored into -;; register operand 0 is non-zero iff either the LT or GT bits are on -;; within condition register operand 1. -(define_insn "setb_signed" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r") - (if_then_else:SI (lt (match_operand:CC 1 "cc_reg_operand" "y") - (const_int 0)) - (const_int -1) - (if_then_else (gt (match_dup 1) - (const_int 0)) - (const_int 1) - (const_int 0))))] - "TARGET_P9_MISC" - "setb %0,%1" - [(set_attr "type" "logical")]) - -(define_insn "setb_unsigned" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r") - (if_then_else:SI (ltu (match_operand:CCUNS 1 "cc_reg_operand" "y") - (const_int 0)) - (const_int -1) - (if_then_else (gtu (match_dup 1) - (const_int 0)) - (const_int 1) - (const_int 0))))] - "TARGET_P9_MISC" - "setb %0,%1" - [(set_attr "type" "logical")]) - -;; Test byte within two ranges. -;; -;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx -;; represents a byte whose value is ignored in this context and -;; vv, the least significant byte, holds the byte value that is to -;; be tested for membership within the range specified by operand 2. -;; The bytes of operand 2 are organized as hi_1:lo_1:hi_2:lo_2. -;; -;; Return in target register operand 0 a value of 1 if (lo_1 <= vv and -;; vv <= hi_1) or if (lo_2 <= vv and vv <= hi_2). Otherwise, set register -;; operand 0 to 0. -;; -;; Though the instructions to which this expansion maps operate on -;; 64-bit registers, the current implementation only operates on -;; SI-mode operands as the high-order bits provide no information -;; that is not already available in the low-order bits. To avoid the -;; costs of data widening operations, future enhancements might allow -;; DI mode for operand 0 and/or might allow operand 1 to be QI mode. -(define_expand "cmprb2" - [(set (match_dup 3) - (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") - (match_operand:SI 2 "gpc_reg_operand" "r")] - UNSPEC_CMPRB2)) - (set (match_operand:SI 0 "gpc_reg_operand" "=r") - (if_then_else:SI (lt (match_dup 3) - (const_int 0)) - (const_int -1) - (if_then_else (gt (match_dup 3) - (const_int 0)) - (const_int 1) - (const_int 0))))] - "TARGET_P9_MISC" -{ - operands[3] = gen_reg_rtx (CCmode); -}) - -;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx -;; represents a byte whose value is ignored in this context and -;; vv, the least significant byte, holds the byte value that is to -;; be tested for membership within the ranges specified by operand 2. -;; The bytes of operand 2 are organized as hi_1:lo_1:hi_2:lo_2. -;; -;; Set bit 1 (the GT bit, 0x4) of CR register operand 0 to 1 if -;; (lo_1 <= vv and vv <= hi_1) or if (lo_2 <= vv and vv <= hi_2). -;; Otherwise, set the GT bit to 0. The other 3 bits of the target -;; CR register are all set to 0. -(define_insn "*cmprb2_internal" - [(set (match_operand:CC 0 "cc_reg_operand" "=y") - (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") - (match_operand:SI 2 "gpc_reg_operand" "r")] - UNSPEC_CMPRB2))] - "TARGET_P9_MISC" - "cmprb %0,1,%1,%2" - [(set_attr "type" "logical")]) - -;; Test byte membership within set of 8 bytes. -;; -;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx -;; represents a byte whose value is ignored in this context and -;; vv, the least significant byte, holds the byte value that is to -;; be tested for membership within the set specified by operand 2. -;; The bytes of operand 2 are organized as e0:e1:e2:e3:e4:e5:e6:e7. -;; -;; Return in target register operand 0 a value of 1 if vv equals one -;; of the values e0, e1, e2, e3, e4, e5, e6, or e7. Otherwise, set -;; register operand 0 to 0. Note that the 8 byte values held within -;; operand 2 need not be unique. -;; -;; Though the instructions to which this expansion maps operate on -;; 64-bit registers, the current implementation requires that operands -;; 0 and 1 have mode SI as the high-order bits provide no information -;; that is not already available in the low-order bits. To avoid the -;; costs of data widening operations, future enhancements might allow -;; DI mode for operand 0 and/or might allow operand 1 to be QI mode. -(define_expand "cmpeqb" - [(set (match_dup 3) - (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") - (match_operand:DI 2 "gpc_reg_operand" "r")] - UNSPEC_CMPEQB)) - (set (match_operand:SI 0 "gpc_reg_operand" "=r") - (if_then_else:SI (lt (match_dup 3) - (const_int 0)) - (const_int -1) - (if_then_else (gt (match_dup 3) - (const_int 0)) - (const_int 1) - (const_int 0))))] - "TARGET_P9_MISC && TARGET_64BIT" -{ - operands[3] = gen_reg_rtx (CCmode); -}) - -;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx -;; represents a byte whose value is ignored in this context and -;; vv, the least significant byte, holds the byte value that is to -;; be tested for membership within the set specified by operand 2. -;; The bytes of operand 2 are organized as e0:e1:e2:e3:e4:e5:e6:e7. -;; -;; Set bit 1 (the GT bit, 0x4) of CR register operand 0 to 1 if vv -;; equals one of the values e0, e1, e2, e3, e4, e5, e6, or e7. Otherwise, -;; set the GT bit to zero. The other 3 bits of the target CR register -;; are all set to 0. -(define_insn "*cmpeqb_internal" - [(set (match_operand:CC 0 "cc_reg_operand" "=y") - (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") - (match_operand:DI 2 "gpc_reg_operand" "r")] - UNSPEC_CMPEQB))] - "TARGET_P9_MISC && TARGET_64BIT" - "cmpeqb %0,%1,%2" - [(set_attr "type" "logical")]) - (define_expand "bcd_" [(parallel [(set (reg:CCFP CR6_REGNO) (compare:CCFP diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 9a7a1da..68cdf68 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -134,6 +134,12 @@ (define_c_enum "unspec" UNSPEC_LSQ UNSPEC_FUSION_GPR UNSPEC_STACK_CHECK + UNSPEC_DARN + UNSPEC_DARN_32 + UNSPEC_DARN_RAW + UNSPEC_CMPRB + UNSPEC_CMPRB2 + UNSPEC_CMPEQB UNSPEC_ADD_ROUND_TO_ODD UNSPEC_SUB_ROUND_TO_ODD UNSPEC_MUL_ROUND_TO_ODD @@ -14376,7 +14382,225 @@ (define_insn "*cmp_hw" "xscmpuqp %0,%1,%2" [(set_attr "type" "veccmp") (set_attr "size" "128")]) + +;; Miscellaneous ISA 3.0 (power9) instructions +(define_insn "darn_32" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(const_int 0)] UNSPEC_DARN_32))] + "TARGET_P9_MISC" + "darn %0,0" + [(set_attr "type" "integer")]) + +(define_insn "darn_raw" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(const_int 0)] UNSPEC_DARN_RAW))] + "TARGET_P9_MISC && TARGET_64BIT" + "darn %0,2" + [(set_attr "type" "integer")]) + +(define_insn "darn" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(const_int 0)] UNSPEC_DARN))] + "TARGET_P9_MISC && TARGET_64BIT" + "darn %0,1" + [(set_attr "type" "integer")]) + +;; Test byte within range. +;; +;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx +;; represents a byte whose value is ignored in this context and +;; vv, the least significant byte, holds the byte value that is to +;; be tested for membership within the range specified by operand 2. +;; The bytes of operand 2 are organized as xx:xx:hi:lo. +;; +;; Return in target register operand 0 a value of 1 if lo <= vv and +;; vv <= hi. Otherwise, set register operand 0 to 0. +;; +;; Though the instructions to which this expansion maps operate on +;; 64-bit registers, the current implementation only operates on +;; SI-mode operands as the high-order bits provide no information +;; that is not already available in the low-order bits. To avoid the +;; costs of data widening operations, future enhancements might allow +;; DI mode for operand 0 and/or might allow operand 1 to be QI mode. +(define_expand "cmprb" + [(set (match_dup 3) + (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "gpc_reg_operand" "r")] + UNSPEC_CMPRB)) + (set (match_operand:SI 0 "gpc_reg_operand" "=r") + (if_then_else:SI (lt (match_dup 3) + (const_int 0)) + (const_int -1) + (if_then_else (gt (match_dup 3) + (const_int 0)) + (const_int 1) + (const_int 0))))] + "TARGET_P9_MISC" +{ + operands[3] = gen_reg_rtx (CCmode); +}) + +;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx +;; represents a byte whose value is ignored in this context and +;; vv, the least significant byte, holds the byte value that is to +;; be tested for membership within the range specified by operand 2. +;; The bytes of operand 2 are organized as xx:xx:hi:lo. +;; +;; Set bit 1 (the GT bit, 0x4) of CR register operand 0 to 1 if +;; lo <= vv and vv <= hi. Otherwise, set the GT bit to 0. The other +;; 3 bits of the target CR register are all set to 0. +(define_insn "*cmprb_internal" + [(set (match_operand:CC 0 "cc_reg_operand" "=y") + (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "gpc_reg_operand" "r")] + UNSPEC_CMPRB))] + "TARGET_P9_MISC" + "cmprb %0,0,%1,%2" + [(set_attr "type" "logical")]) + +;; Set operand 0 register to -1 if the LT bit (0x8) of condition +;; register operand 1 is on. Otherwise, set operand 0 register to 1 +;; if the GT bit (0x4) of condition register operand 1 is on. +;; Otherwise, set operand 0 to 0. Note that the result stored into +;; register operand 0 is non-zero iff either the LT or GT bits are on +;; within condition register operand 1. +(define_insn "setb_signed" + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (if_then_else:SI (lt (match_operand:CC 1 "cc_reg_operand" "y") + (const_int 0)) + (const_int -1) + (if_then_else (gt (match_dup 1) + (const_int 0)) + (const_int 1) + (const_int 0))))] + "TARGET_P9_MISC" + "setb %0,%1" + [(set_attr "type" "logical")]) + +(define_insn "setb_unsigned" + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (if_then_else:SI (ltu (match_operand:CCUNS 1 "cc_reg_operand" "y") + (const_int 0)) + (const_int -1) + (if_then_else (gtu (match_dup 1) + (const_int 0)) + (const_int 1) + (const_int 0))))] + "TARGET_P9_MISC" + "setb %0,%1" + [(set_attr "type" "logical")]) + +;; Test byte within two ranges. +;; +;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx +;; represents a byte whose value is ignored in this context and +;; vv, the least significant byte, holds the byte value that is to +;; be tested for membership within the range specified by operand 2. +;; The bytes of operand 2 are organized as hi_1:lo_1:hi_2:lo_2. +;; +;; Return in target register operand 0 a value of 1 if (lo_1 <= vv and +;; vv <= hi_1) or if (lo_2 <= vv and vv <= hi_2). Otherwise, set register +;; operand 0 to 0. +;; +;; Though the instructions to which this expansion maps operate on +;; 64-bit registers, the current implementation only operates on +;; SI-mode operands as the high-order bits provide no information +;; that is not already available in the low-order bits. To avoid the +;; costs of data widening operations, future enhancements might allow +;; DI mode for operand 0 and/or might allow operand 1 to be QI mode. +(define_expand "cmprb2" + [(set (match_dup 3) + (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "gpc_reg_operand" "r")] + UNSPEC_CMPRB2)) + (set (match_operand:SI 0 "gpc_reg_operand" "=r") + (if_then_else:SI (lt (match_dup 3) + (const_int 0)) + (const_int -1) + (if_then_else (gt (match_dup 3) + (const_int 0)) + (const_int 1) + (const_int 0))))] + "TARGET_P9_MISC" +{ + operands[3] = gen_reg_rtx (CCmode); +}) + +;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx +;; represents a byte whose value is ignored in this context and +;; vv, the least significant byte, holds the byte value that is to +;; be tested for membership within the ranges specified by operand 2. +;; The bytes of operand 2 are organized as hi_1:lo_1:hi_2:lo_2. +;; +;; Set bit 1 (the GT bit, 0x4) of CR register operand 0 to 1 if +;; (lo_1 <= vv and vv <= hi_1) or if (lo_2 <= vv and vv <= hi_2). +;; Otherwise, set the GT bit to 0. The other 3 bits of the target +;; CR register are all set to 0. +(define_insn "*cmprb2_internal" + [(set (match_operand:CC 0 "cc_reg_operand" "=y") + (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "gpc_reg_operand" "r")] + UNSPEC_CMPRB2))] + "TARGET_P9_MISC" + "cmprb %0,1,%1,%2" + [(set_attr "type" "logical")]) + +;; Test byte membership within set of 8 bytes. +;; +;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx +;; represents a byte whose value is ignored in this context and +;; vv, the least significant byte, holds the byte value that is to +;; be tested for membership within the set specified by operand 2. +;; The bytes of operand 2 are organized as e0:e1:e2:e3:e4:e5:e6:e7. +;; +;; Return in target register operand 0 a value of 1 if vv equals one +;; of the values e0, e1, e2, e3, e4, e5, e6, or e7. Otherwise, set +;; register operand 0 to 0. Note that the 8 byte values held within +;; operand 2 need not be unique. +;; +;; Though the instructions to which this expansion maps operate on +;; 64-bit registers, the current implementation requires that operands +;; 0 and 1 have mode SI as the high-order bits provide no information +;; that is not already available in the low-order bits. To avoid the +;; costs of data widening operations, future enhancements might allow +;; DI mode for operand 0 and/or might allow operand 1 to be QI mode. +(define_expand "cmpeqb" + [(set (match_dup 3) + (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:DI 2 "gpc_reg_operand" "r")] + UNSPEC_CMPEQB)) + (set (match_operand:SI 0 "gpc_reg_operand" "=r") + (if_then_else:SI (lt (match_dup 3) + (const_int 0)) + (const_int -1) + (if_then_else (gt (match_dup 3) + (const_int 0)) + (const_int 1) + (const_int 0))))] + "TARGET_P9_MISC && TARGET_64BIT" +{ + operands[3] = gen_reg_rtx (CCmode); +}) + +;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx +;; represents a byte whose value is ignored in this context and +;; vv, the least significant byte, holds the byte value that is to +;; be tested for membership within the set specified by operand 2. +;; The bytes of operand 2 are organized as e0:e1:e2:e3:e4:e5:e6:e7. +;; +;; Set bit 1 (the GT bit, 0x4) of CR register operand 0 to 1 if vv +;; equals one of the values e0, e1, e2, e3, e4, e5, e6, or e7. Otherwise, +;; set the GT bit to zero. The other 3 bits of the target CR register +;; are all set to 0. +(define_insn "*cmpeqb_internal" + [(set (match_operand:CC 0 "cc_reg_operand" "=y") + (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:DI 2 "gpc_reg_operand" "r")] + UNSPEC_CMPEQB))] + "TARGET_P9_MISC && TARGET_64BIT" + "cmpeqb %0,%1,%2" + [(set_attr "type" "logical")]) (include "sync.md")