[rs6000] Update some Power9 latencies

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From: Pat Haugen <pthaugen@linux.vnet.ibm.com>
Subject: [PATCH, rs6000] Update some Power9 latencies
To: GCC Patches <gcc-patches@gcc.gnu.org>
Cc: Segher Boessenkool <segher@gcc.gnu.org>,
	David Edelsohn <dje.gcc@gmail.com>
Date: Wed, 18 Jan 2017 12:34:00 -0600
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Commit Message

Pat Haugen Jan. 18, 2017, 6:34 p.m. UTC

The following patch updates a few latencies in the Power9 machine description. Bootstrap/regtest on powerpc64le with no new regressions. Ok for trunk?

-Pat

2017-01-18  Pat Haugen  <pthaugen@us.ibm.com>

	* config/rs6000/power9.md (power9-alu): Remove 'cmp' type and add
	define_bypass for CR latency.
	(power9-cracked-alu): Update bypass latency and remove power9-branch.
	(power9-alu2): Add define_bypass for CR latency.
	(power9-cmp): New.
	(power9-mul): Update insn latency.
	(power9-mul-compare): Update insn latency, bypass latency and remove
	power9-branch.

Comments

Segher Boessenkool Jan. 18, 2017, 11:33 p.m. UTC | #1

On Wed, Jan 18, 2017 at 12:34:00PM -0600, Pat Haugen wrote:
> The following patch updates a few latencies in the Power9 machine description. Bootstrap/regtest on powerpc64le with no new regressions. Ok for trunk?

Okay, thanks!


Segher


> 2017-01-18  Pat Haugen  <pthaugen@us.ibm.com>
> 
> 	* config/rs6000/power9.md (power9-alu): Remove 'cmp' type and add
> 	define_bypass for CR latency.
> 	(power9-cracked-alu): Update bypass latency and remove power9-branch.
> 	(power9-alu2): Add define_bypass for CR latency.
> 	(power9-cmp): New.
> 	(power9-mul): Update insn latency.
> 	(power9-mul-compare): Update insn latency, bypass latency and remove
> 	power9-branch.

Index: config/rs6000/power9.md
===================================================================
--- config/rs6000/power9.md	(revision 244537)
+++ config/rs6000/power9.md	(working copy)
@@ -243,11 +243,14 @@  (define_insn_reservation "power9-sync" 4
 
 ; Most ALU insns are simple 2 cycle, including record form
 (define_insn_reservation "power9-alu" 2
-  (and (ior (eq_attr "type" "add,cmp,exts,integer,logical,isel")
+  (and (ior (eq_attr "type" "add,exts,integer,logical,isel")
 	    (and (eq_attr "type" "insert,shift")
 		 (eq_attr "dot" "no")))
        (eq_attr "cpu" "power9"))
   "DU_any_power9,VSU_power9")
+; 5 cycle CR latency
+(define_bypass 5 "power9-alu"
+		 "power9-crlogical,power9-mfcr,power9-mfcrf")
 
 ; Record form rotate/shift are cracked
 (define_insn_reservation "power9-cracked-alu" 2
@@ -255,14 +258,23 @@  (define_insn_reservation "power9-cracked
        (eq_attr "dot" "yes")
        (eq_attr "cpu" "power9"))
   "DU_C2_power9,VSU_power9")
-; 4 cycle CR latency
-(define_bypass 4 "power9-cracked-alu"
-		 "power9-crlogical,power9-mfcr,power9-mfcrf,power9-branch")
+; 7 cycle CR latency
+(define_bypass 7 "power9-cracked-alu"
+		 "power9-crlogical,power9-mfcr,power9-mfcrf")
 
 (define_insn_reservation "power9-alu2" 3
   (and (eq_attr "type" "cntlz,popcnt,trap")
        (eq_attr "cpu" "power9"))
   "DU_any_power9,VSU_power9")
+; 6 cycle CR latency
+(define_bypass 6 "power9-alu2"
+		 "power9-crlogical,power9-mfcr,power9-mfcrf")
+
+(define_insn_reservation "power9-cmp" 2
+  (and (eq_attr "type" "cmp")
+       (eq_attr "cpu" "power9"))
+  "DU_any_power9,VSU_power9")
+
 
 ; Treat 'two' and 'three' types as 2 or 3 way cracked
 (define_insn_reservation "power9-two" 4
@@ -275,20 +287,20 @@  (define_insn_reservation "power9-three"
        (eq_attr "cpu" "power9"))
   "DU_C3_power9,VSU_power9")
 
-(define_insn_reservation "power9-mul" 4
+(define_insn_reservation "power9-mul" 5
   (and (eq_attr "type" "mul")
        (eq_attr "dot" "no")
        (eq_attr "cpu" "power9"))
   "DU_any_power9,VSU_power9")
 
-(define_insn_reservation "power9-mul-compare" 4
+(define_insn_reservation "power9-mul-compare" 5
   (and (eq_attr "type" "mul")
        (eq_attr "dot" "yes")
        (eq_attr "cpu" "power9"))
   "DU_C2_power9,VSU_power9")
-; 6 cycle CR latency
-(define_bypass 6 "power9-mul-compare"
-		 "power9-crlogical,power9-mfcr,power9-mfcrf,power9-branch")
+; 10 cycle CR latency
+(define_bypass 10 "power9-mul-compare"
+		 "power9-crlogical,power9-mfcr,power9-mfcrf")
 
 ; Fixed point divides reserve the divide units for a minimum of 8 cycles
 (define_insn_reservation "power9-idiv" 16