From patchwork Tue Jun 4 23:20:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Segher Boessenkool X-Patchwork-Id: 1110259 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-502341-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="Wa9DkGSq"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45JSbj3tPrz9s6w for ; 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4 Jun 2019 23:21:01 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-16.1 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3 autolearn=ham version=3.3.1 spammy= X-HELO: gcc1-power7.osuosl.org Received: from gcc1-power7.osuosl.org (HELO gcc1-power7.osuosl.org) (140.211.15.137) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 04 Jun 2019 23:21:00 +0000 Received: by gcc1-power7.osuosl.org (Postfix, from userid 10019) id B36BF12406A5; Tue, 4 Jun 2019 23:20:58 +0000 (UTC) From: Segher Boessenkool To: gcc-patches@gcc.gnu.org Cc: dje.gcc@gmail.com, Segher Boessenkool Subject: [PATCH 02/12] rs6000: Simplify for VSX_W Date: Tue, 4 Jun 2019 23:20:28 +0000 Message-Id: <0542f96dfccc39e9233516d296bbf3799982aea0.1559685816.git.segher@kernel.crashing.org> In-Reply-To: References: In-Reply-To: References: X-IsSubscribed: yes When used in VSX_W, is always just "wa". 2019-06-04 Segher Boessenkool * config/rs6000/vsx.md: Replace all that are used with VSX_W with just "wa". --- gcc/config/rs6000/vsx.md | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 11e50bf..d349091 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -468,7 +468,7 @@ (define_insn_and_split "*vsx_le_perm_load_" (set_attr "length" "8")]) (define_insn_and_split "*vsx_le_perm_load_" - [(set (match_operand:VSX_W 0 "vsx_register_operand" "=") + [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa") (match_operand:VSX_W 1 "indexed_or_indirect_operand" "Z"))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" "#" @@ -705,7 +705,7 @@ (define_split (define_insn "*vsx_le_perm_store_" [(set (match_operand:VSX_W 0 "indexed_or_indirect_operand" "=Z") - (match_operand:VSX_W 1 "vsx_register_operand" "+"))] + (match_operand:VSX_W 1 "vsx_register_operand" "+wa"))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" "#" [(set_attr "type" "vecstore") @@ -2983,9 +2983,9 @@ (define_insn "*vsx_xxpermdi2_le_" [(set_attr "type" "vecperm")]) (define_insn "*vsx_xxpermdi4_le_" - [(set (match_operand:VSX_W 0 "vsx_register_operand" "=") + [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa") (vec_select:VSX_W - (match_operand:VSX_W 1 "vsx_register_operand" "") + (match_operand:VSX_W 1 "vsx_register_operand" "wa") (parallel [(const_int 2) (const_int 3) (const_int 0) (const_int 1)])))] "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (mode)" @@ -3032,7 +3032,7 @@ (define_insn "*vsx_lxvd2x2_le_" [(set_attr "type" "vecload")]) (define_insn "*vsx_lxvd2x4_le_" - [(set (match_operand:VSX_W 0 "vsx_register_operand" "=") + [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa") (vec_select:VSX_W (match_operand:VSX_W 1 "memory_operand" "Z") (parallel [(const_int 2) (const_int 3) @@ -3083,7 +3083,7 @@ (define_insn "*vsx_stxvd2x2_le_" (define_insn "*vsx_stxvd2x4_le_" [(set (match_operand:VSX_W 0 "memory_operand" "=Z") (vec_select:VSX_W - (match_operand:VSX_W 1 "vsx_register_operand" "") + (match_operand:VSX_W 1 "vsx_register_operand" "wa") (parallel [(const_int 2) (const_int 3) (const_int 0) (const_int 1)])))] "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (mode) && !TARGET_P9_VECTOR" @@ -4156,10 +4156,10 @@ (define_insn_and_split "vsx_splat_v4sf" ;; V4SF/V4SI splat from a vector element (define_insn "vsx_xxspltw_" - [(set (match_operand:VSX_W 0 "vsx_register_operand" "=") + [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa") (vec_duplicate:VSX_W (vec_select: - (match_operand:VSX_W 1 "vsx_register_operand" "") + (match_operand:VSX_W 1 "vsx_register_operand" "wa") (parallel [(match_operand:QI 2 "u5bit_cint_operand" "n")]))))] "VECTOR_MEM_VSX_P (mode)" @@ -4172,8 +4172,8 @@ (define_insn "vsx_xxspltw_" [(set_attr "type" "vecperm")]) (define_insn "vsx_xxspltw__direct" - [(set (match_operand:VSX_W 0 "vsx_register_operand" "=") - (unspec:VSX_W [(match_operand:VSX_W 1 "vsx_register_operand" "") + [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa") + (unspec:VSX_W [(match_operand:VSX_W 1 "vsx_register_operand" "wa") (match_operand:QI 2 "u5bit_cint_operand" "i")] UNSPEC_VSX_XXSPLTW))] "VECTOR_MEM_VSX_P (mode)" @@ -4208,11 +4208,11 @@ (define_insn "vsx_xxspltd_" ;; V4SF/V4SI interleave (define_insn "vsx_xxmrghw_" - [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa,?") + [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa") (vec_select:VSX_W (vec_concat: - (match_operand:VSX_W 1 "vsx_register_operand" "wa,") - (match_operand:VSX_W 2 "vsx_register_operand" "wa,")) + (match_operand:VSX_W 1 "vsx_register_operand" "wa") + (match_operand:VSX_W 2 "vsx_register_operand" "wa")) (parallel [(const_int 0) (const_int 4) (const_int 1) (const_int 5)])))] "VECTOR_MEM_VSX_P (mode)" @@ -4225,11 +4225,11 @@ (define_insn "vsx_xxmrghw_" [(set_attr "type" "vecperm")]) (define_insn "vsx_xxmrglw_" - [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa,?") + [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa") (vec_select:VSX_W (vec_concat: - (match_operand:VSX_W 1 "vsx_register_operand" "wa,") - (match_operand:VSX_W 2 "vsx_register_operand" "wa,?")) + (match_operand:VSX_W 1 "vsx_register_operand" "wa") + (match_operand:VSX_W 2 "vsx_register_operand" "wa")) (parallel [(const_int 2) (const_int 6) (const_int 3) (const_int 7)])))] "VECTOR_MEM_VSX_P (mode)"